Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	696304396	0	0	625
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	696304396	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	696304396	696158922	0	0
tb.dut.CheckAccuCntDw	0	0	625	625	0	0
tb.dut.CheckEscCntDw	0	0	625	625	0	0
tb.dut.CheckNAlerts	0	0	625	625	0	0
tb.dut.CheckNClasses	0	0	625	625	0	0
tb.dut.CheckNEscSev	0	0	625	625	0	0
tb.dut.CrashdumpKnownO_A	0	0	696304396	696158922	0	0
tb.dut.EdnKnownO_A	0	0	696304396	696158922	0	0
tb.dut.EscPKnownO_A	0	0	696304396	696158922	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	696304396	60	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	696304396	60	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	696304396	60	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	696304396	60	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	696304396	60	0	0
tb.dut.IrqAKnownO_A	0	0	696304396	696158922	0	0
tb.dut.IrqBKnownO_A	0	0	696304396	696158922	0	0
tb.dut.IrqCKnownO_A	0	0	696304396	696158922	0	0
tb.dut.IrqDKnownO_A	0	0	696304396	696158922	0	0
tb.dut.TlAReadyKnownO_A	0	0	696304396	696158922	0	0
tb.dut.TlDValidKnownO_A	0	0	696304396	696158922	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	722071950	3793616	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	722071950	9757	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	722071950	9686	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	722071950	9633	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	722071950	11923	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	722071950	11515	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	722071950	9708	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	722071950	10720	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	722071950	8455	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	722071950	11029	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	722071950	8666	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	722071950	10982	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	722071950	9669	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	722071950	8614	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	722071950	8548	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	722071950	8497	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	722071950	8872	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	722071950	9672	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	722071950	9054	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	722071950	10726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	722071950	9592	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	722071950	9715	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	722071950	8455	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	722071950	9635	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	722071950	9240	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	722071950	10226	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	722071950	9097	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	722071950	10939	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	722071950	10019	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	722071950	10291	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	722071950	10488	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	722071950	8379	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	722071950	11607	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	722071950	9794	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	722071950	8338	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	722071950	11035	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	722071950	9900	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	722071950	11480	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	722071950	10401	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	722071950	9577	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	722071950	8508	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	722071950	10211	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	722071950	11893	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	722071950	9702	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	722071950	8530	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	722071950	10988	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	722071950	9314	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	722071950	9528	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	722071950	8844	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	722071950	8400	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	722071950	9876	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	722071950	9207	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	722071950	8685	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	722071950	8950	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	722071950	9395	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	722071950	9710	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	722071950	9994	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	722071950	8390	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	722071950	9488	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	722071950	8359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	722071950	11939	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	722071950	10569	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	722071950	9079	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	722071950	9384	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	722071950	8419	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	722071950	8568	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	722071950	11710	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	722071950	10264	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	722071950	9711	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	722071950	10628	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	722071950	16288	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	722071950	10513	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	722071950	9514	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	722071950	8525	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	722071950	11330	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	722071950	10701	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	722071950	12012	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	722071950	9724	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	722071950	9804	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	696304396	2107	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	696304396	222076	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	696304396	370259385	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	696304396	185	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	696304396	840	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	696304396	47	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	696304396	392	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	696185672	267033213	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	696304396	913	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	696304396	892	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	696304396	874	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	696304396	863	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	696304396	1921	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	696304396	174098	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	696304396	1831	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	696304396	43	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	696304396	1048	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	696304396	868	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	696184753	696115299	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	696304396	696158922	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	696304396	8190	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	696304396	163694	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	696304396	400505284	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	696304396	215	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	696304396	504	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	696304396	18	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	696304396	225	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	696185672	301839439	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	696304396	561	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	696304396	553	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	696304396	546	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	696304396	536	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	696304396	1583	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	696304396	118418	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	696304396	1517	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	696304396	48	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	696304396	1068	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	696304396	888	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	696184753	696115299	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	696304396	696158922	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	696304396	1370	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	696304396	199095	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	696304396	378947528	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	696304396	220	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	696304396	486	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	696304396	21	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	696304396	215	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	696185672	312270379	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	696304396	553	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	696304396	542	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	696304396	534	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	696304396	525	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	696304396	1693	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	696304396	131096	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	696304396	1621	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	696304396	50	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	696304396	1099	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	696304396	919	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	696184753	696115299	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	696304396	696158922	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	696304396	60	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	696304396	2756	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	696304396	199206	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	696304396	423250916	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	696304396	222	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	696304396	459	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	696304396	30	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	696304396	194	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	696185672	318732857	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	696304396	531	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	696304396	522	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	696304396	517	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	696304396	511	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	696304396	1494	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	696304396	127013	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	696304396	1415	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	696304396	47	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	696304396	1070	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	696304396	890	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	696184753	696115299	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	696304396	696158922	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	722071950	149690070	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	722071950	721390360	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	722071950	721390360	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	722071950	187064233	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	722071950	721390360	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	722071950	721390360	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0
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tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	830	830	0	0

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