Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.22	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	4	40	90.91

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	4	40	90.91	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	146	1			T17	1		T6	1		T23	1
index[0x1]	178	1			T2	1		T5	1		T17	1
index[0x2]	159	1			T17	1		T7	2		T8	1
index[0x3]	174	1			T2	1		T17	2		T19	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	219	1			T6	1		T23	2		T20	1
lens_less_than_1000[1]	139	1			T2	1		T5	1		T17	1
lens_less_than_1000[2]	80	1			T9	1		T23	1		T54	1
lens_less_than_1000[3]	69	1			T17	2		T20	1		T34	1
lens_less_than_1000[4]	69	1			T17	2		T8	1		T24	2
lens_less_than_1000[5]	20	1			T23	1		T70	1		T259	1
lens_less_than_1000[6]	23	1			T260	1		T261	1		T262	1
lens_less_than_1000[7]	16	1			T16	2		T40	1		T94	1
lens_less_than_1000[8]	10	1			T2	1		T36	2		T263	1
lens_less_than_1000[9]	1	1			T94	1		-	-		-	-
len_2	11	1			T19	1		T107	1		T108	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	4	40	90.91	4

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[7]]	0	1	1
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	55	1			T6	1		T23	1		T20	1
index[0x0]	lens_less_than_1000[1]	34	1			T17	1		T220	1		T37	1
index[0x0]	lens_less_than_1000[2]	16	1			T72	1		T44	2		T95	2
index[0x0]	lens_less_than_1000[3]	16	1			T20	1		T34	1		T24	1
index[0x0]	lens_less_than_1000[4]	11	1			T264	1		T85	1		T43	1
index[0x0]	lens_less_than_1000[5]	6	1			T70	1		T79	1		T254	1
index[0x0]	lens_less_than_1000[6]	5	1			T262	1		T94	1		T265	1
index[0x0]	lens_less_than_1000[8]	2	1			T266	1		T267	1		-	-
index[0x0]	len_2	1	1			T108	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	42	1			T21	3		T60	2		T26	1
index[0x1]	lens_less_than_1000[1]	51	1			T2	1		T5	1		T24	1
index[0x1]	lens_less_than_1000[2]	21	1			T9	1		T23	1		T54	1
index[0x1]	lens_less_than_1000[3]	23	1			T17	1		T43	2		T268	1
index[0x1]	lens_less_than_1000[4]	16	1			T85	1		T269	1		T108	1
index[0x1]	lens_less_than_1000[5]	3	1			T185	1		T270	1		T271	1
index[0x1]	lens_less_than_1000[6]	7	1			T260	1		T95	3		T272	1
index[0x1]	lens_less_than_1000[7]	10	1			T16	2		T40	1		T94	1
index[0x1]	lens_less_than_1000[8]	2	1			T36	1		T263	1		-	-
index[0x1]	len_2	3	1			T107	1		T108	1		T273	1
index[0x2]	lens_less_than_1000[0]	62	1			T21	1		T24	2		T92	1
index[0x2]	lens_less_than_1000[1]	25	1			T7	2		T83	1		T36	1
index[0x2]	lens_less_than_1000[2]	21	1			T26	1		T93	1		T37	1
index[0x2]	lens_less_than_1000[3]	15	1			T83	1		T26	1		T86	1
index[0x2]	lens_less_than_1000[4]	16	1			T17	1		T8	1		T91	1
index[0x2]	lens_less_than_1000[5]	6	1			T259	1		T253	2		T274	1
index[0x2]	lens_less_than_1000[6]	9	1			T261	1		T78	1		T275	1
index[0x2]	lens_less_than_1000[7]	1	1			T276	1		-	-		-	-
index[0x2]	lens_less_than_1000[8]	2	1			T50	2		-	-		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T94	1		-	-		-	-
index[0x2]	len_2	1	1			T277	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	60	1			T23	1		T278	1		T69	1
index[0x3]	lens_less_than_1000[1]	29	1			T16	1		T37	1		T193	1
index[0x3]	lens_less_than_1000[2]	22	1			T24	2		T26	1		T72	1
index[0x3]	lens_less_than_1000[3]	15	1			T17	1		T44	1		T79	1
index[0x3]	lens_less_than_1000[4]	26	1			T17	1		T24	2		T37	4
index[0x3]	lens_less_than_1000[5]	5	1			T23	1		T105	1		T50	1
index[0x3]	lens_less_than_1000[6]	2	1			T279	1		T185	1		-	-
index[0x3]	lens_less_than_1000[7]	5	1			T50	3		T253	1		T280	1
index[0x3]	lens_less_than_1000[8]	4	1			T2	1		T36	1		T248	1
index[0x3]	len_2	6	1			T19	1		T281	4		T230	1