Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	6	34	85.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	6	34	85.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	43	1			T72	2		T73	2		T77	1
class_index[0x1]	48	1			T20	1		T21	2		T22	1
class_index[0x2]	50	1			T21	2		T72	1		T40	1
class_index[0x3]	47	1			T20	1		T35	1		T69	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	76	1			T35	1		T69	1		T72	3
intr_timeout_cnt[1]	47	1			T21	1		T70	1		T75	2
intr_timeout_cnt[2]	16	1			T20	1		T22	1		T71	1
intr_timeout_cnt[3]	9	1			T21	1		T69	1		T73	1
intr_timeout_cnt[4]	8	1			T40	1		T241	1		T242	1
intr_timeout_cnt[5]	3	1			T21	1		T243	1		T229	1
intr_timeout_cnt[6]	7	1			T21	1		T73	1		T244	1
intr_timeout_cnt[7]	13	1			T74	2		T78	3		T50	1
intr_timeout_cnt[8]	5	1			T20	1		T50	1		T101	1
intr_timeout_cnt[9]	4	1			T245	1		T82	1		T246	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	6	34	85.00	6

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[5] , intr_timeout_cnt[6]]	--	--	2
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	20	1			T72	2		T73	1		T77	1
class_index[0x0]	intr_timeout_cnt[1]	6	1			T47	1		T80	1		T247	1
class_index[0x0]	intr_timeout_cnt[2]	1	1			T73	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[3]	2	1			T52	1		T230	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	4	1			T242	1		T248	1		T249	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T229	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	7	1			T78	3		T50	1		T250	1
class_index[0x0]	intr_timeout_cnt[9]	2	1			T246	1		T251	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	13	1			T73	1		T94	1		T47	1
class_index[0x1]	intr_timeout_cnt[1]	22	1			T21	1		T70	1		T75	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T20	1		T22	1		T71	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T21	1		T69	1		T73	1
class_index[0x1]	intr_timeout_cnt[4]	1	1			T250	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T74	1		T252	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T101	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	26	1			T72	1		T43	1		T44	1
class_index[0x2]	intr_timeout_cnt[1]	7	1			T50	1		T97	1		T253	1
class_index[0x2]	intr_timeout_cnt[2]	2	1			T76	1		T251	1		-	-
class_index[0x2]	intr_timeout_cnt[3]	3	1			T75	1		T46	1		T254	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T40	1		T255	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	2	1			T21	1		T243	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	5	1			T21	1		T73	1		T244	1
class_index[0x2]	intr_timeout_cnt[7]	1	1			T256	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T257	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T82	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	17	1			T35	1		T69	1		T44	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T75	1		T46	1		T81	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T73	1		T75	1		T76	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T78	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	1	1			T241	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T229	1		T258	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	3	1			T74	1		T246	2		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T20	1		T50	1		T256	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T245	1		-	-		-	-