Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	376658	1			T1	27		T2	1259		T3	53
all_values[1]	376658	1			T1	27		T2	1259		T3	53
all_values[2]	376658	1			T1	27		T2	1259		T3	53
all_values[3]	376658	1			T1	27		T2	1259		T3	53

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

748703

1

T1

60

T2

2510

T5

10

auto[1]

757929

1

T1

48

T2

2526

T3

212

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

902005

1

T1

56

T2

3258

T3

177

auto[1]

604627

1

T1

52

T2

1778

T3

35

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	106829	1			T1	10		T2	368		T5	1
all_values[0]	auto[0]	auto[1]	80325	1			T1	9		T2	228		T5	1
all_values[0]	auto[1]	auto[0]	108676	1			T1	4		T2	421		T3	44
all_values[0]	auto[1]	auto[1]	80828	1			T1	4		T2	242		T3	9
all_values[1]	auto[0]	auto[0]	113855	1			T1	3		T2	482		T5	3
all_values[1]	auto[0]	auto[1]	73126	1			T1	3		T2	146		T5	2
all_values[1]	auto[1]	auto[0]	115902	1			T1	11		T2	480		T3	53
all_values[1]	auto[1]	auto[1]	73775	1			T1	10		T2	151		T17	216
all_values[2]	auto[0]	auto[0]	114343	1			T1	9		T2	417		T5	2
all_values[2]	auto[0]	auto[1]	72608	1			T1	8		T2	248		T5	1
all_values[2]	auto[1]	auto[0]	116287	1			T1	5		T2	382		T3	44
all_values[2]	auto[1]	auto[1]	73420	1			T1	5		T2	212		T3	9
all_values[3]	auto[0]	auto[0]	112592	1			T1	9		T2	349		T17	232
all_values[3]	auto[0]	auto[1]	75025	1			T1	9		T2	272		T17	215
all_values[3]	auto[1]	auto[0]	113521	1			T1	5		T2	359		T3	36
all_values[3]	auto[1]	auto[1]	75520	1			T1	4		T2	279		T3	17