Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	376658	1			T1	27		T2	1259		T3	53
all_pins[1]	376658	1			T1	27		T2	1259		T3	53
all_pins[2]	376658	1			T1	27		T2	1259		T3	53
all_pins[3]	376658	1			T1	27		T2	1259		T3	53

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1203089	1			T1	85		T2	4152		T3	177
values[0x1]	303543	1			T1	23		T2	884		T3	35
transitions[0x0=>0x1]	201497	1			T1	17		T2	684		T3	35
transitions[0x1=>0x0]	201739	1			T1	17		T2	685		T3	35

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	295830	1			T1	23		T2	1017		T3	44
all_pins[0]	values[0x1]	80828	1			T1	4		T2	242		T3	9
all_pins[0]	transitions[0x0=>0x1]	80225	1			T1	4		T2	241		T3	9
all_pins[0]	transitions[0x1=>0x0]	75159	1			T1	4		T2	279		T3	17
all_pins[1]	values[0x0]	302883	1			T1	17		T2	1108		T3	53
all_pins[1]	values[0x1]	73775	1			T1	10		T2	151		T17	216
all_pins[1]	transitions[0x0=>0x1]	39702	1			T1	8		T2	86		T17	114
all_pins[1]	transitions[0x1=>0x0]	46755	1			T1	2		T2	177		T3	9
all_pins[2]	values[0x0]	303238	1			T1	22		T2	1047		T3	44
all_pins[2]	values[0x1]	73420	1			T1	5		T2	212		T3	9
all_pins[2]	transitions[0x0=>0x1]	39678	1			T1	2		T2	171		T3	9
all_pins[2]	transitions[0x1=>0x0]	40033	1			T1	7		T2	110		T17	110
all_pins[3]	values[0x0]	301138	1			T1	23		T2	980		T3	36
all_pins[3]	values[0x1]	75520	1			T1	4		T2	279		T3	17
all_pins[3]	transitions[0x0=>0x1]	41892	1			T1	3		T2	186		T3	17
all_pins[3]	transitions[0x1=>0x0]	39792	1			T1	4		T2	119		T3	9