Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	95565	1			T7	91		T19	376		T14	838
accum_cnt_1000	240499	1			T2	773		T17	943		T6	1180
accum_cnt_100	25323	1			T2	90		T17	239		T6	92
accum_cnt_50	71384	1			T1	28		T2	59		T3	18
accum_cnt_10	173791	1			T1	16		T2	1881		T3	55
accum_cnt_0	460572	1			T1	60		T2	941		T3	79

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	277714	1			T1	26		T2	936		T3	38
class_index[0x1]	277714	1			T1	26		T2	936		T3	38
class_index[0x2]	277714	1			T1	26		T2	936		T3	38
class_index[0x3]	277714	1			T1	26		T2	936		T3	38

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22373	1			T19	376		T20	240		T25	371
class_index[0x0]	accum_cnt_1000	62522	1			T17	259		T6	1180		T19	446
class_index[0x0]	accum_cnt_100	7522	1			T17	48		T6	92		T7	2
class_index[0x0]	accum_cnt_50	23510	1			T1	18		T17	52		T6	73
class_index[0x0]	accum_cnt_10	46143	1			T1	4		T2	930		T3	36
class_index[0x0]	accum_cnt_0	103092	1			T1	4		T2	6		T3	2
class_index[0x1]	accum_cnt_2000	22910	1			T23	95		T25	489		T21	470
class_index[0x1]	accum_cnt_1000	56042	1			T17	318		T16	410		T23	507
class_index[0x1]	accum_cnt_100	5566	1			T17	73		T16	156		T23	32
class_index[0x1]	accum_cnt_50	19779	1			T17	56		T16	119		T67	4
class_index[0x1]	accum_cnt_10	37391	1			T2	1		T5	2		T17	14
class_index[0x1]	accum_cnt_0	127033	1			T1	26		T2	935		T3	38
class_index[0x2]	accum_cnt_2000	26264	1			T14	410		T20	89		T21	384
class_index[0x2]	accum_cnt_1000	64826	1			T2	773		T17	290		T19	36
class_index[0x2]	accum_cnt_100	6904	1			T2	90		T17	78		T19	26
class_index[0x2]	accum_cnt_50	12794	1			T1	10		T2	59		T3	18
class_index[0x2]	accum_cnt_10	43784	1			T1	12		T2	14		T3	18
class_index[0x2]	accum_cnt_0	113033	1			T1	4		T3	2		T5	1
class_index[0x3]	accum_cnt_2000	24018	1			T7	91		T14	428		T15	693
class_index[0x3]	accum_cnt_1000	57109	1			T17	76		T7	549		T14	606
class_index[0x3]	accum_cnt_100	5331	1			T17	40		T7	33		T14	32
class_index[0x3]	accum_cnt_50	15301	1			T17	48		T7	36		T14	25
class_index[0x3]	accum_cnt_10	46473	1			T2	936		T3	1		T17	281
class_index[0x3]	accum_cnt_0	117414	1			T1	26		T3	37		T5	3