Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4643	1			T10	1		T56	21		T286	1
alert[0x1]	11278	1			T9	1		T26	230		T69	201
alert[0x2]	11177	1			T9	1		T21	2		T191	120
alert[0x3]	2346	1			T56	37		T26	200		T37	29
alert[0x4]	5682	1			T23	254		T21	300		T26	110
alert[0x5]	5971	1			T23	1615		T21	2		T56	8
alert[0x6]	2911	1			T17	18		T9	1		T23	17
alert[0x7]	7253	1			T191	18		T188	2		T69	8
alert[0x8]	8424	1			T10	1		T68	5		T23	828
alert[0x9]	12608	1			T16	10		T10	1		T21	26
alert[0xa]	4940	1			T56	1742		T190	321		T74	2
alert[0xb]	4479	1			T17	3		T16	11		T26	1262
alert[0xc]	1496	1			T9	1		T16	5		T68	65
alert[0xd]	9371	1			T10	1		T21	75		T191	395
alert[0xe]	8582	1			T3	1		T35	299		T69	305
alert[0xf]	2952	1			T3	1		T17	1		T9	1
alert[0x10]	1516	1			T9	1		T16	73		T21	8
alert[0x11]	5367	1			T3	2		T10	1		T21	43
alert[0x12]	5388	1			T3	1		T21	356		T24	4
alert[0x13]	4214	1			T3	1		T57	1		T24	104
alert[0x14]	10089	1			T3	1		T8	1		T21	241
alert[0x15]	1870	1			T9	2		T56	10		T191	56
alert[0x16]	6326	1			T3	2		T56	98		T191	157
alert[0x17]	3652	1			T16	11		T10	1		T68	1
alert[0x18]	9354	1			T17	6		T16	425		T56	112
alert[0x19]	3277	1			T23	394		T191	175		T35	18
alert[0x1a]	4696	1			T3	1		T56	8		T191	17
alert[0x1b]	7170	1			T16	7		T23	11		T21	1
alert[0x1c]	5451	1			T56	4		T191	34		T24	19
alert[0x1d]	2963	1			T21	7		T56	10		T24	13
alert[0x1e]	8678	1			T3	1		T9	1		T23	35
alert[0x1f]	2879	1			T8	1		T15	1		T9	1
alert[0x20]	5910	1			T56	139		T24	32		T35	2317
alert[0x21]	13108	1			T68	12		T24	123		T188	1
alert[0x22]	2934	1			T192	1		T23	271		T54	4
alert[0x23]	4313	1			T56	9		T191	64		T24	9
alert[0x24]	6008	1			T3	1		T15	3		T68	37
alert[0x25]	8296	1			T3	1		T56	334		T26	113
alert[0x26]	3874	1			T56	29		T26	40		T35	27
alert[0x27]	3540	1			T16	55		T56	409		T24	51
alert[0x28]	4639	1			T10	1		T68	2		T23	87
alert[0x29]	8189	1			T68	2		T23	77		T21	300
alert[0x2a]	6080	1			T7	1		T10	1		T68	3
alert[0x2b]	6513	1			T56	67		T191	170		T24	88
alert[0x2c]	7618	1			T68	2		T23	100		T21	60
alert[0x2d]	3427	1			T15	3		T9	1		T16	1
alert[0x2e]	2944	1			T3	1		T10	1		T56	50
alert[0x2f]	8832	1			T191	26		T24	44		T26	390
alert[0x30]	3878	1			T56	15		T191	269		T35	40
alert[0x31]	7052	1			T23	21		T56	127		T24	66
alert[0x32]	2974	1			T9	1		T23	44		T191	184
alert[0x33]	2918	1			T17	7		T23	37		T56	344
alert[0x34]	7891	1			T3	1		T56	55		T24	3
alert[0x35]	12417	1			T15	2		T16	50		T68	1
alert[0x36]	8148	1			T21	80		T191	8		T35	196
alert[0x37]	9495	1			T21	25		T56	26		T191	82
alert[0x38]	6115	1			T16	139		T21	19		T191	865
alert[0x39]	8440	1			T21	379		T191	99		T35	452
alert[0x3a]	8134	1			T7	3		T21	275		T191	775
alert[0x3b]	10635	1			T56	164		T69	22		T190	3
alert[0x3c]	7238	1			T7	1		T56	225		T26	12
alert[0x3d]	1656	1			T7	2		T23	7		T191	61
alert[0x3e]	7824	1			T3	1		T56	30		T191	85
alert[0x3f]	9281	1			T3	1		T23	44		T21	28
alert[0x40]	4649	1			T10	1		T68	1		T21	30

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	114739	1			T16	787		T10	9		T21	164
class_i[0x1]	73500	1			T7	6		T15	4		T9	2
class_i[0x2]	84000	1			T8	2		T9	10		T10	1
class_i[0x3]	129734	1			T3	17		T17	35		T7	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

401338

1

T17

35

T7

7

T15

9

alert_ping_fail

635

1

T3

17

T8

2

T9

12

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4637	1			T56	21		T39	5		T109	12
alert_integrity_fail	alert[0x1]	11267	1			T26	230		T69	201		T37	1
alert_integrity_fail	alert[0x2]	11168	1			T21	2		T191	120		T24	140
alert_integrity_fail	alert[0x3]	2333	1			T56	37		T26	200		T37	29
alert_integrity_fail	alert[0x4]	5676	1			T23	254		T21	300		T26	110
alert_integrity_fail	alert[0x5]	5960	1			T23	1615		T21	2		T56	8
alert_integrity_fail	alert[0x6]	2899	1			T17	18		T23	17		T21	54
alert_integrity_fail	alert[0x7]	7241	1			T191	18		T69	8		T193	108
alert_integrity_fail	alert[0x8]	8407	1			T68	5		T23	828		T56	183
alert_integrity_fail	alert[0x9]	12600	1			T16	10		T21	26		T191	29
alert_integrity_fail	alert[0xa]	4935	1			T56	1742		T190	321		T74	2
alert_integrity_fail	alert[0xb]	4468	1			T17	3		T16	11		T26	1262
alert_integrity_fail	alert[0xc]	1487	1			T16	5		T68	65		T23	22
alert_integrity_fail	alert[0xd]	9362	1			T21	75		T191	395		T24	6
alert_integrity_fail	alert[0xe]	8574	1			T35	299		T69	305		T37	39
alert_integrity_fail	alert[0xf]	2945	1			T17	1		T21	175		T191	37
alert_integrity_fail	alert[0x10]	1506	1			T16	73		T21	8		T24	16
alert_integrity_fail	alert[0x11]	5358	1			T21	43		T56	32		T24	4
alert_integrity_fail	alert[0x12]	5380	1			T21	356		T24	4		T26	9
alert_integrity_fail	alert[0x13]	4198	1			T24	104		T26	37		T193	88
alert_integrity_fail	alert[0x14]	10077	1			T21	241		T191	8		T24	52
alert_integrity_fail	alert[0x15]	1865	1			T56	10		T191	56		T26	15
alert_integrity_fail	alert[0x16]	6313	1			T56	98		T191	157		T35	307
alert_integrity_fail	alert[0x17]	3640	1			T16	11		T68	1		T23	33
alert_integrity_fail	alert[0x18]	9340	1			T17	6		T16	425		T56	112
alert_integrity_fail	alert[0x19]	3273	1			T23	394		T191	175		T35	18
alert_integrity_fail	alert[0x1a]	4685	1			T56	8		T191	17		T35	124
alert_integrity_fail	alert[0x1b]	7163	1			T16	7		T23	11		T21	1
alert_integrity_fail	alert[0x1c]	5441	1			T56	4		T191	34		T24	19
alert_integrity_fail	alert[0x1d]	2953	1			T21	7		T56	10		T24	13
alert_integrity_fail	alert[0x1e]	8670	1			T23	35		T21	45		T56	15
alert_integrity_fail	alert[0x1f]	2865	1			T15	1		T69	10		T37	224
alert_integrity_fail	alert[0x20]	5897	1			T56	139		T24	32		T35	2317
alert_integrity_fail	alert[0x21]	13099	1			T68	12		T24	123		T69	4000
alert_integrity_fail	alert[0x22]	2921	1			T23	271		T54	4		T21	409
alert_integrity_fail	alert[0x23]	4305	1			T56	9		T191	64		T24	9
alert_integrity_fail	alert[0x24]	6000	1			T15	3		T68	37		T23	72
alert_integrity_fail	alert[0x25]	8284	1			T56	334		T26	113		T35	93
alert_integrity_fail	alert[0x26]	3865	1			T56	29		T26	40		T35	27
alert_integrity_fail	alert[0x27]	3533	1			T16	55		T56	409		T24	51
alert_integrity_fail	alert[0x28]	4624	1			T68	2		T23	87		T21	135
alert_integrity_fail	alert[0x29]	8177	1			T68	2		T23	77		T21	300
alert_integrity_fail	alert[0x2a]	6064	1			T7	1		T68	3		T26	15
alert_integrity_fail	alert[0x2b]	6506	1			T56	67		T191	170		T24	88
alert_integrity_fail	alert[0x2c]	7606	1			T68	2		T23	100		T21	60
alert_integrity_fail	alert[0x2d]	3412	1			T15	3		T16	1		T21	4
alert_integrity_fail	alert[0x2e]	2935	1			T56	50		T191	16		T26	52
alert_integrity_fail	alert[0x2f]	8823	1			T191	26		T24	44		T26	390
alert_integrity_fail	alert[0x30]	3868	1			T56	15		T191	269		T35	40
alert_integrity_fail	alert[0x31]	7044	1			T23	21		T56	127		T24	66
alert_integrity_fail	alert[0x32]	2968	1			T23	44		T191	184		T24	806
alert_integrity_fail	alert[0x33]	2910	1			T17	7		T23	37		T56	344
alert_integrity_fail	alert[0x34]	7882	1			T56	55		T24	3		T69	2
alert_integrity_fail	alert[0x35]	12406	1			T15	2		T16	50		T68	1
alert_integrity_fail	alert[0x36]	8138	1			T21	80		T191	8		T35	196
alert_integrity_fail	alert[0x37]	9486	1			T21	25		T56	26		T191	82
alert_integrity_fail	alert[0x38]	6106	1			T16	139		T21	19		T191	865
alert_integrity_fail	alert[0x39]	8431	1			T21	379		T191	99		T35	452
alert_integrity_fail	alert[0x3a]	8121	1			T7	3		T21	275		T191	775
alert_integrity_fail	alert[0x3b]	10628	1			T56	164		T69	22		T190	3
alert_integrity_fail	alert[0x3c]	7233	1			T7	1		T56	225		T26	12
alert_integrity_fail	alert[0x3d]	1647	1			T7	2		T23	7		T191	61
alert_integrity_fail	alert[0x3e]	7815	1			T56	30		T191	85		T37	1
alert_integrity_fail	alert[0x3f]	9275	1			T23	44		T21	28		T56	14
alert_integrity_fail	alert[0x40]	4643	1			T68	1		T21	30		T35	278
alert_ping_fail	alert[0x0]	6	1			T10	1		T286	1		T219	1
alert_ping_fail	alert[0x1]	11	1			T9	1		T287	1		T288	1
alert_ping_fail	alert[0x2]	9	1			T9	1		T289	1		T290	1
alert_ping_fail	alert[0x3]	13	1			T261	1		T287	1		T291	1
alert_ping_fail	alert[0x4]	6	1			T292	1		T293	1		T294	1
alert_ping_fail	alert[0x5]	11	1			T57	1		T287	1		T292	1
alert_ping_fail	alert[0x6]	12	1			T9	1		T261	1		T295	1
alert_ping_fail	alert[0x7]	12	1			T188	2		T296	1		T297	1
alert_ping_fail	alert[0x8]	17	1			T10	1		T188	2		T287	2
alert_ping_fail	alert[0x9]	8	1			T10	1		T289	1		T261	1
alert_ping_fail	alert[0xa]	5	1			T298	1		T291	1		T299	1
alert_ping_fail	alert[0xb]	11	1			T295	1		T296	1		T293	1
alert_ping_fail	alert[0xc]	9	1			T9	1		T286	1		T219	1
alert_ping_fail	alert[0xd]	9	1			T10	1		T289	1		T296	1
alert_ping_fail	alert[0xe]	8	1			T3	1		T219	1		T291	1
alert_ping_fail	alert[0xf]	7	1			T3	1		T9	1		T292	1
alert_ping_fail	alert[0x10]	10	1			T9	1		T289	1		T261	2
alert_ping_fail	alert[0x11]	9	1			T3	2		T10	1		T297	1
alert_ping_fail	alert[0x12]	8	1			T3	1		T296	1		T297	1
alert_ping_fail	alert[0x13]	16	1			T3	1		T57	1		T188	1
alert_ping_fail	alert[0x14]	12	1			T3	1		T8	1		T188	1
alert_ping_fail	alert[0x15]	5	1			T9	2		T300	1		T301	1
alert_ping_fail	alert[0x16]	13	1			T3	2		T284	1		T283	1
alert_ping_fail	alert[0x17]	12	1			T10	1		T188	1		T296	2
alert_ping_fail	alert[0x18]	14	1			T188	1		T292	2		T290	2
alert_ping_fail	alert[0x19]	4	1			T288	1		T302	1		T300	1
alert_ping_fail	alert[0x1a]	11	1			T3	1		T286	1		T295	1
alert_ping_fail	alert[0x1b]	7	1			T188	1		T261	1		T295	1
alert_ping_fail	alert[0x1c]	10	1			T303	1		T292	1		T304	1
alert_ping_fail	alert[0x1d]	10	1			T286	1		T289	1		T219	1
alert_ping_fail	alert[0x1e]	8	1			T3	1		T9	1		T295	1
alert_ping_fail	alert[0x1f]	14	1			T8	1		T9	1		T188	1
alert_ping_fail	alert[0x20]	13	1			T289	1		T261	1		T305	1
alert_ping_fail	alert[0x21]	9	1			T188	1		T287	2		T291	1
alert_ping_fail	alert[0x22]	13	1			T192	1		T284	1		T306	1
alert_ping_fail	alert[0x23]	8	1			T287	1		T297	1		T304	1
alert_ping_fail	alert[0x24]	8	1			T3	1		T188	1		T286	1
alert_ping_fail	alert[0x25]	12	1			T3	1		T261	1		T287	1
alert_ping_fail	alert[0x26]	9	1			T289	1		T295	1		T288	1
alert_ping_fail	alert[0x27]	7	1			T296	1		T219	2		T307	1
alert_ping_fail	alert[0x28]	15	1			T10	1		T286	1		T308	2
alert_ping_fail	alert[0x29]	12	1			T286	2		T296	2		T292	3
alert_ping_fail	alert[0x2a]	16	1			T10	1		T289	1		T261	1
alert_ping_fail	alert[0x2b]	7	1			T188	2		T305	1		T309	1
alert_ping_fail	alert[0x2c]	12	1			T291	1		T288	1		T302	1
alert_ping_fail	alert[0x2d]	15	1			T9	1		T286	1		T282	2
alert_ping_fail	alert[0x2e]	9	1			T3	1		T10	1		T289	1
alert_ping_fail	alert[0x2f]	9	1			T261	1		T288	1		T310	1
alert_ping_fail	alert[0x30]	10	1			T261	1		T219	1		T293	1
alert_ping_fail	alert[0x31]	8	1			T219	1		T304	1		T294	1
alert_ping_fail	alert[0x32]	6	1			T9	1		T286	1		T289	2
alert_ping_fail	alert[0x33]	8	1			T261	1		T296	1		T305	1
alert_ping_fail	alert[0x34]	9	1			T3	1		T296	1		T311	1
alert_ping_fail	alert[0x35]	11	1			T188	1		T295	2		T291	1
alert_ping_fail	alert[0x36]	10	1			T261	1		T287	1		T293	1
alert_ping_fail	alert[0x37]	9	1			T289	1		T297	1		T292	1
alert_ping_fail	alert[0x38]	9	1			T188	1		T286	1		T291	1
alert_ping_fail	alert[0x39]	9	1			T293	1		T305	1		T299	1
alert_ping_fail	alert[0x3a]	13	1			T296	1		T304	1		T312	1
alert_ping_fail	alert[0x3b]	7	1			T261	1		T287	1		T219	2
alert_ping_fail	alert[0x3c]	5	1			T287	1		T295	1		T219	1
alert_ping_fail	alert[0x3d]	9	1			T289	1		T291	1		T305	1
alert_ping_fail	alert[0x3e]	9	1			T3	1		T219	1		T305	2
alert_ping_fail	alert[0x3f]	6	1			T3	1		T296	1		T297	1
alert_ping_fail	alert[0x40]	6	1			T10	1		T296	1		T293	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	114607	1			T16	787		T21	164		T56	53
alert_integrity_fail	class_i[0x1]	73383	1			T7	6		T15	4		T68	126
alert_integrity_fail	class_i[0x2]	83849	1			T68	5		T23	3965		T54	4
alert_integrity_fail	class_i[0x3]	129499	1			T17	35		T7	1		T15	5
alert_ping_fail	class_i[0x0]	132	1			T10	9		T188	2		T289	14
alert_ping_fail	class_i[0x1]	117	1			T9	2		T188	1		T286	11
alert_ping_fail	class_i[0x2]	151	1			T8	2		T9	10		T10	1
alert_ping_fail	class_i[0x3]	235	1			T3	17		T192	1		T188	12