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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.74 99.97 100.00 100.00 99.38 99.40


Total test records in report: 830
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T773 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3429545120 Jul 14 05:59:47 PM PDT 24 Jul 14 05:59:50 PM PDT 24 8540261 ps
T774 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.205399682 Jul 14 05:59:56 PM PDT 24 Jul 14 05:59:57 PM PDT 24 22067462 ps
T775 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1484353390 Jul 14 05:59:37 PM PDT 24 Jul 14 06:00:01 PM PDT 24 735743485 ps
T776 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3243353661 Jul 14 05:59:24 PM PDT 24 Jul 14 06:00:06 PM PDT 24 2060680755 ps
T136 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2869205965 Jul 14 05:59:18 PM PDT 24 Jul 14 06:03:10 PM PDT 24 1657271042 ps
T777 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2637017752 Jul 14 05:59:11 PM PDT 24 Jul 14 05:59:13 PM PDT 24 10556595 ps
T778 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2178037385 Jul 14 05:59:39 PM PDT 24 Jul 14 05:59:51 PM PDT 24 111564981 ps
T168 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1286088986 Jul 14 05:59:32 PM PDT 24 Jul 14 06:00:07 PM PDT 24 1041818296 ps
T779 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.962811462 Jul 14 05:59:26 PM PDT 24 Jul 14 05:59:28 PM PDT 24 10259105 ps
T780 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.158675965 Jul 14 05:59:46 PM PDT 24 Jul 14 05:59:49 PM PDT 24 8589758 ps
T781 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1580971284 Jul 14 05:59:13 PM PDT 24 Jul 14 05:59:19 PM PDT 24 33271817 ps
T782 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3163947072 Jul 14 05:59:32 PM PDT 24 Jul 14 05:59:57 PM PDT 24 1304426044 ps
T783 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2865636364 Jul 14 05:59:47 PM PDT 24 Jul 14 05:59:50 PM PDT 24 12436877 ps
T143 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.936213888 Jul 14 05:59:26 PM PDT 24 Jul 14 06:07:26 PM PDT 24 25814789111 ps
T784 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1897599625 Jul 14 05:59:46 PM PDT 24 Jul 14 05:59:48 PM PDT 24 35483736 ps
T785 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2381386884 Jul 14 05:59:35 PM PDT 24 Jul 14 05:59:47 PM PDT 24 255815879 ps
T155 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1282942391 Jul 14 05:59:13 PM PDT 24 Jul 14 06:00:21 PM PDT 24 905930084 ps
T786 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1334504387 Jul 14 05:59:44 PM PDT 24 Jul 14 05:59:45 PM PDT 24 11435208 ps
T160 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3623733150 Jul 14 05:59:21 PM PDT 24 Jul 14 05:59:24 PM PDT 24 48487839 ps
T787 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1897276802 Jul 14 05:59:36 PM PDT 24 Jul 14 05:59:46 PM PDT 24 498800771 ps
T788 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2078579117 Jul 14 05:59:40 PM PDT 24 Jul 14 06:00:07 PM PDT 24 334270620 ps
T789 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.413509541 Jul 14 05:59:30 PM PDT 24 Jul 14 06:00:18 PM PDT 24 2159056057 ps
T790 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3445112142 Jul 14 05:59:31 PM PDT 24 Jul 14 05:59:33 PM PDT 24 7591881 ps
T791 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.18864367 Jul 14 05:59:33 PM PDT 24 Jul 14 05:59:38 PM PDT 24 51866496 ps
T138 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2803296420 Jul 14 05:59:37 PM PDT 24 Jul 14 06:10:58 PM PDT 24 5706441330 ps
T792 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1033353197 Jul 14 05:59:11 PM PDT 24 Jul 14 06:00:47 PM PDT 24 3408076070 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.474697109 Jul 14 05:59:16 PM PDT 24 Jul 14 05:59:41 PM PDT 24 186229486 ps
T794 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1663718578 Jul 14 05:59:43 PM PDT 24 Jul 14 05:59:45 PM PDT 24 10508446 ps
T156 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3772878710 Jul 14 05:59:30 PM PDT 24 Jul 14 06:00:43 PM PDT 24 1815304994 ps
T795 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.488115004 Jul 14 05:59:15 PM PDT 24 Jul 14 05:59:24 PM PDT 24 118016990 ps
T139 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2408201973 Jul 14 05:59:18 PM PDT 24 Jul 14 06:04:44 PM PDT 24 67409897659 ps
T796 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2309637475 Jul 14 05:59:43 PM PDT 24 Jul 14 05:59:46 PM PDT 24 10432954 ps
T797 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.245358624 Jul 14 05:59:40 PM PDT 24 Jul 14 05:59:54 PM PDT 24 610413265 ps
T798 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1522964033 Jul 14 05:59:20 PM PDT 24 Jul 14 05:59:33 PM PDT 24 94169406 ps
T799 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3640511912 Jul 14 05:59:48 PM PDT 24 Jul 14 05:59:50 PM PDT 24 13508783 ps
T142 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1041987563 Jul 14 05:59:33 PM PDT 24 Jul 14 06:16:41 PM PDT 24 75104108241 ps
T800 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3027728222 Jul 14 05:59:25 PM PDT 24 Jul 14 05:59:42 PM PDT 24 259428304 ps
T801 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3646090602 Jul 14 05:59:35 PM PDT 24 Jul 14 05:59:59 PM PDT 24 298585946 ps
T165 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3894609577 Jul 14 05:59:32 PM PDT 24 Jul 14 05:59:36 PM PDT 24 165063602 ps
T162 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2994991359 Jul 14 05:59:46 PM PDT 24 Jul 14 06:00:34 PM PDT 24 360996797 ps
T341 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2542900400 Jul 14 05:59:39 PM PDT 24 Jul 14 06:11:16 PM PDT 24 4428757493 ps
T145 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1951912435 Jul 14 05:59:28 PM PDT 24 Jul 14 06:05:58 PM PDT 24 24122131398 ps
T802 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.4104274965 Jul 14 05:59:56 PM PDT 24 Jul 14 05:59:58 PM PDT 24 18744376 ps
T803 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2353120815 Jul 14 05:59:47 PM PDT 24 Jul 14 05:59:49 PM PDT 24 14541841 ps
T804 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3818805049 Jul 14 05:59:55 PM PDT 24 Jul 14 05:59:56 PM PDT 24 13176601 ps
T135 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1814317191 Jul 14 05:59:13 PM PDT 24 Jul 14 06:01:36 PM PDT 24 8027546432 ps
T805 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.4204080451 Jul 14 05:59:34 PM PDT 24 Jul 14 05:59:42 PM PDT 24 62747282 ps
T806 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1050452436 Jul 14 05:59:40 PM PDT 24 Jul 14 05:59:44 PM PDT 24 15602657 ps
T169 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1713115052 Jul 14 05:59:24 PM PDT 24 Jul 14 05:59:27 PM PDT 24 93745032 ps
T807 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4182451724 Jul 14 05:59:12 PM PDT 24 Jul 14 05:59:18 PM PDT 24 194257038 ps
T808 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.537557848 Jul 14 05:59:45 PM PDT 24 Jul 14 05:59:51 PM PDT 24 102090555 ps
T809 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2372284994 Jul 14 05:59:22 PM PDT 24 Jul 14 05:59:33 PM PDT 24 489475943 ps
T810 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3253922736 Jul 14 05:59:15 PM PDT 24 Jul 14 05:59:38 PM PDT 24 650757033 ps
T146 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2715975150 Jul 14 05:59:37 PM PDT 24 Jul 14 06:05:34 PM PDT 24 17738852534 ps
T811 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3443517982 Jul 14 05:59:27 PM PDT 24 Jul 14 05:59:32 PM PDT 24 22921073 ps
T812 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1461821844 Jul 14 05:59:18 PM PDT 24 Jul 14 05:59:24 PM PDT 24 225641588 ps
T813 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.258605265 Jul 14 05:59:35 PM PDT 24 Jul 14 05:59:45 PM PDT 24 117037309 ps
T814 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2095040376 Jul 14 05:59:38 PM PDT 24 Jul 14 05:59:44 PM PDT 24 34215192 ps
T161 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3563987400 Jul 14 05:59:42 PM PDT 24 Jul 14 05:59:47 PM PDT 24 126850849 ps
T815 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3891483906 Jul 14 05:59:42 PM PDT 24 Jul 14 06:00:24 PM PDT 24 602473682 ps
T816 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2214910271 Jul 14 05:59:32 PM PDT 24 Jul 14 05:59:36 PM PDT 24 40181700 ps
T817 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2186558486 Jul 14 05:59:20 PM PDT 24 Jul 14 06:06:27 PM PDT 24 11877225051 ps
T818 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3954576376 Jul 14 05:59:35 PM PDT 24 Jul 14 05:59:48 PM PDT 24 997079112 ps
T819 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3522862304 Jul 14 05:59:27 PM PDT 24 Jul 14 05:59:34 PM PDT 24 600550908 ps
T820 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.339286885 Jul 14 05:59:24 PM PDT 24 Jul 14 05:59:31 PM PDT 24 141066127 ps
T147 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2914024726 Jul 14 05:59:09 PM PDT 24 Jul 14 06:01:45 PM PDT 24 7798985001 ps
T821 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3232898061 Jul 14 05:59:37 PM PDT 24 Jul 14 05:59:51 PM PDT 24 310480808 ps
T340 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1263775861 Jul 14 05:59:18 PM PDT 24 Jul 14 06:05:23 PM PDT 24 2293238771 ps
T822 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3128521247 Jul 14 05:59:38 PM PDT 24 Jul 14 06:00:03 PM PDT 24 292500503 ps
T823 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.734189006 Jul 14 05:59:15 PM PDT 24 Jul 14 06:04:10 PM PDT 24 8542800548 ps
T824 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1541450393 Jul 14 05:59:40 PM PDT 24 Jul 14 05:59:42 PM PDT 24 20613335 ps
T825 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.591282621 Jul 14 05:59:13 PM PDT 24 Jul 14 05:59:16 PM PDT 24 13173243 ps
T826 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2123571552 Jul 14 05:59:47 PM PDT 24 Jul 14 05:59:49 PM PDT 24 7847171 ps
T339 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1722018062 Jul 14 05:59:42 PM PDT 24 Jul 14 06:09:42 PM PDT 24 5023065941 ps
T164 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1865975199 Jul 14 05:59:42 PM PDT 24 Jul 14 06:00:03 PM PDT 24 154096704 ps
T827 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2119188119 Jul 14 05:59:38 PM PDT 24 Jul 14 05:59:51 PM PDT 24 715384283 ps
T828 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3626772041 Jul 14 05:59:32 PM PDT 24 Jul 14 05:59:38 PM PDT 24 55746976 ps
T829 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3125088676 Jul 14 05:59:47 PM PDT 24 Jul 14 05:59:50 PM PDT 24 10669688 ps
T830 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3532760299 Jul 14 05:59:07 PM PDT 24 Jul 14 05:59:16 PM PDT 24 369710918 ps
T144 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1536061637 Jul 14 05:59:11 PM PDT 24 Jul 14 06:11:06 PM PDT 24 17550492129 ps

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2169182264
Short name T17
Test name
Test status
Simulation time 154135658074 ps
CPU time 2819.77 seconds
Started Jul 14 05:12:14 PM PDT 24
Finished Jul 14 05:59:15 PM PDT 24
Peak memory 290452 kb
Host smart-20b087c9-dbf0-4c79-88db-38bd07ac6585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169182264 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2169182264
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3642810506
Short name T16
Test name
Test status
Simulation time 66880463315 ps
CPU time 6101.06 seconds
Started Jul 14 05:08:51 PM PDT 24
Finished Jul 14 06:50:33 PM PDT 24
Peak memory 364080 kb
Host smart-1e5f8ac0-00f1-4d8d-bd3c-d8dcedfea54a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642810506 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3642810506
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2243838042
Short name T4
Test name
Test status
Simulation time 426141958 ps
CPU time 13.9 seconds
Started Jul 14 05:06:31 PM PDT 24
Finished Jul 14 05:06:45 PM PDT 24
Peak memory 279124 kb
Host smart-b79cbaf9-ed7d-4611-86a6-85fd9d82d301
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2243838042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2243838042
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1605699296
Short name T35
Test name
Test status
Simulation time 405233601167 ps
CPU time 10083.4 seconds
Started Jul 14 05:12:00 PM PDT 24
Finished Jul 14 08:00:05 PM PDT 24
Peak memory 387388 kb
Host smart-754cef19-992b-44b9-a047-25a6537d12ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605699296 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1605699296
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1232707199
Short name T118
Test name
Test status
Simulation time 53690451515 ps
CPU time 1027.38 seconds
Started Jul 14 05:59:33 PM PDT 24
Finished Jul 14 06:16:41 PM PDT 24
Peak memory 265280 kb
Host smart-88725fd5-ebef-4418-b1b8-266bdf42de27
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232707199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1232707199
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1119497822
Short name T23
Test name
Test status
Simulation time 178173285938 ps
CPU time 4573.79 seconds
Started Jul 14 05:06:31 PM PDT 24
Finished Jul 14 06:22:46 PM PDT 24
Peak memory 335416 kb
Host smart-3abff377-c28d-4652-829b-e8132f23ba62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119497822 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1119497822
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3766679529
Short name T704
Test name
Test status
Simulation time 16122572493 ps
CPU time 1962.65 seconds
Started Jul 14 05:12:40 PM PDT 24
Finished Jul 14 05:45:24 PM PDT 24
Peak memory 304360 kb
Host smart-6544c118-e14b-4a84-850e-56020625424c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766679529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3766679529
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3811480472
Short name T112
Test name
Test status
Simulation time 17773028308 ps
CPU time 573.07 seconds
Started Jul 14 05:59:35 PM PDT 24
Finished Jul 14 06:09:09 PM PDT 24
Peak memory 272832 kb
Host smart-b1b731ef-cf26-45be-8396-329ef2303e55
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811480472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3811480472
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1459615410
Short name T55
Test name
Test status
Simulation time 667552618 ps
CPU time 12.09 seconds
Started Jul 14 05:08:10 PM PDT 24
Finished Jul 14 05:08:22 PM PDT 24
Peak memory 249212 kb
Host smart-1b0b1189-3d02-48ba-b3b6-c1bd3b0de137
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1459615410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1459615410
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.4262829799
Short name T13
Test name
Test status
Simulation time 84625030789 ps
CPU time 2737.81 seconds
Started Jul 14 05:07:41 PM PDT 24
Finished Jul 14 05:53:19 PM PDT 24
Peak memory 289560 kb
Host smart-5a06ed46-a9ca-4c7b-b594-f27343f11eb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262829799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.4262829799
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2715957672
Short name T24
Test name
Test status
Simulation time 55926065309 ps
CPU time 6067.39 seconds
Started Jul 14 05:16:22 PM PDT 24
Finished Jul 14 06:57:31 PM PDT 24
Peak memory 365152 kb
Host smart-d89cd093-5587-462e-8437-4a91b3ac170b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715957672 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2715957672
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.864944417
Short name T183
Test name
Test status
Simulation time 23311267908 ps
CPU time 225.97 seconds
Started Jul 14 05:59:11 PM PDT 24
Finished Jul 14 06:02:57 PM PDT 24
Peak memory 237468 kb
Host smart-1e22078a-d3a7-44da-b6e0-c330a1527c30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=864944417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.864944417
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.93121092
Short name T116
Test name
Test status
Simulation time 4975488682 ps
CPU time 340.43 seconds
Started Jul 14 05:59:41 PM PDT 24
Finished Jul 14 06:05:22 PM PDT 24
Peak memory 265372 kb
Host smart-be3aef42-0f3e-4a95-b3f7-79f8d63231b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=93121092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_error
s.93121092
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.4128208478
Short name T26
Test name
Test status
Simulation time 11777062596 ps
CPU time 1224.47 seconds
Started Jul 14 05:07:25 PM PDT 24
Finished Jul 14 05:27:50 PM PDT 24
Peak memory 283800 kb
Host smart-6c7fb5d0-b47a-487c-9013-19b24ab27c41
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128208478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.4128208478
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3049179859
Short name T43
Test name
Test status
Simulation time 52932753779 ps
CPU time 1862.05 seconds
Started Jul 14 05:16:08 PM PDT 24
Finished Jul 14 05:47:11 PM PDT 24
Peak memory 286140 kb
Host smart-6009d9d0-7ff1-4576-92b2-9efbdbfded06
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049179859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3049179859
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2869205965
Short name T136
Test name
Test status
Simulation time 1657271042 ps
CPU time 231.31 seconds
Started Jul 14 05:59:18 PM PDT 24
Finished Jul 14 06:03:10 PM PDT 24
Peak memory 265384 kb
Host smart-5afc376c-035d-4a5b-8c59-8651a18facc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2869205965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2869205965
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.617390639
Short name T3
Test name
Test status
Simulation time 49661469792 ps
CPU time 493.73 seconds
Started Jul 14 05:14:04 PM PDT 24
Finished Jul 14 05:22:18 PM PDT 24
Peak memory 256564 kb
Host smart-13dec687-dc7d-4c26-ac86-96e2045df492
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617390639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.617390639
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2692145762
Short name T285
Test name
Test status
Simulation time 153835467067 ps
CPU time 2281.22 seconds
Started Jul 14 05:06:30 PM PDT 24
Finished Jul 14 05:44:32 PM PDT 24
Peak memory 273768 kb
Host smart-8251b6d2-e29e-4bf2-82ee-2fb763185d5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692145762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2692145762
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3323624159
Short name T128
Test name
Test status
Simulation time 16309664120 ps
CPU time 1114.14 seconds
Started Jul 14 05:59:19 PM PDT 24
Finished Jul 14 06:17:54 PM PDT 24
Peak memory 264344 kb
Host smart-cbb9e731-3bd5-4284-b830-ca1ade85ef85
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323624159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3323624159
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3233598007
Short name T151
Test name
Test status
Simulation time 8199539 ps
CPU time 1.39 seconds
Started Jul 14 05:59:46 PM PDT 24
Finished Jul 14 05:59:48 PM PDT 24
Peak memory 236584 kb
Host smart-67dd3761-cdad-4732-bab3-8f950dd81a75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3233598007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3233598007
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3740561495
Short name T119
Test name
Test status
Simulation time 5111127831 ps
CPU time 724.45 seconds
Started Jul 14 05:59:23 PM PDT 24
Finished Jul 14 06:11:28 PM PDT 24
Peak memory 273260 kb
Host smart-d2f855e8-1e38-4c85-bc73-3dc7391a7f40
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740561495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3740561495
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3185297977
Short name T261
Test name
Test status
Simulation time 19088722493 ps
CPU time 429.25 seconds
Started Jul 14 05:08:10 PM PDT 24
Finished Jul 14 05:15:20 PM PDT 24
Peak memory 249288 kb
Host smart-9472be4c-2dc8-4a2d-b4eb-18143b06e0e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185297977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3185297977
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.4248167432
Short name T282
Test name
Test status
Simulation time 123705404805 ps
CPU time 2327.03 seconds
Started Jul 14 05:11:19 PM PDT 24
Finished Jul 14 05:50:06 PM PDT 24
Peak memory 282008 kb
Host smart-d171852a-901e-41f3-91c8-faf58fdce835
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248167432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.4248167432
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2715975150
Short name T146
Test name
Test status
Simulation time 17738852534 ps
CPU time 356.17 seconds
Started Jul 14 05:59:37 PM PDT 24
Finished Jul 14 06:05:34 PM PDT 24
Peak memory 265488 kb
Host smart-e26ace10-857e-4da3-bf05-9a715b840244
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2715975150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2715975150
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3446937858
Short name T50
Test name
Test status
Simulation time 119450895672 ps
CPU time 9955.05 seconds
Started Jul 14 05:15:48 PM PDT 24
Finished Jul 14 08:01:44 PM PDT 24
Peak memory 404612 kb
Host smart-cba11583-e126-4a34-b417-cc2d7ff55e3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446937858 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3446937858
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.4246973896
Short name T190
Test name
Test status
Simulation time 17944358307 ps
CPU time 1434.98 seconds
Started Jul 14 05:14:03 PM PDT 24
Finished Jul 14 05:37:59 PM PDT 24
Peak memory 273680 kb
Host smart-bd55d989-19ea-4810-81df-6f75b2d59aa8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246973896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4246973896
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2937612563
Short name T308
Test name
Test status
Simulation time 194000104425 ps
CPU time 2937.5 seconds
Started Jul 14 05:06:35 PM PDT 24
Finished Jul 14 05:55:34 PM PDT 24
Peak memory 284984 kb
Host smart-9f1fff77-a10d-4f6d-a175-eb9ffad63ad0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937612563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2937612563
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.943592228
Short name T296
Test name
Test status
Simulation time 11686653394 ps
CPU time 452.76 seconds
Started Jul 14 05:16:07 PM PDT 24
Finished Jul 14 05:23:40 PM PDT 24
Peak memory 249068 kb
Host smart-67bd28ba-9bcc-43c3-b640-3ff8078ef608
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943592228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.943592228
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3820595316
Short name T117
Test name
Test status
Simulation time 4101647702 ps
CPU time 262.62 seconds
Started Jul 14 05:59:39 PM PDT 24
Finished Jul 14 06:04:02 PM PDT 24
Peak memory 271636 kb
Host smart-579c9907-5690-42fc-b00b-19f8163d35b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3820595316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3820595316
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.313232970
Short name T150
Test name
Test status
Simulation time 117928976 ps
CPU time 3.38 seconds
Started Jul 14 05:59:19 PM PDT 24
Finished Jul 14 05:59:23 PM PDT 24
Peak memory 237900 kb
Host smart-ced0daac-0500-453d-a9b8-b7a1c3f1c24a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=313232970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.313232970
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.904988107
Short name T568
Test name
Test status
Simulation time 17658587687 ps
CPU time 741.74 seconds
Started Jul 14 05:10:30 PM PDT 24
Finished Jul 14 05:22:52 PM PDT 24
Peak memory 249348 kb
Host smart-d5641e38-e19d-4cae-912a-082f43b23e1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904988107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.904988107
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.4008640088
Short name T21
Test name
Test status
Simulation time 56008028599 ps
CPU time 5134.48 seconds
Started Jul 14 05:14:51 PM PDT 24
Finished Jul 14 06:40:26 PM PDT 24
Peak memory 330908 kb
Host smart-b55cb401-de5b-4b5b-9688-88782ae98a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008640088 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.4008640088
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1522635879
Short name T114
Test name
Test status
Simulation time 7981280712 ps
CPU time 205.2 seconds
Started Jul 14 05:59:38 PM PDT 24
Finished Jul 14 06:03:05 PM PDT 24
Peak memory 265364 kb
Host smart-b5da3ad4-e0b0-4b10-ad33-a5c09d29ab56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1522635879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1522635879
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2050115716
Short name T239
Test name
Test status
Simulation time 26496508 ps
CPU time 1.51 seconds
Started Jul 14 05:59:50 PM PDT 24
Finished Jul 14 05:59:52 PM PDT 24
Peak memory 237548 kb
Host smart-734448c1-b0e5-46e9-99ca-478c0eb5592d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2050115716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2050115716
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1773536907
Short name T264
Test name
Test status
Simulation time 13555096300 ps
CPU time 1167.87 seconds
Started Jul 14 05:08:39 PM PDT 24
Finished Jul 14 05:28:08 PM PDT 24
Peak memory 273800 kb
Host smart-846747e7-f255-4b0f-9d7d-05918d74c72e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773536907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1773536907
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.693206166
Short name T647
Test name
Test status
Simulation time 36852957170 ps
CPU time 372.38 seconds
Started Jul 14 05:13:32 PM PDT 24
Finished Jul 14 05:19:45 PM PDT 24
Peak memory 249300 kb
Host smart-c654d0db-469b-4ffe-9407-216da144c5de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693206166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.693206166
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1682463796
Short name T286
Test name
Test status
Simulation time 125164404473 ps
CPU time 396.32 seconds
Started Jul 14 05:08:24 PM PDT 24
Finished Jul 14 05:15:01 PM PDT 24
Peak memory 249252 kb
Host smart-65cf8220-60a7-4cca-9db7-3d09c632c1e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682463796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1682463796
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3322940109
Short name T108
Test name
Test status
Simulation time 60199602210 ps
CPU time 5897.35 seconds
Started Jul 14 05:14:14 PM PDT 24
Finished Jul 14 06:52:32 PM PDT 24
Peak memory 347684 kb
Host smart-6517db7e-2eea-4793-82a6-c230c51474d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322940109 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3322940109
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.372005326
Short name T315
Test name
Test status
Simulation time 54272544656 ps
CPU time 3221.32 seconds
Started Jul 14 05:07:13 PM PDT 24
Finished Jul 14 06:00:55 PM PDT 24
Peak memory 290244 kb
Host smart-3bb5f68b-4c31-4b89-8c3c-0b7516d8c43b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372005326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.372005326
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2382403298
Short name T133
Test name
Test status
Simulation time 86166949288 ps
CPU time 1013.2 seconds
Started Jul 14 05:59:08 PM PDT 24
Finished Jul 14 06:16:02 PM PDT 24
Peak memory 265284 kb
Host smart-f7d3dd84-8db5-4870-82c3-a477f1ce3ed5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382403298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2382403298
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4063321727
Short name T40
Test name
Test status
Simulation time 19013502459 ps
CPU time 2163.4 seconds
Started Jul 14 05:15:52 PM PDT 24
Finished Jul 14 05:51:56 PM PDT 24
Peak memory 300392 kb
Host smart-2d2ed894-c3f4-492c-bccd-506380782cf2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063321727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4063321727
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1578645491
Short name T231
Test name
Test status
Simulation time 185841508 ps
CPU time 13.8 seconds
Started Jul 14 05:59:13 PM PDT 24
Finished Jul 14 05:59:27 PM PDT 24
Peak memory 248780 kb
Host smart-a2058141-ff45-428b-a039-c601c32c50c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578645491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1578645491
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1536061637
Short name T144
Test name
Test status
Simulation time 17550492129 ps
CPU time 714.23 seconds
Started Jul 14 05:59:11 PM PDT 24
Finished Jul 14 06:11:06 PM PDT 24
Peak memory 266304 kb
Host smart-69bde629-bc95-4560-be57-870b48500456
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536061637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1536061637
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3621746719
Short name T36
Test name
Test status
Simulation time 9376468712 ps
CPU time 53.96 seconds
Started Jul 14 05:09:56 PM PDT 24
Finished Jul 14 05:10:50 PM PDT 24
Peak memory 249268 kb
Host smart-e33d1091-17b7-4d5a-b268-94e40cf7a0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36217
46719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3621746719
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1111851641
Short name T640
Test name
Test status
Simulation time 36658194519 ps
CPU time 475.14 seconds
Started Jul 14 05:11:18 PM PDT 24
Finished Jul 14 05:19:14 PM PDT 24
Peak memory 249096 kb
Host smart-6251bea6-ece5-4402-8076-3450b090ecae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111851641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1111851641
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2742938006
Short name T251
Test name
Test status
Simulation time 32824591570 ps
CPU time 1572.32 seconds
Started Jul 14 05:12:35 PM PDT 24
Finished Jul 14 05:38:48 PM PDT 24
Peak memory 290080 kb
Host smart-e9dc3912-07ee-49e7-b645-4d5f0944b26a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742938006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2742938006
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1243525127
Short name T325
Test name
Test status
Simulation time 215667552506 ps
CPU time 2911.53 seconds
Started Jul 14 05:12:55 PM PDT 24
Finished Jul 14 06:01:27 PM PDT 24
Peak memory 290212 kb
Host smart-6db29edd-fd26-4b24-a1e3-a617de0ae3de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243525127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1243525127
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3381673501
Short name T94
Test name
Test status
Simulation time 94168816224 ps
CPU time 2140.21 seconds
Started Jul 14 05:14:00 PM PDT 24
Finished Jul 14 05:49:40 PM PDT 24
Peak memory 282188 kb
Host smart-e48c46a8-1c0e-4215-8662-e02ae53414ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381673501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3381673501
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1814317191
Short name T135
Test name
Test status
Simulation time 8027546432 ps
CPU time 142 seconds
Started Jul 14 05:59:13 PM PDT 24
Finished Jul 14 06:01:36 PM PDT 24
Peak memory 264624 kb
Host smart-56a7c51d-a908-4e05-9cb2-51b6fb5754c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1814317191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1814317191
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2803296420
Short name T138
Test name
Test status
Simulation time 5706441330 ps
CPU time 681.5 seconds
Started Jul 14 05:59:37 PM PDT 24
Finished Jul 14 06:10:58 PM PDT 24
Peak memory 265508 kb
Host smart-6fac6d9c-8529-491d-8a2b-216f4963b963
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803296420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2803296420
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1566118451
Short name T196
Test name
Test status
Simulation time 26082180 ps
CPU time 2.55 seconds
Started Jul 14 05:06:32 PM PDT 24
Finished Jul 14 05:06:35 PM PDT 24
Peak memory 249468 kb
Host smart-3be318c4-4b45-4d2b-9ffe-f13d90c296bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1566118451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1566118451
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2383161493
Short name T211
Test name
Test status
Simulation time 420488994 ps
CPU time 3.66 seconds
Started Jul 14 05:06:36 PM PDT 24
Finished Jul 14 05:06:40 PM PDT 24
Peak memory 249460 kb
Host smart-296b8658-c99b-47e9-9cb9-5001d867bffb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2383161493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2383161493
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.994985333
Short name T200
Test name
Test status
Simulation time 53763732 ps
CPU time 3.58 seconds
Started Jul 14 05:08:46 PM PDT 24
Finished Jul 14 05:08:50 PM PDT 24
Peak memory 249548 kb
Host smart-4a1b3fa9-2004-4a2f-b73b-13341ce9339c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=994985333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.994985333
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3731391585
Short name T209
Test name
Test status
Simulation time 16101885 ps
CPU time 2.82 seconds
Started Jul 14 05:08:51 PM PDT 24
Finished Jul 14 05:08:55 PM PDT 24
Peak memory 249492 kb
Host smart-67f4de24-ce78-4780-8b2d-20c9c95b339d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3731391585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3731391585
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3928379313
Short name T185
Test name
Test status
Simulation time 32207613479 ps
CPU time 2174.14 seconds
Started Jul 14 05:06:35 PM PDT 24
Finished Jul 14 05:42:50 PM PDT 24
Peak memory 289872 kb
Host smart-631b6657-ba2a-4f8c-b47e-decd7d2d541a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928379313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3928379313
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.886239145
Short name T229
Test name
Test status
Simulation time 96639728744 ps
CPU time 2935.24 seconds
Started Jul 14 05:08:31 PM PDT 24
Finished Jul 14 05:57:27 PM PDT 24
Peak memory 289724 kb
Host smart-18d20bce-34ec-4e41-b03b-64b76ee7df55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886239145 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.886239145
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2349439136
Short name T73
Test name
Test status
Simulation time 66295899364 ps
CPU time 2633.74 seconds
Started Jul 14 05:09:16 PM PDT 24
Finished Jul 14 05:53:11 PM PDT 24
Peak memory 290344 kb
Host smart-e6ed6d7e-72c5-42de-b3a9-d96c91382d84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349439136 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2349439136
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.951485464
Short name T254
Test name
Test status
Simulation time 1367562880 ps
CPU time 26.52 seconds
Started Jul 14 05:09:17 PM PDT 24
Finished Jul 14 05:09:44 PM PDT 24
Peak memory 255796 kb
Host smart-466c5072-75c5-4990-ac11-d0aef767ab7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95148
5464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.951485464
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1359647596
Short name T230
Test name
Test status
Simulation time 32233658492 ps
CPU time 2241.43 seconds
Started Jul 14 05:09:29 PM PDT 24
Finished Jul 14 05:46:51 PM PDT 24
Peak memory 289744 kb
Host smart-3852aafb-6d11-4a99-bf10-d906d91805f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359647596 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1359647596
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1692661333
Short name T74
Test name
Test status
Simulation time 260856059578 ps
CPU time 3693.76 seconds
Started Jul 14 05:10:17 PM PDT 24
Finished Jul 14 06:11:51 PM PDT 24
Peak memory 290200 kb
Host smart-0c1a8d9d-4973-4ca8-9c7a-f9e51cfbc591
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692661333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1692661333
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.178078944
Short name T86
Test name
Test status
Simulation time 46331308490 ps
CPU time 2688.57 seconds
Started Jul 14 05:10:27 PM PDT 24
Finished Jul 14 05:55:16 PM PDT 24
Peak memory 284348 kb
Host smart-2d481b87-9502-499c-a73e-93787e67bbec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178078944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.178078944
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3644809443
Short name T587
Test name
Test status
Simulation time 132979151567 ps
CPU time 1635.86 seconds
Started Jul 14 05:12:41 PM PDT 24
Finished Jul 14 05:39:58 PM PDT 24
Peak memory 273864 kb
Host smart-00984c5c-fca7-4f19-9e79-3fb8d9a7063e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644809443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3644809443
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2741692178
Short name T300
Test name
Test status
Simulation time 6173480032 ps
CPU time 273.47 seconds
Started Jul 14 05:12:48 PM PDT 24
Finished Jul 14 05:17:22 PM PDT 24
Peak memory 249272 kb
Host smart-26b82de9-e2ec-4504-a7a8-469e91b9aea1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741692178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2741692178
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4251765114
Short name T130
Test name
Test status
Simulation time 3767071073 ps
CPU time 282.34 seconds
Started Jul 14 05:59:44 PM PDT 24
Finished Jul 14 06:04:27 PM PDT 24
Peak memory 265560 kb
Host smart-f710c182-c825-4be6-b20c-99dd3a22647e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4251765114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.4251765114
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.224110060
Short name T166
Test name
Test status
Simulation time 3319811786 ps
CPU time 76.75 seconds
Started Jul 14 05:59:32 PM PDT 24
Finished Jul 14 06:00:50 PM PDT 24
Peak memory 248784 kb
Host smart-8fda57ae-3d41-4313-8781-8d7825ab3815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=224110060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.224110060
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2136247244
Short name T307
Test name
Test status
Simulation time 33184503579 ps
CPU time 360.24 seconds
Started Jul 14 05:06:23 PM PDT 24
Finished Jul 14 05:12:24 PM PDT 24
Peak memory 256412 kb
Host smart-5405c767-811e-45df-b8d6-799ac1c55fdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136247244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2136247244
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3836841039
Short name T245
Test name
Test status
Simulation time 2320332304 ps
CPU time 42.19 seconds
Started Jul 14 05:08:00 PM PDT 24
Finished Jul 14 05:08:43 PM PDT 24
Peak memory 256748 kb
Host smart-f8803ab5-ff11-46e8-9f1b-5cecb9d2eadd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38368
41039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3836841039
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1022632334
Short name T82
Test name
Test status
Simulation time 18145439310 ps
CPU time 1127.21 seconds
Started Jul 14 05:08:08 PM PDT 24
Finished Jul 14 05:26:56 PM PDT 24
Peak memory 273032 kb
Host smart-337d9ec4-3de6-4c81-b25b-3f8202f937b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022632334 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1022632334
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2908111753
Short name T320
Test name
Test status
Simulation time 69270714124 ps
CPU time 1595.54 seconds
Started Jul 14 05:08:11 PM PDT 24
Finished Jul 14 05:34:47 PM PDT 24
Peak memory 290248 kb
Host smart-a5b3e8fb-76b7-4452-8813-d5d259426ac9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908111753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2908111753
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1360220401
Short name T267
Test name
Test status
Simulation time 1428061997 ps
CPU time 49.71 seconds
Started Jul 14 05:08:08 PM PDT 24
Finished Jul 14 05:08:58 PM PDT 24
Peak memory 249108 kb
Host smart-08452cb8-1992-46e6-b12e-f12c14d40e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13602
20401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1360220401
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3493566454
Short name T616
Test name
Test status
Simulation time 222135491 ps
CPU time 17.51 seconds
Started Jul 14 05:08:51 PM PDT 24
Finished Jul 14 05:09:10 PM PDT 24
Peak memory 248492 kb
Host smart-7d7e3e07-23cf-4445-b39d-a437301f8331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34935
66454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3493566454
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.4117310835
Short name T57
Test name
Test status
Simulation time 64381168325 ps
CPU time 2084.84 seconds
Started Jul 14 05:09:10 PM PDT 24
Finished Jul 14 05:43:56 PM PDT 24
Peak memory 286244 kb
Host smart-8dbef3b0-db97-4e06-9197-24b0cf7668d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117310835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.4117310835
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2623116280
Short name T250
Test name
Test status
Simulation time 4340590192 ps
CPU time 58.52 seconds
Started Jul 14 05:09:08 PM PDT 24
Finished Jul 14 05:10:07 PM PDT 24
Peak memory 256476 kb
Host smart-21e9a25d-6624-45fc-a9d7-8d9b0ae135be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26231
16280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2623116280
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2708521909
Short name T276
Test name
Test status
Simulation time 9788178922 ps
CPU time 735.6 seconds
Started Jul 14 05:09:23 PM PDT 24
Finished Jul 14 05:21:40 PM PDT 24
Peak memory 273616 kb
Host smart-a35ef367-8b03-4224-9b9f-8b08647e7ccd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708521909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2708521909
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.670994709
Short name T257
Test name
Test status
Simulation time 238580559 ps
CPU time 29.29 seconds
Started Jul 14 05:09:47 PM PDT 24
Finished Jul 14 05:10:17 PM PDT 24
Peak memory 249128 kb
Host smart-2cc8deb6-5b44-4a48-a5b8-aa90eb6345db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67099
4709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.670994709
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3602641015
Short name T664
Test name
Test status
Simulation time 1461866896 ps
CPU time 46.65 seconds
Started Jul 14 05:10:15 PM PDT 24
Finished Jul 14 05:11:03 PM PDT 24
Peak memory 256400 kb
Host smart-e3126329-db59-4277-80b1-aafa3a253248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36026
41015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3602641015
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.4006143585
Short name T255
Test name
Test status
Simulation time 5042232582 ps
CPU time 46.59 seconds
Started Jul 14 05:10:28 PM PDT 24
Finished Jul 14 05:11:15 PM PDT 24
Peak memory 248416 kb
Host smart-ae256a56-75aa-4d77-ae4f-5bb434d45790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40061
43585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4006143585
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2192237250
Short name T101
Test name
Test status
Simulation time 63626888657 ps
CPU time 2231.09 seconds
Started Jul 14 05:10:55 PM PDT 24
Finished Jul 14 05:48:06 PM PDT 24
Peak memory 290480 kb
Host smart-bec3b52f-7921-4b4b-ac12-36b83ba0c4f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192237250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2192237250
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2752047412
Short name T277
Test name
Test status
Simulation time 72928191032 ps
CPU time 657.36 seconds
Started Jul 14 05:11:02 PM PDT 24
Finished Jul 14 05:22:00 PM PDT 24
Peak memory 257428 kb
Host smart-026b3f74-1b03-4ce0-bc45-dace59f68e82
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752047412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2752047412
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.533213179
Short name T78
Test name
Test status
Simulation time 309017220346 ps
CPU time 1635.23 seconds
Started Jul 14 05:12:28 PM PDT 24
Finished Jul 14 05:39:44 PM PDT 24
Peak memory 288924 kb
Host smart-dca6b995-c81a-405a-906a-b8d60b8b0bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533213179 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.533213179
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.4076338896
Short name T256
Test name
Test status
Simulation time 732008382 ps
CPU time 25.81 seconds
Started Jul 14 05:14:27 PM PDT 24
Finished Jul 14 05:14:53 PM PDT 24
Peak memory 248760 kb
Host smart-73c8b763-dd8d-4e67-a537-c4731b3d4201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40763
38896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4076338896
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1033234892
Short name T241
Test name
Test status
Simulation time 1085381694 ps
CPU time 28.24 seconds
Started Jul 14 05:07:14 PM PDT 24
Finished Jul 14 05:07:43 PM PDT 24
Peak memory 249116 kb
Host smart-7496db19-29d1-447f-9f3e-355b8e67a2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10332
34892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1033234892
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3250796271
Short name T96
Test name
Test status
Simulation time 378770579 ps
CPU time 21.82 seconds
Started Jul 14 05:08:30 PM PDT 24
Finished Jul 14 05:08:52 PM PDT 24
Peak memory 257116 kb
Host smart-b495d5a1-858a-4d12-960e-dab55fe3795e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32507
96271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3250796271
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3409934549
Short name T129
Test name
Test status
Simulation time 24725630902 ps
CPU time 321.83 seconds
Started Jul 14 05:59:33 PM PDT 24
Finished Jul 14 06:04:56 PM PDT 24
Peak memory 273508 kb
Host smart-6a16b0fa-3e62-45f9-a044-53dbf11c1b74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3409934549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3409934549
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3772878710
Short name T156
Test name
Test status
Simulation time 1815304994 ps
CPU time 71.97 seconds
Started Jul 14 05:59:30 PM PDT 24
Finished Jul 14 06:00:43 PM PDT 24
Peak memory 240476 kb
Host smart-e87a353f-2da3-483c-b46d-061d51f246c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3772878710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3772878710
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3894609577
Short name T165
Test name
Test status
Simulation time 165063602 ps
CPU time 3.65 seconds
Started Jul 14 05:59:32 PM PDT 24
Finished Jul 14 05:59:36 PM PDT 24
Peak memory 236624 kb
Host smart-d307bbe7-377e-4370-94e0-71ec9fc5d795
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3894609577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3894609577
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1865975199
Short name T164
Test name
Test status
Simulation time 154096704 ps
CPU time 19.52 seconds
Started Jul 14 05:59:42 PM PDT 24
Finished Jul 14 06:00:03 PM PDT 24
Peak memory 240484 kb
Host smart-242ab563-a7f2-4999-86f8-65e341483157
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1865975199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1865975199
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1940060081
Short name T157
Test name
Test status
Simulation time 115388767 ps
CPU time 3.2 seconds
Started Jul 14 05:59:06 PM PDT 24
Finished Jul 14 05:59:09 PM PDT 24
Peak memory 237804 kb
Host smart-644b5b7b-aafc-4925-9223-b0bc4e271687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1940060081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1940060081
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3661839331
Short name T154
Test name
Test status
Simulation time 3660675891 ps
CPU time 71.08 seconds
Started Jul 14 05:59:42 PM PDT 24
Finished Jul 14 06:00:53 PM PDT 24
Peak memory 240564 kb
Host smart-256dec19-a61a-4fa0-b9ab-0d063a4c55ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3661839331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3661839331
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3563987400
Short name T161
Test name
Test status
Simulation time 126850849 ps
CPU time 4.08 seconds
Started Jul 14 05:59:42 PM PDT 24
Finished Jul 14 05:59:47 PM PDT 24
Peak memory 236520 kb
Host smart-9f054c4e-34b8-4b91-ba9b-8105641b891d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3563987400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3563987400
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2994991359
Short name T162
Test name
Test status
Simulation time 360996797 ps
CPU time 47.35 seconds
Started Jul 14 05:59:46 PM PDT 24
Finished Jul 14 06:00:34 PM PDT 24
Peak memory 240496 kb
Host smart-e2007696-547c-41d6-be60-804a6e7d2fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2994991359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2994991359
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1285713232
Short name T159
Test name
Test status
Simulation time 156736650 ps
CPU time 4.08 seconds
Started Jul 14 05:59:35 PM PDT 24
Finished Jul 14 05:59:40 PM PDT 24
Peak memory 237560 kb
Host smart-0dfb8621-b422-4ef1-817e-6dde6f7d38a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1285713232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1285713232
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2176498041
Short name T167
Test name
Test status
Simulation time 223842767 ps
CPU time 4 seconds
Started Jul 14 05:59:32 PM PDT 24
Finished Jul 14 05:59:37 PM PDT 24
Peak memory 238476 kb
Host smart-326a8be6-1a89-449d-9232-13dab4f80b09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2176498041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2176498041
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.459482437
Short name T131
Test name
Test status
Simulation time 3301905219 ps
CPU time 219.06 seconds
Started Jul 14 05:59:33 PM PDT 24
Finished Jul 14 06:03:13 PM PDT 24
Peak memory 265540 kb
Host smart-31324b63-99e4-4863-a5b9-10ce6619c928
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=459482437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.459482437
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3212074565
Short name T158
Test name
Test status
Simulation time 78515789 ps
CPU time 3.06 seconds
Started Jul 14 05:59:26 PM PDT 24
Finished Jul 14 05:59:30 PM PDT 24
Peak memory 237784 kb
Host smart-1fd8950b-514e-4ecf-9a78-e228eb9b0c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3212074565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3212074565
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1286088986
Short name T168
Test name
Test status
Simulation time 1041818296 ps
CPU time 34.03 seconds
Started Jul 14 05:59:32 PM PDT 24
Finished Jul 14 06:00:07 PM PDT 24
Peak memory 237672 kb
Host smart-d37b6e76-b062-41ac-b9d9-6a678bb6a602
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1286088986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1286088986
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2598827296
Short name T148
Test name
Test status
Simulation time 56537057 ps
CPU time 2.8 seconds
Started Jul 14 05:59:39 PM PDT 24
Finished Jul 14 05:59:42 PM PDT 24
Peak memory 237564 kb
Host smart-3aef4c6a-4e9e-449f-a481-393e6f3169b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2598827296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2598827296
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1282942391
Short name T155
Test name
Test status
Simulation time 905930084 ps
CPU time 67.02 seconds
Started Jul 14 05:59:13 PM PDT 24
Finished Jul 14 06:00:21 PM PDT 24
Peak memory 246104 kb
Host smart-11c7ba0e-8ab2-45e8-bd83-fe0ddf6bb3a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1282942391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1282942391
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.447012690
Short name T163
Test name
Test status
Simulation time 598815765 ps
CPU time 27.38 seconds
Started Jul 14 05:59:14 PM PDT 24
Finished Jul 14 05:59:42 PM PDT 24
Peak memory 245964 kb
Host smart-ec93a21c-863d-4019-98ae-786a2d1f0474
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=447012690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.447012690
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3623733150
Short name T160
Test name
Test status
Simulation time 48487839 ps
CPU time 2.39 seconds
Started Jul 14 05:59:21 PM PDT 24
Finished Jul 14 05:59:24 PM PDT 24
Peak memory 237548 kb
Host smart-8b16b4ed-efad-48bd-82c9-ba84ce875cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3623733150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3623733150
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.904596434
Short name T173
Test name
Test status
Simulation time 101225571 ps
CPU time 2.8 seconds
Started Jul 14 05:59:27 PM PDT 24
Finished Jul 14 05:59:30 PM PDT 24
Peak memory 238004 kb
Host smart-77389bc9-e9d2-47c6-918f-9e2b0e7e3d60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=904596434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.904596434
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1713115052
Short name T169
Test name
Test status
Simulation time 93745032 ps
CPU time 2.43 seconds
Started Jul 14 05:59:24 PM PDT 24
Finished Jul 14 05:59:27 PM PDT 24
Peak memory 237364 kb
Host smart-6571692e-2de5-44e5-9667-ba9d2b201583
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1713115052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1713115052
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.734189006
Short name T823
Test name
Test status
Simulation time 8542800548 ps
CPU time 293.99 seconds
Started Jul 14 05:59:15 PM PDT 24
Finished Jul 14 06:04:10 PM PDT 24
Peak memory 242016 kb
Host smart-112a516b-b1ae-487d-a67c-0477cdb22c25
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=734189006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.734189006
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2130317618
Short name T761
Test name
Test status
Simulation time 167419233 ps
CPU time 6.32 seconds
Started Jul 14 05:59:11 PM PDT 24
Finished Jul 14 05:59:18 PM PDT 24
Peak memory 248720 kb
Host smart-cc577bdb-f5c4-4217-9454-1c4610b240c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2130317618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2130317618
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3532760299
Short name T830
Test name
Test status
Simulation time 369710918 ps
CPU time 9.07 seconds
Started Jul 14 05:59:07 PM PDT 24
Finished Jul 14 05:59:16 PM PDT 24
Peak memory 237460 kb
Host smart-3e7169c8-7bed-494b-8e8a-4f54ac8a036a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3532760299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3532760299
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3805034463
Short name T743
Test name
Test status
Simulation time 6295787 ps
CPU time 1.46 seconds
Started Jul 14 05:59:06 PM PDT 24
Finished Jul 14 05:59:08 PM PDT 24
Peak memory 237560 kb
Host smart-9bb7e437-e031-4eb4-823b-c36d7687026b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3805034463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3805034463
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.474697109
Short name T793
Test name
Test status
Simulation time 186229486 ps
CPU time 25.04 seconds
Started Jul 14 05:59:16 PM PDT 24
Finished Jul 14 05:59:41 PM PDT 24
Peak memory 245776 kb
Host smart-aa308531-8500-4b02-9575-8806748e82e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=474697109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.474697109
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2914024726
Short name T147
Test name
Test status
Simulation time 7798985001 ps
CPU time 156.02 seconds
Started Jul 14 05:59:09 PM PDT 24
Finished Jul 14 06:01:45 PM PDT 24
Peak memory 265328 kb
Host smart-ec912665-b2cf-4bd1-85b8-078f88b44893
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2914024726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2914024726
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2526328681
Short name T236
Test name
Test status
Simulation time 117850514 ps
CPU time 9.42 seconds
Started Jul 14 05:59:08 PM PDT 24
Finished Jul 14 05:59:18 PM PDT 24
Peak memory 248772 kb
Host smart-5e68a3e3-45b0-46ca-bc6a-7ceb5bdb1f3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2526328681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2526328681
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.32594231
Short name T180
Test name
Test status
Simulation time 3649700575 ps
CPU time 79.84 seconds
Started Jul 14 05:59:14 PM PDT 24
Finished Jul 14 06:00:34 PM PDT 24
Peak memory 237592 kb
Host smart-18a36e2d-9d9b-4b41-aecd-62df97cc11f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=32594231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.32594231
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.4274506649
Short name T752
Test name
Test status
Simulation time 2886543349 ps
CPU time 195.8 seconds
Started Jul 14 05:59:12 PM PDT 24
Finished Jul 14 06:02:28 PM PDT 24
Peak memory 237632 kb
Host smart-8d5b4bdd-e4f9-4c45-bef9-2d1328c2d504
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4274506649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.4274506649
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4182451724
Short name T807
Test name
Test status
Simulation time 194257038 ps
CPU time 5.69 seconds
Started Jul 14 05:59:12 PM PDT 24
Finished Jul 14 05:59:18 PM PDT 24
Peak memory 248704 kb
Host smart-07e70718-cfb6-4af2-a494-082beebbbca3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4182451724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.4182451724
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1496959223
Short name T755
Test name
Test status
Simulation time 562382470 ps
CPU time 5.88 seconds
Started Jul 14 05:59:15 PM PDT 24
Finished Jul 14 05:59:22 PM PDT 24
Peak memory 240492 kb
Host smart-b53e7a4b-e320-43cf-ab53-e633d8e09660
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496959223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1496959223
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4056499394
Short name T772
Test name
Test status
Simulation time 118076814 ps
CPU time 8.49 seconds
Started Jul 14 05:59:13 PM PDT 24
Finished Jul 14 05:59:22 PM PDT 24
Peak memory 236500 kb
Host smart-47a182b1-e8aa-4cc9-bfcf-fd54b85aa167
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4056499394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.4056499394
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3795892401
Short name T759
Test name
Test status
Simulation time 21473914 ps
CPU time 1.37 seconds
Started Jul 14 05:59:15 PM PDT 24
Finished Jul 14 05:59:17 PM PDT 24
Peak memory 237392 kb
Host smart-53294a9c-ef08-4aac-adec-d9134f3a2997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3795892401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3795892401
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3253922736
Short name T810
Test name
Test status
Simulation time 650757033 ps
CPU time 21.64 seconds
Started Jul 14 05:59:15 PM PDT 24
Finished Jul 14 05:59:38 PM PDT 24
Peak memory 245684 kb
Host smart-aadb2b94-2689-403f-ac71-58b8c3aeaa75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3253922736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3253922736
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.847134327
Short name T725
Test name
Test status
Simulation time 41083389 ps
CPU time 5.36 seconds
Started Jul 14 05:59:11 PM PDT 24
Finished Jul 14 05:59:17 PM PDT 24
Peak memory 248820 kb
Host smart-1511b757-63b5-4b56-950b-23bfaa7aaea0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=847134327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.847134327
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.808640392
Short name T149
Test name
Test status
Simulation time 23381947 ps
CPU time 2.49 seconds
Started Jul 14 05:59:14 PM PDT 24
Finished Jul 14 05:59:17 PM PDT 24
Peak memory 236600 kb
Host smart-83947190-af88-4b74-938e-a87b892bec94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=808640392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.808640392
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3954576376
Short name T818
Test name
Test status
Simulation time 997079112 ps
CPU time 12.69 seconds
Started Jul 14 05:59:35 PM PDT 24
Finished Jul 14 05:59:48 PM PDT 24
Peak memory 251824 kb
Host smart-5cb4d46c-9f34-4676-ada6-08360d9c5e1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954576376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3954576376
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2214910271
Short name T816
Test name
Test status
Simulation time 40181700 ps
CPU time 3.68 seconds
Started Jul 14 05:59:32 PM PDT 24
Finished Jul 14 05:59:36 PM PDT 24
Peak memory 237488 kb
Host smart-99bd79d4-3102-4c88-847d-cf9a4f816b5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2214910271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2214910271
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1491673217
Short name T767
Test name
Test status
Simulation time 6534347 ps
CPU time 1.41 seconds
Started Jul 14 05:59:34 PM PDT 24
Finished Jul 14 05:59:36 PM PDT 24
Peak memory 236540 kb
Host smart-d1cd2284-4c1a-4d69-a6b9-c3d045bd2432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1491673217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1491673217
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.413509541
Short name T789
Test name
Test status
Simulation time 2159056057 ps
CPU time 46.23 seconds
Started Jul 14 05:59:30 PM PDT 24
Finished Jul 14 06:00:18 PM PDT 24
Peak memory 244776 kb
Host smart-dede4ef7-c45b-4e8f-b68f-c024f0fd608f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=413509541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.413509541
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1951912435
Short name T145
Test name
Test status
Simulation time 24122131398 ps
CPU time 388.33 seconds
Started Jul 14 05:59:28 PM PDT 24
Finished Jul 14 06:05:58 PM PDT 24
Peak memory 265412 kb
Host smart-58b64a56-009c-4bf4-a745-4a56b67e8c96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1951912435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1951912435
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2484228621
Short name T137
Test name
Test status
Simulation time 25189762561 ps
CPU time 534.38 seconds
Started Jul 14 05:59:27 PM PDT 24
Finished Jul 14 06:08:23 PM PDT 24
Peak memory 265560 kb
Host smart-d97327ca-43c9-4d05-b1b5-1be9f2eb5e09
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484228621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2484228621
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3232898061
Short name T821
Test name
Test status
Simulation time 310480808 ps
CPU time 12.3 seconds
Started Jul 14 05:59:37 PM PDT 24
Finished Jul 14 05:59:51 PM PDT 24
Peak memory 248724 kb
Host smart-3dd0ae54-c82f-45c7-bc82-af4dc4ea86d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3232898061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3232898061
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3662597847
Short name T762
Test name
Test status
Simulation time 118923320 ps
CPU time 10.45 seconds
Started Jul 14 05:59:31 PM PDT 24
Finished Jul 14 05:59:42 PM PDT 24
Peak memory 256964 kb
Host smart-2987b40a-40a3-4a50-ab0a-a98d5951aa34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662597847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3662597847
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.18864367
Short name T791
Test name
Test status
Simulation time 51866496 ps
CPU time 4.53 seconds
Started Jul 14 05:59:33 PM PDT 24
Finished Jul 14 05:59:38 PM PDT 24
Peak memory 237560 kb
Host smart-3f53ee67-9c7d-46c3-b44e-4c827031711a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=18864367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.18864367
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3445112142
Short name T790
Test name
Test status
Simulation time 7591881 ps
CPU time 1.47 seconds
Started Jul 14 05:59:31 PM PDT 24
Finished Jul 14 05:59:33 PM PDT 24
Peak memory 237544 kb
Host smart-27524213-97a3-4193-b358-6deabf66cabc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3445112142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3445112142
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3646090602
Short name T801
Test name
Test status
Simulation time 298585946 ps
CPU time 22.4 seconds
Started Jul 14 05:59:35 PM PDT 24
Finished Jul 14 05:59:59 PM PDT 24
Peak memory 244808 kb
Host smart-efe0e76d-05df-49f1-8acb-23ab5d43fa3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3646090602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3646090602
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3263582254
Short name T125
Test name
Test status
Simulation time 10416719667 ps
CPU time 130.94 seconds
Started Jul 14 05:59:37 PM PDT 24
Finished Jul 14 06:01:49 PM PDT 24
Peak memory 265356 kb
Host smart-9ece4c02-4074-46ab-bef0-9ea84cf53bf1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3263582254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3263582254
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1253682124
Short name T124
Test name
Test status
Simulation time 6610946134 ps
CPU time 580.84 seconds
Started Jul 14 05:59:32 PM PDT 24
Finished Jul 14 06:09:14 PM PDT 24
Peak memory 269940 kb
Host smart-e24d5426-8e56-4190-aaee-17d3741affdb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253682124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1253682124
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2381386884
Short name T785
Test name
Test status
Simulation time 255815879 ps
CPU time 10.04 seconds
Started Jul 14 05:59:35 PM PDT 24
Finished Jul 14 05:59:47 PM PDT 24
Peak memory 249792 kb
Host smart-bd8228bc-1019-46c9-ba1a-9e25f19b19cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2381386884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2381386884
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1033576705
Short name T338
Test name
Test status
Simulation time 190974000 ps
CPU time 4.99 seconds
Started Jul 14 05:59:32 PM PDT 24
Finished Jul 14 05:59:38 PM PDT 24
Peak memory 237620 kb
Host smart-596a552d-f1f1-4d8c-9b8e-beff087b71eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033576705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1033576705
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1897276802
Short name T787
Test name
Test status
Simulation time 498800771 ps
CPU time 9.28 seconds
Started Jul 14 05:59:36 PM PDT 24
Finished Jul 14 05:59:46 PM PDT 24
Peak memory 240528 kb
Host smart-f1e8a14c-a653-4088-8e1f-b93dff3e55dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1897276802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1897276802
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.641014039
Short name T745
Test name
Test status
Simulation time 16339452 ps
CPU time 1.31 seconds
Started Jul 14 05:59:34 PM PDT 24
Finished Jul 14 05:59:36 PM PDT 24
Peak memory 236496 kb
Host smart-8f838f2e-70a8-4c0c-bbcd-601e15c09e8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=641014039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.641014039
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2012272973
Short name T770
Test name
Test status
Simulation time 700315427 ps
CPU time 23.95 seconds
Started Jul 14 05:59:35 PM PDT 24
Finished Jul 14 05:59:59 PM PDT 24
Peak memory 245756 kb
Host smart-95456cce-3ab2-48cf-a702-0267181c4ba7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2012272973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2012272973
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2119188119
Short name T827
Test name
Test status
Simulation time 715384283 ps
CPU time 12.42 seconds
Started Jul 14 05:59:38 PM PDT 24
Finished Jul 14 05:59:51 PM PDT 24
Peak memory 248600 kb
Host smart-e04f248f-443a-4f8a-a4f8-92d91d133e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2119188119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2119188119
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.258605265
Short name T813
Test name
Test status
Simulation time 117037309 ps
CPU time 9.53 seconds
Started Jul 14 05:59:35 PM PDT 24
Finished Jul 14 05:59:45 PM PDT 24
Peak memory 253944 kb
Host smart-c8441a4f-3119-43cd-b740-398ddfbe714c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258605265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.258605265
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3626772041
Short name T828
Test name
Test status
Simulation time 55746976 ps
CPU time 6.52 seconds
Started Jul 14 05:59:32 PM PDT 24
Finished Jul 14 05:59:38 PM PDT 24
Peak memory 237552 kb
Host smart-ba580566-35c1-4985-8d6c-87aa7fd959db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3626772041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3626772041
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1341735050
Short name T335
Test name
Test status
Simulation time 12879211 ps
CPU time 1.34 seconds
Started Jul 14 05:59:37 PM PDT 24
Finished Jul 14 05:59:40 PM PDT 24
Peak memory 236608 kb
Host smart-f9ade713-572a-472b-8e2d-a6ced6df9ec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1341735050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1341735050
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1571907363
Short name T763
Test name
Test status
Simulation time 384129581 ps
CPU time 26.75 seconds
Started Jul 14 05:59:30 PM PDT 24
Finished Jul 14 05:59:58 PM PDT 24
Peak memory 245744 kb
Host smart-6749561f-f32e-474f-98c4-2b86000d0064
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1571907363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1571907363
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1041987563
Short name T142
Test name
Test status
Simulation time 75104108241 ps
CPU time 1026.87 seconds
Started Jul 14 05:59:33 PM PDT 24
Finished Jul 14 06:16:41 PM PDT 24
Peak memory 265544 kb
Host smart-f70babb8-f681-4a43-9e3f-02fb556d69f5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041987563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1041987563
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3163947072
Short name T782
Test name
Test status
Simulation time 1304426044 ps
CPU time 24.51 seconds
Started Jul 14 05:59:32 PM PDT 24
Finished Jul 14 05:59:57 PM PDT 24
Peak memory 248864 kb
Host smart-7ad0118d-7cea-44ab-896c-d6afed9015a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3163947072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3163947072
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4225382064
Short name T232
Test name
Test status
Simulation time 138506077 ps
CPU time 10.79 seconds
Started Jul 14 05:59:40 PM PDT 24
Finished Jul 14 05:59:52 PM PDT 24
Peak memory 238272 kb
Host smart-4ba7ec80-4d00-47e9-8959-f6d79363b19a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225382064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.4225382064
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.75103261
Short name T177
Test name
Test status
Simulation time 460679583 ps
CPU time 9.01 seconds
Started Jul 14 05:59:45 PM PDT 24
Finished Jul 14 05:59:55 PM PDT 24
Peak memory 237576 kb
Host smart-0ea223dc-ee81-4e00-8140-280701a26381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=75103261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.75103261
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3743247153
Short name T337
Test name
Test status
Simulation time 10649289 ps
CPU time 1.36 seconds
Started Jul 14 05:59:38 PM PDT 24
Finished Jul 14 05:59:40 PM PDT 24
Peak memory 237548 kb
Host smart-c8bbd6b5-e3b8-4a15-8346-db9fed135e0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3743247153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3743247153
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2078579117
Short name T788
Test name
Test status
Simulation time 334270620 ps
CPU time 26.32 seconds
Started Jul 14 05:59:40 PM PDT 24
Finished Jul 14 06:00:07 PM PDT 24
Peak memory 245696 kb
Host smart-727a88f3-c82f-466f-8847-256a6a52a8ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2078579117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2078579117
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3810411411
Short name T122
Test name
Test status
Simulation time 2101427482 ps
CPU time 175.9 seconds
Started Jul 14 05:59:35 PM PDT 24
Finished Jul 14 06:02:31 PM PDT 24
Peak memory 265476 kb
Host smart-ab83b3ba-a097-44d3-b58c-2e3b2aac9ce6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3810411411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3810411411
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3074746694
Short name T141
Test name
Test status
Simulation time 13726591103 ps
CPU time 1120.82 seconds
Started Jul 14 05:59:30 PM PDT 24
Finished Jul 14 06:18:12 PM PDT 24
Peak memory 265476 kb
Host smart-028ba9d5-a706-4749-b0a1-805d3529fd81
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074746694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3074746694
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.4204080451
Short name T805
Test name
Test status
Simulation time 62747282 ps
CPU time 7.64 seconds
Started Jul 14 05:59:34 PM PDT 24
Finished Jul 14 05:59:42 PM PDT 24
Peak memory 247256 kb
Host smart-8227a59a-7b4f-4a87-a182-48dfbe43e2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4204080451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.4204080451
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1562662665
Short name T768
Test name
Test status
Simulation time 105592981 ps
CPU time 8.29 seconds
Started Jul 14 05:59:38 PM PDT 24
Finished Jul 14 05:59:47 PM PDT 24
Peak memory 240720 kb
Host smart-96d520f2-54cc-4c8e-9cee-6b20061e541d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562662665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1562662665
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2345370686
Short name T757
Test name
Test status
Simulation time 212247617 ps
CPU time 5.64 seconds
Started Jul 14 05:59:40 PM PDT 24
Finished Jul 14 05:59:47 PM PDT 24
Peak memory 237448 kb
Host smart-0fbf778f-b5dc-420c-8948-c581820c1451
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2345370686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2345370686
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4015997691
Short name T723
Test name
Test status
Simulation time 8202819 ps
CPU time 1.5 seconds
Started Jul 14 05:59:42 PM PDT 24
Finished Jul 14 05:59:45 PM PDT 24
Peak memory 237568 kb
Host smart-33f21d1c-300f-465d-ac27-67b2df4a1af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4015997691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.4015997691
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1484353390
Short name T775
Test name
Test status
Simulation time 735743485 ps
CPU time 23.73 seconds
Started Jul 14 05:59:37 PM PDT 24
Finished Jul 14 06:00:01 PM PDT 24
Peak memory 248684 kb
Host smart-e1b473f7-6a05-4dbd-a894-79f61659ef7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1484353390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1484353390
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2542900400
Short name T341
Test name
Test status
Simulation time 4428757493 ps
CPU time 696.56 seconds
Started Jul 14 05:59:39 PM PDT 24
Finished Jul 14 06:11:16 PM PDT 24
Peak memory 265304 kb
Host smart-bacf63c1-8127-4429-b7c1-9b3e1dc65c1c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542900400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2542900400
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.376849763
Short name T727
Test name
Test status
Simulation time 883989705 ps
CPU time 11.03 seconds
Started Jul 14 05:59:38 PM PDT 24
Finished Jul 14 05:59:50 PM PDT 24
Peak memory 247660 kb
Host smart-20cd9c61-cc04-43e3-9fa4-c425911baf2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=376849763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.376849763
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.245358624
Short name T797
Test name
Test status
Simulation time 610413265 ps
CPU time 12.61 seconds
Started Jul 14 05:59:40 PM PDT 24
Finished Jul 14 05:59:54 PM PDT 24
Peak memory 242992 kb
Host smart-3487b7de-be4e-4ae3-a431-a6e3af349468
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245358624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.245358624
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1517266058
Short name T174
Test name
Test status
Simulation time 484435467 ps
CPU time 4.89 seconds
Started Jul 14 05:59:41 PM PDT 24
Finished Jul 14 05:59:46 PM PDT 24
Peak memory 236352 kb
Host smart-7d244c23-f9e1-429c-b236-a6f68fc043d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1517266058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1517266058
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1354638267
Short name T732
Test name
Test status
Simulation time 8457318 ps
CPU time 1.48 seconds
Started Jul 14 05:59:40 PM PDT 24
Finished Jul 14 05:59:42 PM PDT 24
Peak memory 237552 kb
Host smart-bf6fdf99-d332-4909-8cac-903fd505ed0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1354638267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1354638267
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3891483906
Short name T815
Test name
Test status
Simulation time 602473682 ps
CPU time 40.77 seconds
Started Jul 14 05:59:42 PM PDT 24
Finished Jul 14 06:00:24 PM PDT 24
Peak memory 244704 kb
Host smart-9723265b-10f5-4046-a195-d6b60755e4d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3891483906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3891483906
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.968819479
Short name T126
Test name
Test status
Simulation time 9092812410 ps
CPU time 309.19 seconds
Started Jul 14 05:59:46 PM PDT 24
Finished Jul 14 06:04:56 PM PDT 24
Peak memory 265416 kb
Host smart-4aa18204-7ea0-4d08-a093-65a3c81da291
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968819479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.968819479
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1050452436
Short name T806
Test name
Test status
Simulation time 15602657 ps
CPU time 2.73 seconds
Started Jul 14 05:59:40 PM PDT 24
Finished Jul 14 05:59:44 PM PDT 24
Peak memory 248364 kb
Host smart-a0cb2002-7eb9-4907-9c8d-5b08f8d59d48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1050452436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1050452436
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1544124710
Short name T742
Test name
Test status
Simulation time 223149954 ps
CPU time 10.54 seconds
Started Jul 14 05:59:38 PM PDT 24
Finished Jul 14 05:59:50 PM PDT 24
Peak memory 251284 kb
Host smart-03b89883-1b13-4d36-ba52-bdfbb08b40b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544124710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1544124710
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2095040376
Short name T814
Test name
Test status
Simulation time 34215192 ps
CPU time 5.95 seconds
Started Jul 14 05:59:38 PM PDT 24
Finished Jul 14 05:59:44 PM PDT 24
Peak memory 237552 kb
Host smart-b151b704-d245-4289-b85b-4466d966931b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2095040376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2095040376
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3044221770
Short name T336
Test name
Test status
Simulation time 15685286 ps
CPU time 1.38 seconds
Started Jul 14 05:59:42 PM PDT 24
Finished Jul 14 05:59:44 PM PDT 24
Peak memory 237564 kb
Host smart-8416691e-94d8-4c21-8753-e831ec9effdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3044221770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3044221770
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2733669132
Short name T175
Test name
Test status
Simulation time 672679004 ps
CPU time 26.91 seconds
Started Jul 14 05:59:40 PM PDT 24
Finished Jul 14 06:00:07 PM PDT 24
Peak memory 245680 kb
Host smart-5d684be1-a858-4848-84c5-3616cb3c5ec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2733669132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2733669132
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.736663187
Short name T123
Test name
Test status
Simulation time 12721341318 ps
CPU time 571.85 seconds
Started Jul 14 05:59:38 PM PDT 24
Finished Jul 14 06:09:10 PM PDT 24
Peak memory 265552 kb
Host smart-96dc534b-9ddd-44d2-8496-aed33c54a498
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736663187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.736663187
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3603591280
Short name T719
Test name
Test status
Simulation time 234225986 ps
CPU time 9.59 seconds
Started Jul 14 05:59:41 PM PDT 24
Finished Jul 14 05:59:51 PM PDT 24
Peak memory 248732 kb
Host smart-dc7ea595-cb03-4ea5-9f3d-3b1129e51e66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3603591280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3603591280
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2178037385
Short name T778
Test name
Test status
Simulation time 111564981 ps
CPU time 11.12 seconds
Started Jul 14 05:59:39 PM PDT 24
Finished Jul 14 05:59:51 PM PDT 24
Peak memory 252720 kb
Host smart-ba9a055c-13b8-4164-83c6-675c77cd8a1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178037385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2178037385
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.537557848
Short name T808
Test name
Test status
Simulation time 102090555 ps
CPU time 5.23 seconds
Started Jul 14 05:59:45 PM PDT 24
Finished Jul 14 05:59:51 PM PDT 24
Peak memory 237576 kb
Host smart-8784e5a7-25c1-486e-a74c-d213bcc54e5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=537557848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.537557848
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2022525322
Short name T731
Test name
Test status
Simulation time 13475123 ps
CPU time 1.56 seconds
Started Jul 14 05:59:42 PM PDT 24
Finished Jul 14 05:59:44 PM PDT 24
Peak memory 237556 kb
Host smart-d48355c6-7df8-4704-95a3-d29140f4e23e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2022525322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2022525322
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3868216710
Short name T179
Test name
Test status
Simulation time 10597226973 ps
CPU time 46.77 seconds
Started Jul 14 05:59:41 PM PDT 24
Finished Jul 14 06:00:29 PM PDT 24
Peak memory 245676 kb
Host smart-35a87a9a-c298-4932-9cad-88c2d830f0ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3868216710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3868216710
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1722018062
Short name T339
Test name
Test status
Simulation time 5023065941 ps
CPU time 598.53 seconds
Started Jul 14 05:59:42 PM PDT 24
Finished Jul 14 06:09:42 PM PDT 24
Peak memory 273568 kb
Host smart-68f9e848-87b5-4ad7-bfe7-5a3b11e65737
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722018062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1722018062
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1868252902
Short name T238
Test name
Test status
Simulation time 155776939 ps
CPU time 11.17 seconds
Started Jul 14 05:59:42 PM PDT 24
Finished Jul 14 05:59:53 PM PDT 24
Peak memory 248532 kb
Host smart-4353f6fd-e352-43a9-b4b8-853ca227cb70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1868252902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1868252902
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2955455691
Short name T735
Test name
Test status
Simulation time 141292018 ps
CPU time 6.41 seconds
Started Jul 14 05:59:46 PM PDT 24
Finished Jul 14 05:59:53 PM PDT 24
Peak memory 243592 kb
Host smart-04d62e12-27f7-404a-82c7-0d2d6a8d6e31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955455691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2955455691
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1983791459
Short name T769
Test name
Test status
Simulation time 268004926 ps
CPU time 5.65 seconds
Started Jul 14 05:59:38 PM PDT 24
Finished Jul 14 05:59:45 PM PDT 24
Peak memory 237540 kb
Host smart-6ee3ec7c-bd37-434d-81ef-4b20a3a95fb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1983791459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1983791459
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1541450393
Short name T824
Test name
Test status
Simulation time 20613335 ps
CPU time 1.67 seconds
Started Jul 14 05:59:40 PM PDT 24
Finished Jul 14 05:59:42 PM PDT 24
Peak memory 237572 kb
Host smart-7d42c319-81dc-45c8-95d2-d0ef039b9e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1541450393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1541450393
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1643128732
Short name T728
Test name
Test status
Simulation time 637475410 ps
CPU time 12.15 seconds
Started Jul 14 05:59:38 PM PDT 24
Finished Jul 14 05:59:51 PM PDT 24
Peak memory 240456 kb
Host smart-87be939c-48ea-4bf8-aded-f5000aa9ac6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1643128732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1643128732
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3128521247
Short name T822
Test name
Test status
Simulation time 292500503 ps
CPU time 24.45 seconds
Started Jul 14 05:59:38 PM PDT 24
Finished Jul 14 06:00:03 PM PDT 24
Peak memory 248764 kb
Host smart-48d5118d-ca68-4f1f-a6b2-9b67b6ee91d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3128521247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3128521247
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3131156104
Short name T234
Test name
Test status
Simulation time 34447617445 ps
CPU time 155.63 seconds
Started Jul 14 05:59:13 PM PDT 24
Finished Jul 14 06:01:49 PM PDT 24
Peak memory 237576 kb
Host smart-1d1e4afb-872c-4d11-9e31-f8900809edaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3131156104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3131156104
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1033353197
Short name T792
Test name
Test status
Simulation time 3408076070 ps
CPU time 95.62 seconds
Started Jul 14 05:59:11 PM PDT 24
Finished Jul 14 06:00:47 PM PDT 24
Peak memory 240304 kb
Host smart-62d7b780-bf2c-4f18-aac9-792c08800125
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1033353197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1033353197
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.492370928
Short name T235
Test name
Test status
Simulation time 222133113 ps
CPU time 5.01 seconds
Started Jul 14 05:59:14 PM PDT 24
Finished Jul 14 05:59:20 PM PDT 24
Peak memory 240484 kb
Host smart-14fd7226-4f45-4fb9-8087-b8b9d3c306e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=492370928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.492370928
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3751554856
Short name T172
Test name
Test status
Simulation time 268908471 ps
CPU time 5.62 seconds
Started Jul 14 05:59:11 PM PDT 24
Finished Jul 14 05:59:17 PM PDT 24
Peak memory 240308 kb
Host smart-7d93c8ba-0b9f-44b2-8155-7321262e331b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751554856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3751554856
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1133764494
Short name T750
Test name
Test status
Simulation time 191362362 ps
CPU time 5.58 seconds
Started Jul 14 05:59:13 PM PDT 24
Finished Jul 14 05:59:19 PM PDT 24
Peak memory 237460 kb
Host smart-c91a7566-4301-4c8a-9df3-7634a10bcce7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1133764494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1133764494
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2637017752
Short name T777
Test name
Test status
Simulation time 10556595 ps
CPU time 1.68 seconds
Started Jul 14 05:59:11 PM PDT 24
Finished Jul 14 05:59:13 PM PDT 24
Peak memory 236540 kb
Host smart-e8ecb164-54bf-4159-b244-31edd57bbfb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2637017752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2637017752
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.909077476
Short name T758
Test name
Test status
Simulation time 1807761899 ps
CPU time 38.24 seconds
Started Jul 14 05:59:11 PM PDT 24
Finished Jul 14 05:59:50 PM PDT 24
Peak memory 245752 kb
Host smart-c7afb628-cb11-4626-b375-22b0895c0a27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=909077476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.909077476
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4008008542
Short name T115
Test name
Test status
Simulation time 5146005627 ps
CPU time 332.56 seconds
Started Jul 14 05:59:13 PM PDT 24
Finished Jul 14 06:04:46 PM PDT 24
Peak memory 265408 kb
Host smart-8d6093f7-e0d5-4723-a3d9-7e853fdc85a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4008008542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.4008008542
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3837230589
Short name T120
Test name
Test status
Simulation time 6165939573 ps
CPU time 515.72 seconds
Started Jul 14 05:59:13 PM PDT 24
Finished Jul 14 06:07:49 PM PDT 24
Peak memory 265456 kb
Host smart-0c75fffc-9eff-4012-a801-e5a282be6561
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837230589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3837230589
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.488115004
Short name T795
Test name
Test status
Simulation time 118016990 ps
CPU time 8.41 seconds
Started Jul 14 05:59:15 PM PDT 24
Finished Jul 14 05:59:24 PM PDT 24
Peak memory 249740 kb
Host smart-ded01788-bd30-424c-bf28-75f0faffd23b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=488115004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.488115004
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2309637475
Short name T796
Test name
Test status
Simulation time 10432954 ps
CPU time 1.76 seconds
Started Jul 14 05:59:43 PM PDT 24
Finished Jul 14 05:59:46 PM PDT 24
Peak memory 237584 kb
Host smart-0b38e18d-4f10-4f74-84e5-8aa5b949885b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2309637475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2309637475
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3131252634
Short name T733
Test name
Test status
Simulation time 12757162 ps
CPU time 1.37 seconds
Started Jul 14 05:59:45 PM PDT 24
Finished Jul 14 05:59:47 PM PDT 24
Peak memory 237488 kb
Host smart-53090236-697e-4b85-9f53-3648eab6dd39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3131252634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3131252634
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.158675965
Short name T780
Test name
Test status
Simulation time 8589758 ps
CPU time 1.53 seconds
Started Jul 14 05:59:46 PM PDT 24
Finished Jul 14 05:59:49 PM PDT 24
Peak memory 237564 kb
Host smart-581ec93b-81b4-4e52-a2af-0b4e4190763d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=158675965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.158675965
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.4104274965
Short name T802
Test name
Test status
Simulation time 18744376 ps
CPU time 1.45 seconds
Started Jul 14 05:59:56 PM PDT 24
Finished Jul 14 05:59:58 PM PDT 24
Peak memory 237544 kb
Host smart-ed35a374-a182-441b-86ba-b590e2cf4a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4104274965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.4104274965
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.505800960
Short name T736
Test name
Test status
Simulation time 13257307 ps
CPU time 1.3 seconds
Started Jul 14 05:59:45 PM PDT 24
Finished Jul 14 05:59:47 PM PDT 24
Peak memory 237564 kb
Host smart-c10b94f4-ce86-4541-94fc-7aefcf5bee48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=505800960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.505800960
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3640511912
Short name T799
Test name
Test status
Simulation time 13508783 ps
CPU time 1.36 seconds
Started Jul 14 05:59:48 PM PDT 24
Finished Jul 14 05:59:50 PM PDT 24
Peak memory 237476 kb
Host smart-8efba86d-30b9-4457-a51c-08f51c4ef9f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3640511912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3640511912
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1897599625
Short name T784
Test name
Test status
Simulation time 35483736 ps
CPU time 1.36 seconds
Started Jul 14 05:59:46 PM PDT 24
Finished Jul 14 05:59:48 PM PDT 24
Peak memory 237352 kb
Host smart-f3df0c17-9c33-4b51-a0b7-41468d818939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1897599625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1897599625
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2127561652
Short name T152
Test name
Test status
Simulation time 9920639 ps
CPU time 1.41 seconds
Started Jul 14 05:59:47 PM PDT 24
Finished Jul 14 05:59:49 PM PDT 24
Peak memory 236640 kb
Host smart-3c87edb0-2173-4f6e-a114-58399c4771df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2127561652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2127561652
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1663718578
Short name T794
Test name
Test status
Simulation time 10508446 ps
CPU time 1.58 seconds
Started Jul 14 05:59:43 PM PDT 24
Finished Jul 14 05:59:45 PM PDT 24
Peak memory 237568 kb
Host smart-420a3f70-644f-47be-97e9-8d85c051e145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1663718578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1663718578
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2083650843
Short name T153
Test name
Test status
Simulation time 8056436 ps
CPU time 1.56 seconds
Started Jul 14 05:59:47 PM PDT 24
Finished Jul 14 05:59:50 PM PDT 24
Peak memory 236784 kb
Host smart-e003d5e8-7c90-4815-b216-cc43ef6aa968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2083650843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2083650843
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.327513061
Short name T771
Test name
Test status
Simulation time 13956706904 ps
CPU time 257.12 seconds
Started Jul 14 05:59:19 PM PDT 24
Finished Jul 14 06:03:37 PM PDT 24
Peak memory 240472 kb
Host smart-9d68be7d-ebbf-40fa-9b50-0560ed76b399
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=327513061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.327513061
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.857712338
Short name T748
Test name
Test status
Simulation time 43600584334 ps
CPU time 479.93 seconds
Started Jul 14 05:59:13 PM PDT 24
Finished Jul 14 06:07:13 PM PDT 24
Peak memory 236668 kb
Host smart-33fa13f7-c240-49b1-8f49-b8169a754718
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=857712338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.857712338
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.100098130
Short name T751
Test name
Test status
Simulation time 142893267 ps
CPU time 6.44 seconds
Started Jul 14 05:59:15 PM PDT 24
Finished Jul 14 05:59:22 PM PDT 24
Peak memory 249060 kb
Host smart-ef44ed2f-2b77-41e1-bfa9-2e62d1c3132b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=100098130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.100098130
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.4154035159
Short name T171
Test name
Test status
Simulation time 92716730 ps
CPU time 8.46 seconds
Started Jul 14 05:59:23 PM PDT 24
Finished Jul 14 05:59:32 PM PDT 24
Peak memory 240508 kb
Host smart-deb79e02-4a9b-4989-8a37-7aaeeb3e37cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154035159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.4154035159
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1580971284
Short name T781
Test name
Test status
Simulation time 33271817 ps
CPU time 4.94 seconds
Started Jul 14 05:59:13 PM PDT 24
Finished Jul 14 05:59:19 PM PDT 24
Peak memory 240500 kb
Host smart-9d6eee1e-8135-405e-839f-70eb0628221b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1580971284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1580971284
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.591282621
Short name T825
Test name
Test status
Simulation time 13173243 ps
CPU time 1.84 seconds
Started Jul 14 05:59:13 PM PDT 24
Finished Jul 14 05:59:16 PM PDT 24
Peak memory 237552 kb
Host smart-5fdb6b3e-181d-4d2e-84ac-eb84b7377d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=591282621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.591282621
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2757213757
Short name T176
Test name
Test status
Simulation time 165157314 ps
CPU time 10.96 seconds
Started Jul 14 05:59:18 PM PDT 24
Finished Jul 14 05:59:30 PM PDT 24
Peak memory 244796 kb
Host smart-fb317eb2-9e31-4088-8006-11cc23e42f9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2757213757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2757213757
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3421414395
Short name T132
Test name
Test status
Simulation time 2147750831 ps
CPU time 137.66 seconds
Started Jul 14 05:59:11 PM PDT 24
Finished Jul 14 06:01:29 PM PDT 24
Peak memory 257064 kb
Host smart-4cedc1ed-b4e6-45d7-95ca-5a38f3369bc3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3421414395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3421414395
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1266513735
Short name T121
Test name
Test status
Simulation time 6193107684 ps
CPU time 479.51 seconds
Started Jul 14 05:59:15 PM PDT 24
Finished Jul 14 06:07:15 PM PDT 24
Peak memory 265528 kb
Host smart-9a2a2db3-8c53-4ff7-86a6-e23ae3da20a7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266513735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1266513735
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2914534601
Short name T765
Test name
Test status
Simulation time 247193895 ps
CPU time 8.31 seconds
Started Jul 14 05:59:11 PM PDT 24
Finished Jul 14 05:59:20 PM PDT 24
Peak memory 253800 kb
Host smart-17873b7d-6151-45b5-baf6-d0fe8b7269f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2914534601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2914534601
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.205399682
Short name T774
Test name
Test status
Simulation time 22067462 ps
CPU time 1.29 seconds
Started Jul 14 05:59:56 PM PDT 24
Finished Jul 14 05:59:57 PM PDT 24
Peak memory 236600 kb
Host smart-469dab77-f553-41cd-94c1-9458c91bc530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=205399682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.205399682
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1334504387
Short name T786
Test name
Test status
Simulation time 11435208 ps
CPU time 1.4 seconds
Started Jul 14 05:59:44 PM PDT 24
Finished Jul 14 05:59:45 PM PDT 24
Peak memory 237576 kb
Host smart-7bc0f528-259f-4ff0-970a-7e8d0d094a55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1334504387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1334504387
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3696857666
Short name T738
Test name
Test status
Simulation time 6407513 ps
CPU time 1.46 seconds
Started Jul 14 05:59:48 PM PDT 24
Finished Jul 14 05:59:50 PM PDT 24
Peak memory 236784 kb
Host smart-5640689c-8571-4fc2-a863-081a132edce2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3696857666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3696857666
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4191728178
Short name T718
Test name
Test status
Simulation time 9433079 ps
CPU time 1.44 seconds
Started Jul 14 05:59:47 PM PDT 24
Finished Jul 14 05:59:50 PM PDT 24
Peak memory 237728 kb
Host smart-ac67c4bf-352f-443e-821c-c8e2502e9860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4191728178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.4191728178
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2123571552
Short name T826
Test name
Test status
Simulation time 7847171 ps
CPU time 1.54 seconds
Started Jul 14 05:59:47 PM PDT 24
Finished Jul 14 05:59:49 PM PDT 24
Peak memory 237488 kb
Host smart-655a50a9-1e4b-462e-9ef6-bf3856eff264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2123571552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2123571552
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2353120815
Short name T803
Test name
Test status
Simulation time 14541841 ps
CPU time 1.33 seconds
Started Jul 14 05:59:47 PM PDT 24
Finished Jul 14 05:59:49 PM PDT 24
Peak memory 237540 kb
Host smart-8c7e4faf-06fd-4f57-854c-3517b832991d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2353120815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2353120815
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2938243984
Short name T240
Test name
Test status
Simulation time 10280738 ps
CPU time 1.76 seconds
Started Jul 14 05:59:49 PM PDT 24
Finished Jul 14 05:59:52 PM PDT 24
Peak memory 237568 kb
Host smart-0c3f256c-025c-46ea-b699-7774cfe113ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2938243984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2938243984
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2701664826
Short name T766
Test name
Test status
Simulation time 11970348 ps
CPU time 1.41 seconds
Started Jul 14 05:59:46 PM PDT 24
Finished Jul 14 05:59:49 PM PDT 24
Peak memory 237564 kb
Host smart-e86c220b-e5af-409f-b1fd-1b85c47c67d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2701664826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2701664826
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3971081932
Short name T737
Test name
Test status
Simulation time 9763117 ps
CPU time 1.59 seconds
Started Jul 14 05:59:45 PM PDT 24
Finished Jul 14 05:59:47 PM PDT 24
Peak memory 237592 kb
Host smart-87a1f38f-6b91-4542-ae62-52061607cabb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3971081932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3971081932
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3629287537
Short name T747
Test name
Test status
Simulation time 6985525 ps
CPU time 1.46 seconds
Started Jul 14 05:59:46 PM PDT 24
Finished Jul 14 05:59:48 PM PDT 24
Peak memory 235580 kb
Host smart-bcebc8e9-7289-4ea8-b607-a629e4fb4ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3629287537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3629287537
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3012058973
Short name T756
Test name
Test status
Simulation time 3248993374 ps
CPU time 270.66 seconds
Started Jul 14 05:59:20 PM PDT 24
Finished Jul 14 06:03:51 PM PDT 24
Peak memory 240664 kb
Host smart-58ba1f33-f9d0-4df6-b86f-2b536b07e623
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3012058973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3012058973
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2186558486
Short name T817
Test name
Test status
Simulation time 11877225051 ps
CPU time 426.98 seconds
Started Jul 14 05:59:20 PM PDT 24
Finished Jul 14 06:06:27 PM PDT 24
Peak memory 240476 kb
Host smart-ccac5f4e-8f8e-4678-8833-fd2bb4d5f361
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2186558486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2186558486
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.339286885
Short name T820
Test name
Test status
Simulation time 141066127 ps
CPU time 6.7 seconds
Started Jul 14 05:59:24 PM PDT 24
Finished Jul 14 05:59:31 PM PDT 24
Peak memory 248660 kb
Host smart-a5da49f5-85d2-485f-b2ae-7e6fceee9c23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=339286885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.339286885
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2447586827
Short name T749
Test name
Test status
Simulation time 129703083 ps
CPU time 10.94 seconds
Started Jul 14 05:59:18 PM PDT 24
Finished Jul 14 05:59:30 PM PDT 24
Peak memory 256880 kb
Host smart-6d9afaa7-dc14-40f7-b5c1-709735ded0c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447586827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2447586827
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2372284994
Short name T809
Test name
Test status
Simulation time 489475943 ps
CPU time 9.99 seconds
Started Jul 14 05:59:22 PM PDT 24
Finished Jul 14 05:59:33 PM PDT 24
Peak memory 240500 kb
Host smart-4834185d-c49e-41fe-8b67-566797df6dd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2372284994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2372284994
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2859535776
Short name T746
Test name
Test status
Simulation time 24675144 ps
CPU time 1.41 seconds
Started Jul 14 05:59:19 PM PDT 24
Finished Jul 14 05:59:21 PM PDT 24
Peak memory 236604 kb
Host smart-e00e8efe-1e32-4a97-8d7e-d3a81380578c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2859535776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2859535776
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3229265208
Short name T178
Test name
Test status
Simulation time 346703458 ps
CPU time 12.84 seconds
Started Jul 14 05:59:22 PM PDT 24
Finished Jul 14 05:59:36 PM PDT 24
Peak memory 245768 kb
Host smart-c8fc76a8-553a-4c46-aeec-09f95b4c9aff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3229265208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3229265208
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3610227763
Short name T127
Test name
Test status
Simulation time 5302267781 ps
CPU time 336.98 seconds
Started Jul 14 05:59:23 PM PDT 24
Finished Jul 14 06:05:01 PM PDT 24
Peak memory 264460 kb
Host smart-baa8e87b-c8b1-4165-9e24-0156cd71023f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3610227763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3610227763
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.942943127
Short name T140
Test name
Test status
Simulation time 24644792861 ps
CPU time 601.61 seconds
Started Jul 14 05:59:20 PM PDT 24
Finished Jul 14 06:09:22 PM PDT 24
Peak memory 266900 kb
Host smart-8a80cf2e-4f02-4f0b-8c6b-c4005ce5dfb4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942943127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.942943127
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2958049450
Short name T729
Test name
Test status
Simulation time 284996384 ps
CPU time 21.13 seconds
Started Jul 14 05:59:19 PM PDT 24
Finished Jul 14 05:59:41 PM PDT 24
Peak memory 248772 kb
Host smart-598d2653-1fb2-40e2-9828-19ca27dd11a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2958049450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2958049450
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.4090508566
Short name T740
Test name
Test status
Simulation time 16268650 ps
CPU time 1.38 seconds
Started Jul 14 05:59:55 PM PDT 24
Finished Jul 14 05:59:57 PM PDT 24
Peak memory 237544 kb
Host smart-c63535b1-c2d7-4f61-9c3c-79258fcab63f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4090508566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.4090508566
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2865636364
Short name T783
Test name
Test status
Simulation time 12436877 ps
CPU time 1.38 seconds
Started Jul 14 05:59:47 PM PDT 24
Finished Jul 14 05:59:50 PM PDT 24
Peak memory 237520 kb
Host smart-00d83d17-65f7-40ed-82cb-157a9de09c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2865636364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2865636364
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3429545120
Short name T773
Test name
Test status
Simulation time 8540261 ps
CPU time 1.58 seconds
Started Jul 14 05:59:47 PM PDT 24
Finished Jul 14 05:59:50 PM PDT 24
Peak memory 237468 kb
Host smart-359b4047-5666-4284-954c-5fb578f9f536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3429545120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3429545120
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3125088676
Short name T829
Test name
Test status
Simulation time 10669688 ps
CPU time 1.63 seconds
Started Jul 14 05:59:47 PM PDT 24
Finished Jul 14 05:59:50 PM PDT 24
Peak memory 236624 kb
Host smart-f3b501c6-a2e8-414a-ac37-8c12884d30f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3125088676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3125088676
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1729724510
Short name T334
Test name
Test status
Simulation time 20145779 ps
CPU time 1.3 seconds
Started Jul 14 05:59:45 PM PDT 24
Finished Jul 14 05:59:47 PM PDT 24
Peak memory 235524 kb
Host smart-8a404923-1466-4ed3-af5a-0a451b29cc56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1729724510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1729724510
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3605861445
Short name T721
Test name
Test status
Simulation time 10860552 ps
CPU time 1.66 seconds
Started Jul 14 05:59:54 PM PDT 24
Finished Jul 14 05:59:56 PM PDT 24
Peak memory 236496 kb
Host smart-b1e11722-13de-465b-95d0-eaadcb329e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3605861445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3605861445
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3847304236
Short name T227
Test name
Test status
Simulation time 12122981 ps
CPU time 1.49 seconds
Started Jul 14 05:59:49 PM PDT 24
Finished Jul 14 05:59:51 PM PDT 24
Peak memory 236508 kb
Host smart-482bc8ac-74b4-40e7-991c-1d33dc2ae99e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3847304236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3847304236
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3818805049
Short name T804
Test name
Test status
Simulation time 13176601 ps
CPU time 1.44 seconds
Started Jul 14 05:59:55 PM PDT 24
Finished Jul 14 05:59:56 PM PDT 24
Peak memory 237584 kb
Host smart-7e4547bf-847c-4c3f-9d0b-80fdffed09a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3818805049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3818805049
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1461821844
Short name T812
Test name
Test status
Simulation time 225641588 ps
CPU time 5.19 seconds
Started Jul 14 05:59:18 PM PDT 24
Finished Jul 14 05:59:24 PM PDT 24
Peak memory 240324 kb
Host smart-e5247a5b-23b2-40e8-98a0-67c2ece8d161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461821844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1461821844
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2508411851
Short name T342
Test name
Test status
Simulation time 231093162 ps
CPU time 5.49 seconds
Started Jul 14 05:59:19 PM PDT 24
Finished Jul 14 05:59:25 PM PDT 24
Peak memory 240492 kb
Host smart-1fdd7b35-fe61-4590-9690-f9d92ed56bbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2508411851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2508411851
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.251662045
Short name T333
Test name
Test status
Simulation time 8859760 ps
CPU time 1.44 seconds
Started Jul 14 05:59:22 PM PDT 24
Finished Jul 14 05:59:23 PM PDT 24
Peak memory 236636 kb
Host smart-cca0272f-7c5e-4adc-9d3a-933cac3eb564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=251662045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.251662045
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3628022730
Short name T764
Test name
Test status
Simulation time 3055438612 ps
CPU time 40.81 seconds
Started Jul 14 05:59:18 PM PDT 24
Finished Jul 14 05:59:59 PM PDT 24
Peak memory 245840 kb
Host smart-ecd24db6-90f9-46a0-a822-a5d5dc0f74b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3628022730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3628022730
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2408201973
Short name T139
Test name
Test status
Simulation time 67409897659 ps
CPU time 325.29 seconds
Started Jul 14 05:59:18 PM PDT 24
Finished Jul 14 06:04:44 PM PDT 24
Peak memory 265436 kb
Host smart-d56fbf81-52a5-4a70-b5bb-743f51a15c95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2408201973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2408201973
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1263775861
Short name T340
Test name
Test status
Simulation time 2293238771 ps
CPU time 363.6 seconds
Started Jul 14 05:59:18 PM PDT 24
Finished Jul 14 06:05:23 PM PDT 24
Peak memory 270228 kb
Host smart-ec4da853-28c1-4d91-ae97-a3b0df802906
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263775861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1263775861
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1522964033
Short name T798
Test name
Test status
Simulation time 94169406 ps
CPU time 12.26 seconds
Started Jul 14 05:59:20 PM PDT 24
Finished Jul 14 05:59:33 PM PDT 24
Peak memory 255376 kb
Host smart-1f6d6d19-32f9-4b8c-9e23-6649a1f70436
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1522964033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1522964033
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.851838342
Short name T730
Test name
Test status
Simulation time 31834169 ps
CPU time 4.71 seconds
Started Jul 14 05:59:28 PM PDT 24
Finished Jul 14 05:59:34 PM PDT 24
Peak memory 240652 kb
Host smart-3e2c917e-44e3-4cee-955e-bbceaf6146f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851838342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.alert_handler_csr_mem_rw_with_rand_reset.851838342
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3363574434
Short name T753
Test name
Test status
Simulation time 21641518 ps
CPU time 3.74 seconds
Started Jul 14 05:59:26 PM PDT 24
Finished Jul 14 05:59:30 PM PDT 24
Peak memory 240456 kb
Host smart-e2b473b1-22a3-48f8-9e71-51ef10b4f740
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3363574434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3363574434
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3043535176
Short name T760
Test name
Test status
Simulation time 8582558 ps
CPU time 1.48 seconds
Started Jul 14 05:59:35 PM PDT 24
Finished Jul 14 05:59:37 PM PDT 24
Peak memory 237568 kb
Host smart-13c34a53-cea7-4094-8f8b-f576a9a3e18c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3043535176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3043535176
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2480683141
Short name T724
Test name
Test status
Simulation time 2746797465 ps
CPU time 18.79 seconds
Started Jul 14 05:59:24 PM PDT 24
Finished Jul 14 05:59:43 PM PDT 24
Peak memory 248772 kb
Host smart-4d222cc0-9530-4ad8-8d5f-6be6c8dbf853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2480683141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2480683141
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1095533561
Short name T233
Test name
Test status
Simulation time 1432358591 ps
CPU time 29.66 seconds
Started Jul 14 05:59:20 PM PDT 24
Finished Jul 14 05:59:50 PM PDT 24
Peak memory 248660 kb
Host smart-b56edaa7-3846-426d-81a2-3ae13e6557d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1095533561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1095533561
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3557068272
Short name T744
Test name
Test status
Simulation time 59862305 ps
CPU time 9.99 seconds
Started Jul 14 05:59:26 PM PDT 24
Finished Jul 14 05:59:37 PM PDT 24
Peak memory 252928 kb
Host smart-f61cab45-c2ce-4cad-81de-e82d30cb01a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557068272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3557068272
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3443517982
Short name T811
Test name
Test status
Simulation time 22921073 ps
CPU time 3.97 seconds
Started Jul 14 05:59:27 PM PDT 24
Finished Jul 14 05:59:32 PM PDT 24
Peak memory 240404 kb
Host smart-a8211b1d-2b3a-412c-bee3-a4064d15154a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3443517982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3443517982
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2480169507
Short name T720
Test name
Test status
Simulation time 7411468 ps
CPU time 1.41 seconds
Started Jul 14 05:59:24 PM PDT 24
Finished Jul 14 05:59:26 PM PDT 24
Peak memory 235596 kb
Host smart-84b49d35-faa2-437d-afad-d96885fff913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2480169507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2480169507
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3243353661
Short name T776
Test name
Test status
Simulation time 2060680755 ps
CPU time 40.85 seconds
Started Jul 14 05:59:24 PM PDT 24
Finished Jul 14 06:00:06 PM PDT 24
Peak memory 248696 kb
Host smart-44ba4535-8c1b-42a5-8a21-7e99c122ef98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3243353661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3243353661
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1168099691
Short name T111
Test name
Test status
Simulation time 3430849980 ps
CPU time 143.63 seconds
Started Jul 14 05:59:25 PM PDT 24
Finished Jul 14 06:01:49 PM PDT 24
Peak memory 266692 kb
Host smart-12cbe7c8-fcfe-430e-9048-74c43864e2f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1168099691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1168099691
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4043869398
Short name T722
Test name
Test status
Simulation time 2361922721 ps
CPU time 14.37 seconds
Started Jul 14 05:59:28 PM PDT 24
Finished Jul 14 05:59:43 PM PDT 24
Peak memory 253204 kb
Host smart-2453816f-d8ff-4c5e-9088-1671d14a8c5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4043869398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.4043869398
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3522862304
Short name T819
Test name
Test status
Simulation time 600550908 ps
CPU time 6.02 seconds
Started Jul 14 05:59:27 PM PDT 24
Finished Jul 14 05:59:34 PM PDT 24
Peak memory 240508 kb
Host smart-a2e6fff0-4ec3-43db-b6a1-c5141c7fac1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522862304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3522862304
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1827899728
Short name T754
Test name
Test status
Simulation time 97203274 ps
CPU time 4.86 seconds
Started Jul 14 05:59:28 PM PDT 24
Finished Jul 14 05:59:33 PM PDT 24
Peak memory 240464 kb
Host smart-3abc9e64-ab79-43a2-878a-a0afe48f1389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1827899728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1827899728
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2421562757
Short name T734
Test name
Test status
Simulation time 25933071 ps
CPU time 1.36 seconds
Started Jul 14 05:59:26 PM PDT 24
Finished Jul 14 05:59:28 PM PDT 24
Peak memory 237436 kb
Host smart-28a4794a-9d6a-4512-8fb1-8ee7591da8df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2421562757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2421562757
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.465268466
Short name T739
Test name
Test status
Simulation time 391584493 ps
CPU time 17.33 seconds
Started Jul 14 05:59:25 PM PDT 24
Finished Jul 14 05:59:43 PM PDT 24
Peak memory 244832 kb
Host smart-77f95df4-7df2-4916-992b-fc78f750547f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=465268466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.465268466
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.4084932414
Short name T113
Test name
Test status
Simulation time 774513376 ps
CPU time 97.15 seconds
Started Jul 14 05:59:26 PM PDT 24
Finished Jul 14 06:01:03 PM PDT 24
Peak memory 265232 kb
Host smart-5d9fc50c-6813-49d7-8757-bc7150bf3d8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4084932414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.4084932414
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.936213888
Short name T143
Test name
Test status
Simulation time 25814789111 ps
CPU time 479.68 seconds
Started Jul 14 05:59:26 PM PDT 24
Finished Jul 14 06:07:26 PM PDT 24
Peak memory 265324 kb
Host smart-6437476a-a26b-4bad-9210-55786215eee6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936213888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.936213888
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3027728222
Short name T800
Test name
Test status
Simulation time 259428304 ps
CPU time 17.07 seconds
Started Jul 14 05:59:25 PM PDT 24
Finished Jul 14 05:59:42 PM PDT 24
Peak memory 248824 kb
Host smart-57c14acd-678b-451f-9165-c8cad93cbd01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3027728222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3027728222
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.323982893
Short name T726
Test name
Test status
Simulation time 276034714 ps
CPU time 12.29 seconds
Started Jul 14 05:59:23 PM PDT 24
Finished Jul 14 05:59:36 PM PDT 24
Peak memory 253480 kb
Host smart-be83541e-7121-4acc-acd3-c2e55834f57c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323982893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.323982893
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.817509315
Short name T237
Test name
Test status
Simulation time 491211765 ps
CPU time 10.95 seconds
Started Jul 14 05:59:23 PM PDT 24
Finished Jul 14 05:59:35 PM PDT 24
Peak memory 240496 kb
Host smart-d9e3a7a5-e2e7-4994-bf6b-b8392f001492
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=817509315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.817509315
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.962811462
Short name T779
Test name
Test status
Simulation time 10259105 ps
CPU time 1.44 seconds
Started Jul 14 05:59:26 PM PDT 24
Finished Jul 14 05:59:28 PM PDT 24
Peak memory 237524 kb
Host smart-9d7f8a10-77ff-451f-a29b-d18b7e3cd6c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=962811462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.962811462
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1281843046
Short name T170
Test name
Test status
Simulation time 720443486 ps
CPU time 23.72 seconds
Started Jul 14 05:59:27 PM PDT 24
Finished Jul 14 05:59:52 PM PDT 24
Peak memory 248700 kb
Host smart-36a97515-c95d-449e-9cde-3a0f68b07092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1281843046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1281843046
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2333951947
Short name T134
Test name
Test status
Simulation time 7396868375 ps
CPU time 428.48 seconds
Started Jul 14 05:59:25 PM PDT 24
Finished Jul 14 06:06:34 PM PDT 24
Peak memory 271556 kb
Host smart-8fe881e6-b15c-4b27-8920-7e08381a0119
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2333951947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2333951947
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1757059463
Short name T741
Test name
Test status
Simulation time 566839833 ps
CPU time 17.46 seconds
Started Jul 14 05:59:35 PM PDT 24
Finished Jul 14 05:59:53 PM PDT 24
Peak memory 251840 kb
Host smart-2f1425f3-afd5-4db5-a8f9-ba27445530e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1757059463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1757059463
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3257949415
Short name T45
Test name
Test status
Simulation time 7644250371 ps
CPU time 791.15 seconds
Started Jul 14 05:06:20 PM PDT 24
Finished Jul 14 05:19:31 PM PDT 24
Peak memory 273284 kb
Host smart-f4abbb72-53fb-484d-90f7-e2409bb88f22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257949415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3257949415
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2287001998
Short name T356
Test name
Test status
Simulation time 117158321 ps
CPU time 7.67 seconds
Started Jul 14 05:06:28 PM PDT 24
Finished Jul 14 05:06:36 PM PDT 24
Peak memory 249164 kb
Host smart-715f8470-3b52-49f8-9c40-4899ea08fd5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2287001998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2287001998
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.4067518198
Short name T88
Test name
Test status
Simulation time 628818842 ps
CPU time 20.76 seconds
Started Jul 14 05:06:24 PM PDT 24
Finished Jul 14 05:06:45 PM PDT 24
Peak memory 256000 kb
Host smart-9c5dbaf8-7825-4038-b8bc-9673b95cc34b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40675
18198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.4067518198
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2044445098
Short name T433
Test name
Test status
Simulation time 742124384 ps
CPU time 30.8 seconds
Started Jul 14 05:06:22 PM PDT 24
Finished Jul 14 05:06:53 PM PDT 24
Peak memory 249196 kb
Host smart-ed9cb413-69f7-4056-af5d-2cabd9b9e508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20444
45098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2044445098
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.478377563
Short name T397
Test name
Test status
Simulation time 121648921747 ps
CPU time 1857.88 seconds
Started Jul 14 05:06:29 PM PDT 24
Finished Jul 14 05:37:28 PM PDT 24
Peak memory 285940 kb
Host smart-02e7ea52-d3e2-405f-b9cf-d901eeeffbaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478377563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.478377563
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3496311120
Short name T518
Test name
Test status
Simulation time 540352924 ps
CPU time 27.59 seconds
Started Jul 14 05:06:21 PM PDT 24
Finished Jul 14 05:06:48 PM PDT 24
Peak memory 256316 kb
Host smart-04630fb6-69bc-4e5c-add9-3b5cbfd2f0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34963
11120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3496311120
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2375164592
Short name T62
Test name
Test status
Simulation time 58288832 ps
CPU time 5.91 seconds
Started Jul 14 05:06:21 PM PDT 24
Finished Jul 14 05:06:27 PM PDT 24
Peak memory 248704 kb
Host smart-1050cf02-16dd-42d0-86c4-c1659f6be983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23751
64592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2375164592
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.304637160
Short name T68
Test name
Test status
Simulation time 599079977 ps
CPU time 38.8 seconds
Started Jul 14 05:06:22 PM PDT 24
Finished Jul 14 05:07:01 PM PDT 24
Peak memory 249120 kb
Host smart-6b5048d6-8c79-47e5-b7e4-c1fde77d30ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30463
7160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.304637160
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1687549912
Short name T353
Test name
Test status
Simulation time 1087975349 ps
CPU time 9.16 seconds
Started Jul 14 05:06:24 PM PDT 24
Finished Jul 14 05:06:34 PM PDT 24
Peak memory 252148 kb
Host smart-d98f84e2-f266-424c-b704-732e49117b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16875
49912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1687549912
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3008082751
Short name T385
Test name
Test status
Simulation time 39292906208 ps
CPU time 1557.18 seconds
Started Jul 14 05:06:29 PM PDT 24
Finished Jul 14 05:32:27 PM PDT 24
Peak memory 273900 kb
Host smart-5f4340d3-aca4-4232-9562-ecadec791fec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008082751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3008082751
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3684952143
Short name T652
Test name
Test status
Simulation time 810032014 ps
CPU time 9.3 seconds
Started Jul 14 05:06:34 PM PDT 24
Finished Jul 14 05:06:44 PM PDT 24
Peak memory 249152 kb
Host smart-c0ced06a-fcf0-4386-8b1e-cb465495e2ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3684952143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3684952143
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2696705151
Short name T592
Test name
Test status
Simulation time 2396361400 ps
CPU time 59.26 seconds
Started Jul 14 05:06:27 PM PDT 24
Finished Jul 14 05:07:27 PM PDT 24
Peak memory 257484 kb
Host smart-d39e912f-9e13-49da-94b0-4865ed807844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26967
05151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2696705151
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.633871038
Short name T542
Test name
Test status
Simulation time 700233519 ps
CPU time 30.62 seconds
Started Jul 14 05:06:35 PM PDT 24
Finished Jul 14 05:07:07 PM PDT 24
Peak memory 249192 kb
Host smart-de801e5a-7ae1-4234-b836-5d6913fa134f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63387
1038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.633871038
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3990843303
Short name T529
Test name
Test status
Simulation time 216964729697 ps
CPU time 3165.26 seconds
Started Jul 14 05:06:27 PM PDT 24
Finished Jul 14 05:59:13 PM PDT 24
Peak memory 290216 kb
Host smart-7eacccb6-ba83-4d37-bce6-efb3d59f0faf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990843303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3990843303
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2447588915
Short name T670
Test name
Test status
Simulation time 29312576235 ps
CPU time 189.04 seconds
Started Jul 14 05:06:28 PM PDT 24
Finished Jul 14 05:09:37 PM PDT 24
Peak memory 249224 kb
Host smart-fb01b1d8-3dcd-4d77-b98b-a1a7f588e13e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447588915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2447588915
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2744615955
Short name T645
Test name
Test status
Simulation time 758158055 ps
CPU time 32.54 seconds
Started Jul 14 05:06:29 PM PDT 24
Finished Jul 14 05:07:02 PM PDT 24
Peak memory 249092 kb
Host smart-b5952da4-dc80-48c4-9930-c53e87b8234a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27446
15955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2744615955
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3871419890
Short name T551
Test name
Test status
Simulation time 160291707 ps
CPU time 13.81 seconds
Started Jul 14 05:06:27 PM PDT 24
Finished Jul 14 05:06:41 PM PDT 24
Peak memory 254796 kb
Host smart-45e18280-68ce-4363-a4a6-80e37039a4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38714
19890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3871419890
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1967569342
Short name T28
Test name
Test status
Simulation time 979730268 ps
CPU time 15.32 seconds
Started Jul 14 05:06:35 PM PDT 24
Finished Jul 14 05:06:51 PM PDT 24
Peak memory 271256 kb
Host smart-855ecd28-e3fe-422b-b3e8-37dc6c3cac1f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1967569342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1967569342
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1483313580
Short name T439
Test name
Test status
Simulation time 4108442912 ps
CPU time 49.32 seconds
Started Jul 14 05:06:28 PM PDT 24
Finished Jul 14 05:07:17 PM PDT 24
Peak memory 248968 kb
Host smart-9eef7009-9f26-4f06-91fb-649451257e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14833
13580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1483313580
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1214441953
Short name T625
Test name
Test status
Simulation time 276072738 ps
CPU time 18.33 seconds
Started Jul 14 05:06:34 PM PDT 24
Finished Jul 14 05:06:53 PM PDT 24
Peak memory 249168 kb
Host smart-357e273c-d037-4c20-a800-94af28b0ce87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12144
41953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1214441953
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3368950984
Short name T184
Test name
Test status
Simulation time 34602687107 ps
CPU time 3035.56 seconds
Started Jul 14 05:06:34 PM PDT 24
Finished Jul 14 05:57:10 PM PDT 24
Peak memory 319788 kb
Host smart-c03e138c-69cc-4be2-aea5-051130c1ff1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368950984 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3368950984
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4141140910
Short name T204
Test name
Test status
Simulation time 48770109 ps
CPU time 4.34 seconds
Started Jul 14 05:08:06 PM PDT 24
Finished Jul 14 05:08:11 PM PDT 24
Peak memory 249468 kb
Host smart-ce8962d5-f9e6-4645-9d64-1a6a02f69956
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4141140910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4141140910
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2532974423
Short name T650
Test name
Test status
Simulation time 7586240132 ps
CPU time 1170.87 seconds
Started Jul 14 05:07:59 PM PDT 24
Finished Jul 14 05:27:30 PM PDT 24
Peak memory 282096 kb
Host smart-c1b2a2b6-946b-4a08-9865-fe9a68f6c114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532974423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2532974423
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2781886055
Short name T396
Test name
Test status
Simulation time 2819907081 ps
CPU time 33.55 seconds
Started Jul 14 05:08:00 PM PDT 24
Finished Jul 14 05:08:34 PM PDT 24
Peak memory 249148 kb
Host smart-f2d1ac97-efa0-4b0b-97c5-006581e3a975
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2781886055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2781886055
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.384537819
Short name T362
Test name
Test status
Simulation time 5908522961 ps
CPU time 94.14 seconds
Started Jul 14 05:07:54 PM PDT 24
Finished Jul 14 05:09:28 PM PDT 24
Peak memory 257556 kb
Host smart-d9284aae-9520-45c3-8d61-9a07df9e18b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38453
7819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.384537819
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.4119115043
Short name T451
Test name
Test status
Simulation time 1650200268 ps
CPU time 50.17 seconds
Started Jul 14 05:07:52 PM PDT 24
Finished Jul 14 05:08:43 PM PDT 24
Peak memory 256104 kb
Host smart-b39cffee-1d0b-4b06-b448-c1582cf52c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41191
15043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.4119115043
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1214660502
Short name T298
Test name
Test status
Simulation time 74244450294 ps
CPU time 1989.71 seconds
Started Jul 14 05:08:00 PM PDT 24
Finished Jul 14 05:41:10 PM PDT 24
Peak memory 273800 kb
Host smart-264758e6-f77d-483a-9c53-8b02410cedfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214660502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1214660502
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2139904607
Short name T89
Test name
Test status
Simulation time 9529489726 ps
CPU time 692.68 seconds
Started Jul 14 05:07:59 PM PDT 24
Finished Jul 14 05:19:32 PM PDT 24
Peak memory 273252 kb
Host smart-69408b2b-240e-4b8e-8372-dc3ab19e0232
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139904607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2139904607
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.789202531
Short name T612
Test name
Test status
Simulation time 20483089169 ps
CPU time 280.18 seconds
Started Jul 14 05:07:59 PM PDT 24
Finished Jul 14 05:12:40 PM PDT 24
Peak memory 249272 kb
Host smart-d01a7ea7-2a49-46b1-b0bb-4976d88b0510
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789202531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.789202531
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3539461092
Short name T478
Test name
Test status
Simulation time 300438162 ps
CPU time 10.48 seconds
Started Jul 14 05:07:52 PM PDT 24
Finished Jul 14 05:08:03 PM PDT 24
Peak memory 257244 kb
Host smart-92c54b0e-3c77-40e1-87fe-63e1b8d3b2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35394
61092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3539461092
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4206788762
Short name T610
Test name
Test status
Simulation time 756463597 ps
CPU time 12.81 seconds
Started Jul 14 05:07:53 PM PDT 24
Finished Jul 14 05:08:06 PM PDT 24
Peak memory 255012 kb
Host smart-38377a2d-3376-4104-b09a-d5bc09055ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42067
88762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4206788762
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1332954650
Short name T627
Test name
Test status
Simulation time 604843084 ps
CPU time 35.17 seconds
Started Jul 14 05:07:54 PM PDT 24
Finished Jul 14 05:08:30 PM PDT 24
Peak memory 257388 kb
Host smart-4965f7e9-0218-4f76-a443-e86bf36a7504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13329
54650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1332954650
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1218028457
Short name T44
Test name
Test status
Simulation time 46574827332 ps
CPU time 3403.65 seconds
Started Jul 14 05:08:06 PM PDT 24
Finished Jul 14 06:04:50 PM PDT 24
Peak memory 302756 kb
Host smart-685bc52b-ebb0-4777-92b6-42a5c725c3a9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218028457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1218028457
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3676561960
Short name T207
Test name
Test status
Simulation time 60524131 ps
CPU time 4.43 seconds
Started Jul 14 05:08:10 PM PDT 24
Finished Jul 14 05:08:15 PM PDT 24
Peak memory 249420 kb
Host smart-90869c2b-d4ff-4252-affe-bf4990974557
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3676561960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3676561960
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.954880410
Short name T417
Test name
Test status
Simulation time 41412214755 ps
CPU time 2561.37 seconds
Started Jul 14 05:08:06 PM PDT 24
Finished Jul 14 05:50:48 PM PDT 24
Peak memory 289760 kb
Host smart-3ecac242-f224-4874-8709-1e2b7d0bccce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954880410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.954880410
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.440855058
Short name T450
Test name
Test status
Simulation time 1360594934 ps
CPU time 102.25 seconds
Started Jul 14 05:08:07 PM PDT 24
Finished Jul 14 05:09:50 PM PDT 24
Peak memory 256812 kb
Host smart-18111eeb-6f1f-4e70-9f6f-8e7b02154f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44085
5058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.440855058
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2694517235
Short name T391
Test name
Test status
Simulation time 597203265 ps
CPU time 10 seconds
Started Jul 14 05:08:05 PM PDT 24
Finished Jul 14 05:08:16 PM PDT 24
Peak memory 248720 kb
Host smart-dd08b4d6-4004-427d-8c9b-b9aa17aba582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26945
17235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2694517235
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.294515845
Short name T549
Test name
Test status
Simulation time 137932467539 ps
CPU time 2328.77 seconds
Started Jul 14 05:08:11 PM PDT 24
Finished Jul 14 05:47:01 PM PDT 24
Peak memory 289992 kb
Host smart-130c53a8-2c60-40be-9a51-cb8147191c9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294515845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.294515845
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.4207717169
Short name T554
Test name
Test status
Simulation time 205851656 ps
CPU time 4.66 seconds
Started Jul 14 05:08:04 PM PDT 24
Finished Jul 14 05:08:09 PM PDT 24
Peak memory 249152 kb
Host smart-27f5745a-bfdb-483e-9dd2-8bfdee7c0554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42077
17169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4207717169
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1319421878
Short name T449
Test name
Test status
Simulation time 1426555307 ps
CPU time 24.01 seconds
Started Jul 14 05:08:04 PM PDT 24
Finished Jul 14 05:08:29 PM PDT 24
Peak memory 248560 kb
Host smart-f05feb8e-30bc-4df7-9f2f-cc68c7c3f6b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13194
21878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1319421878
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3413841405
Short name T32
Test name
Test status
Simulation time 91105659 ps
CPU time 9.82 seconds
Started Jul 14 05:08:05 PM PDT 24
Finished Jul 14 05:08:15 PM PDT 24
Peak memory 254232 kb
Host smart-cc43ed50-faa1-45bc-98ec-81027b6b63cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34138
41405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3413841405
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2464971300
Short name T680
Test name
Test status
Simulation time 28520626350 ps
CPU time 1131.8 seconds
Started Jul 14 05:08:11 PM PDT 24
Finished Jul 14 05:27:04 PM PDT 24
Peak memory 288228 kb
Host smart-c118cca6-f066-4360-825d-8dbd221b45d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464971300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2464971300
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1574694010
Short name T681
Test name
Test status
Simulation time 12352650126 ps
CPU time 1079.73 seconds
Started Jul 14 05:08:18 PM PDT 24
Finished Jul 14 05:26:18 PM PDT 24
Peak memory 283468 kb
Host smart-c6a25732-49f5-4cf0-9395-31f553773a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574694010 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1574694010
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3098031066
Short name T194
Test name
Test status
Simulation time 40582301 ps
CPU time 3.51 seconds
Started Jul 14 05:08:25 PM PDT 24
Finished Jul 14 05:08:29 PM PDT 24
Peak memory 249472 kb
Host smart-cf7aa4e3-9eb1-4220-b1c9-6df975287b85
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3098031066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3098031066
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3942892999
Short name T367
Test name
Test status
Simulation time 9009961827 ps
CPU time 1001.56 seconds
Started Jul 14 05:08:25 PM PDT 24
Finished Jul 14 05:25:07 PM PDT 24
Peak memory 272164 kb
Host smart-78ddc313-c24e-4622-bc5c-93c89ce592b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942892999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3942892999
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1354250282
Short name T186
Test name
Test status
Simulation time 4270487474 ps
CPU time 51.22 seconds
Started Jul 14 05:08:27 PM PDT 24
Finished Jul 14 05:09:19 PM PDT 24
Peak memory 249300 kb
Host smart-d48ca84a-ef01-4189-b8b7-dea34c177a57
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1354250282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1354250282
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2321307421
Short name T685
Test name
Test status
Simulation time 94903642 ps
CPU time 7.63 seconds
Started Jul 14 05:08:26 PM PDT 24
Finished Jul 14 05:08:34 PM PDT 24
Peak memory 252180 kb
Host smart-0fee2724-36dc-4c42-ab57-740a5315c13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23213
07421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2321307421
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.343552182
Short name T67
Test name
Test status
Simulation time 1526504309 ps
CPU time 50.04 seconds
Started Jul 14 05:08:17 PM PDT 24
Finished Jul 14 05:09:08 PM PDT 24
Peak memory 248872 kb
Host smart-f1fda27a-7df8-4385-8fff-2f0d2b734923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34355
2182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.343552182
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.451348394
Short name T327
Test name
Test status
Simulation time 10596702019 ps
CPU time 978.06 seconds
Started Jul 14 05:08:24 PM PDT 24
Finished Jul 14 05:24:43 PM PDT 24
Peak memory 273816 kb
Host smart-3642cee6-43bb-4f6f-a037-64d1988ae2b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451348394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.451348394
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.134142729
Short name T488
Test name
Test status
Simulation time 139207247486 ps
CPU time 2070.89 seconds
Started Jul 14 05:08:26 PM PDT 24
Finished Jul 14 05:42:57 PM PDT 24
Peak memory 289268 kb
Host smart-d61ba0cb-16a5-458b-8c7a-9780312c134d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134142729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.134142729
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2727853935
Short name T605
Test name
Test status
Simulation time 765852116 ps
CPU time 25.4 seconds
Started Jul 14 05:08:18 PM PDT 24
Finished Jul 14 05:08:44 PM PDT 24
Peak memory 249256 kb
Host smart-a13c9576-bf75-4e0f-83db-4b7a4aaa03f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27278
53935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2727853935
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.368234559
Short name T371
Test name
Test status
Simulation time 347506388 ps
CPU time 24.82 seconds
Started Jul 14 05:08:16 PM PDT 24
Finished Jul 14 05:08:41 PM PDT 24
Peak memory 256548 kb
Host smart-3c045acd-497e-4f15-902a-5797ed62b049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36823
4559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.368234559
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.293426106
Short name T527
Test name
Test status
Simulation time 632953032 ps
CPU time 39.65 seconds
Started Jul 14 05:08:24 PM PDT 24
Finished Jul 14 05:09:04 PM PDT 24
Peak memory 257084 kb
Host smart-9379865f-a941-4822-af7e-1e663cf12b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29342
6106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.293426106
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2004900664
Short name T508
Test name
Test status
Simulation time 296807040 ps
CPU time 27.31 seconds
Started Jul 14 05:08:17 PM PDT 24
Finished Jul 14 05:08:45 PM PDT 24
Peak memory 257392 kb
Host smart-ebd5dfef-32b2-4623-83d2-321988b9b9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20049
00664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2004900664
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.483737072
Short name T714
Test name
Test status
Simulation time 87823018358 ps
CPU time 1939.75 seconds
Started Jul 14 05:08:26 PM PDT 24
Finished Jul 14 05:40:47 PM PDT 24
Peak memory 298500 kb
Host smart-81207add-fbc8-4591-87b7-4b46cf8ac8a9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483737072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.483737072
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1635868332
Short name T280
Test name
Test status
Simulation time 73594258685 ps
CPU time 1063.58 seconds
Started Jul 14 05:08:31 PM PDT 24
Finished Jul 14 05:26:15 PM PDT 24
Peak memory 265604 kb
Host smart-e5c22ba6-c4fc-46e9-9108-38469bc79128
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635868332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1635868332
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2972688558
Short name T215
Test name
Test status
Simulation time 485050253 ps
CPU time 8.08 seconds
Started Jul 14 05:08:37 PM PDT 24
Finished Jul 14 05:08:46 PM PDT 24
Peak memory 249072 kb
Host smart-d28515e1-6811-43a1-bdd6-647559636029
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2972688558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2972688558
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1572946525
Short name T373
Test name
Test status
Simulation time 1081783706 ps
CPU time 97.36 seconds
Started Jul 14 05:08:32 PM PDT 24
Finished Jul 14 05:10:09 PM PDT 24
Peak memory 257412 kb
Host smart-785f98cc-30b4-4604-b027-9f84be0f7db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15729
46525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1572946525
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2567688538
Short name T370
Test name
Test status
Simulation time 692998668 ps
CPU time 12.11 seconds
Started Jul 14 05:08:33 PM PDT 24
Finished Jul 14 05:08:46 PM PDT 24
Peak memory 253844 kb
Host smart-7a7af4db-3d9c-4e10-9e26-adf250443c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25676
88538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2567688538
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.88813032
Short name T388
Test name
Test status
Simulation time 98336589799 ps
CPU time 1532.45 seconds
Started Jul 14 05:08:38 PM PDT 24
Finished Jul 14 05:34:11 PM PDT 24
Peak memory 269760 kb
Host smart-0681a0d9-da14-43d3-8e5f-4a550b37c0f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88813032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.88813032
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3286100032
Short name T595
Test name
Test status
Simulation time 218059449332 ps
CPU time 512.75 seconds
Started Jul 14 05:08:33 PM PDT 24
Finished Jul 14 05:17:06 PM PDT 24
Peak memory 249268 kb
Host smart-c3361d50-aed7-4114-a643-ce299bbf50b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286100032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3286100032
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1347279149
Short name T392
Test name
Test status
Simulation time 2414341484 ps
CPU time 50.61 seconds
Started Jul 14 05:08:31 PM PDT 24
Finished Jul 14 05:09:22 PM PDT 24
Peak memory 256624 kb
Host smart-216619fe-cf36-4d01-8f63-a0af8e8f878a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13472
79149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1347279149
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.4019272779
Short name T528
Test name
Test status
Simulation time 290559291 ps
CPU time 16.31 seconds
Started Jul 14 05:08:29 PM PDT 24
Finished Jul 14 05:08:46 PM PDT 24
Peak memory 256412 kb
Host smart-76ab97a5-4eca-4a6c-a101-73ce79a73d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40192
72779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4019272779
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.430971348
Short name T697
Test name
Test status
Simulation time 576106816 ps
CPU time 28.79 seconds
Started Jul 14 05:08:31 PM PDT 24
Finished Jul 14 05:09:01 PM PDT 24
Peak memory 249200 kb
Host smart-a631ba61-d546-440d-8b5d-1b52350e7f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43097
1348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.430971348
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3931302130
Short name T524
Test name
Test status
Simulation time 41155374454 ps
CPU time 2889.6 seconds
Started Jul 14 05:08:44 PM PDT 24
Finished Jul 14 05:56:54 PM PDT 24
Peak memory 289960 kb
Host smart-06c31e1a-12c9-4b6c-b9c7-09098ec030a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931302130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3931302130
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2069685684
Short name T514
Test name
Test status
Simulation time 37670442283 ps
CPU time 3286.91 seconds
Started Jul 14 05:08:44 PM PDT 24
Finished Jul 14 06:03:32 PM PDT 24
Peak memory 304148 kb
Host smart-8d52518e-db5d-475c-8c92-cd2448f8faa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069685684 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2069685684
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.4265169113
Short name T419
Test name
Test status
Simulation time 20352444997 ps
CPU time 1344.74 seconds
Started Jul 14 05:08:51 PM PDT 24
Finished Jul 14 05:31:16 PM PDT 24
Peak memory 273512 kb
Host smart-3a63eba0-5c8f-4b28-92e9-baef7b661bfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265169113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.4265169113
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1230351377
Short name T579
Test name
Test status
Simulation time 1941514841 ps
CPU time 20.72 seconds
Started Jul 14 05:08:51 PM PDT 24
Finished Jul 14 05:09:12 PM PDT 24
Peak memory 249104 kb
Host smart-ce937713-7b14-4ae7-89f8-a4638c6f06af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1230351377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1230351377
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.424899330
Short name T223
Test name
Test status
Simulation time 33074897682 ps
CPU time 162.97 seconds
Started Jul 14 05:08:52 PM PDT 24
Finished Jul 14 05:11:36 PM PDT 24
Peak memory 257356 kb
Host smart-299bfe82-b823-4c3b-8212-57b621c4a419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42489
9330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.424899330
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3888768087
Short name T638
Test name
Test status
Simulation time 1537779369 ps
CPU time 51.21 seconds
Started Jul 14 05:08:51 PM PDT 24
Finished Jul 14 05:09:43 PM PDT 24
Peak memory 249116 kb
Host smart-a1e0f90d-e33b-4294-9486-0de57b980242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38887
68087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3888768087
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3118900900
Short name T328
Test name
Test status
Simulation time 75224817070 ps
CPU time 2106.7 seconds
Started Jul 14 05:08:50 PM PDT 24
Finished Jul 14 05:43:57 PM PDT 24
Peak memory 273140 kb
Host smart-0677eb59-849e-4b60-b808-f1d8485c5712
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118900900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3118900900
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2995896297
Short name T559
Test name
Test status
Simulation time 23906800568 ps
CPU time 1227.39 seconds
Started Jul 14 05:08:50 PM PDT 24
Finished Jul 14 05:29:18 PM PDT 24
Peak memory 289664 kb
Host smart-212a625d-e997-45cf-bd51-ce50d2891a3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995896297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2995896297
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1878503281
Short name T620
Test name
Test status
Simulation time 28261086858 ps
CPU time 274.7 seconds
Started Jul 14 05:08:50 PM PDT 24
Finished Jul 14 05:13:25 PM PDT 24
Peak memory 249060 kb
Host smart-c52e6f58-8130-4557-bcd3-90b93d6bda4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878503281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1878503281
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2655919232
Short name T351
Test name
Test status
Simulation time 2981785089 ps
CPU time 46.83 seconds
Started Jul 14 05:08:50 PM PDT 24
Finished Jul 14 05:09:38 PM PDT 24
Peak memory 256756 kb
Host smart-eaa5ad73-3ae3-492e-b545-13ae67739915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26559
19232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2655919232
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3240874379
Short name T693
Test name
Test status
Simulation time 873932022 ps
CPU time 8.48 seconds
Started Jul 14 05:08:43 PM PDT 24
Finished Jul 14 05:08:52 PM PDT 24
Peak memory 252152 kb
Host smart-688cb835-a57f-4e9c-8487-b800f5b171ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32408
74379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3240874379
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2952493162
Short name T479
Test name
Test status
Simulation time 4544044522 ps
CPU time 61.59 seconds
Started Jul 14 05:08:44 PM PDT 24
Finished Jul 14 05:09:47 PM PDT 24
Peak memory 256504 kb
Host smart-4563af8c-8066-4814-963d-916948635223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29524
93162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2952493162
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3036726385
Short name T701
Test name
Test status
Simulation time 4504954610 ps
CPU time 333.51 seconds
Started Jul 14 05:08:49 PM PDT 24
Finished Jul 14 05:14:23 PM PDT 24
Peak memory 257468 kb
Host smart-5ff0ccab-ba05-4329-af30-81abaad0ee4f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036726385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3036726385
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3141666362
Short name T203
Test name
Test status
Simulation time 33696030 ps
CPU time 3.37 seconds
Started Jul 14 05:09:15 PM PDT 24
Finished Jul 14 05:09:18 PM PDT 24
Peak memory 249544 kb
Host smart-e9e94c49-f96b-40ce-bd46-f13c2c648ca9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3141666362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3141666362
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.681102401
Short name T191
Test name
Test status
Simulation time 79526250052 ps
CPU time 1316.55 seconds
Started Jul 14 05:09:10 PM PDT 24
Finished Jul 14 05:31:07 PM PDT 24
Peak memory 273148 kb
Host smart-768362e5-7960-46a6-862d-c3ffd6734223
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681102401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.681102401
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.651717486
Short name T688
Test name
Test status
Simulation time 379589437 ps
CPU time 19.05 seconds
Started Jul 14 05:09:10 PM PDT 24
Finished Jul 14 05:09:29 PM PDT 24
Peak memory 249216 kb
Host smart-86e7440c-262a-49dc-80ca-3f932f016c40
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=651717486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.651717486
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3055437818
Short name T442
Test name
Test status
Simulation time 2390258420 ps
CPU time 114.17 seconds
Started Jul 14 05:09:03 PM PDT 24
Finished Jul 14 05:10:57 PM PDT 24
Peak memory 256912 kb
Host smart-f93065d7-074a-48d9-a541-3e7db9d36507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30554
37818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3055437818
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2591416841
Short name T461
Test name
Test status
Simulation time 498529074 ps
CPU time 10.53 seconds
Started Jul 14 05:08:58 PM PDT 24
Finished Jul 14 05:09:09 PM PDT 24
Peak memory 255260 kb
Host smart-c19e9cac-fd12-4ba5-bc47-ae79b411a6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25914
16841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2591416841
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3942791064
Short name T531
Test name
Test status
Simulation time 61722937061 ps
CPU time 1797.4 seconds
Started Jul 14 05:09:08 PM PDT 24
Finished Jul 14 05:39:06 PM PDT 24
Peak memory 284584 kb
Host smart-98e0f87c-85b5-480c-baf6-6be499ddf5e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942791064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3942791064
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3740624774
Short name T299
Test name
Test status
Simulation time 15573807836 ps
CPU time 170.58 seconds
Started Jul 14 05:09:12 PM PDT 24
Finished Jul 14 05:12:03 PM PDT 24
Peak memory 248996 kb
Host smart-c22cbe92-e21e-42ff-b755-768a270036fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740624774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3740624774
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.4072095991
Short name T504
Test name
Test status
Simulation time 406443619 ps
CPU time 13.47 seconds
Started Jul 14 05:08:58 PM PDT 24
Finished Jul 14 05:09:12 PM PDT 24
Peak memory 249160 kb
Host smart-630b5cb6-1ec5-4d7b-a086-2bd42edf11de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40720
95991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.4072095991
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1373398454
Short name T33
Test name
Test status
Simulation time 525004495 ps
CPU time 9.42 seconds
Started Jul 14 05:08:58 PM PDT 24
Finished Jul 14 05:09:08 PM PDT 24
Peak memory 248468 kb
Host smart-96e9e5f8-8441-476f-b908-b2013b5291cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13733
98454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1373398454
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1255964962
Short name T689
Test name
Test status
Simulation time 253024651 ps
CPU time 17.41 seconds
Started Jul 14 05:08:57 PM PDT 24
Finished Jul 14 05:09:15 PM PDT 24
Peak memory 256440 kb
Host smart-912c048a-4d2f-475c-86fe-edf604e54cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12559
64962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1255964962
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.964118484
Short name T563
Test name
Test status
Simulation time 56380904038 ps
CPU time 1415.44 seconds
Started Jul 14 05:09:09 PM PDT 24
Finished Jul 14 05:32:45 PM PDT 24
Peak memory 289900 kb
Host smart-cdaf9b57-f015-44b3-976d-2af1fbb55883
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964118484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.964118484
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.689914908
Short name T208
Test name
Test status
Simulation time 40478265 ps
CPU time 3.57 seconds
Started Jul 14 05:09:24 PM PDT 24
Finished Jul 14 05:09:29 PM PDT 24
Peak memory 249388 kb
Host smart-fb0242e7-3996-4af5-9a5d-1bc4503911a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=689914908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.689914908
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3774484335
Short name T546
Test name
Test status
Simulation time 19370127050 ps
CPU time 1398.52 seconds
Started Jul 14 05:09:16 PM PDT 24
Finished Jul 14 05:32:35 PM PDT 24
Peak memory 289920 kb
Host smart-4e7fa800-b6f0-4866-96ac-0c1b06b49646
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774484335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3774484335
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2033596393
Short name T575
Test name
Test status
Simulation time 333709655 ps
CPU time 9.95 seconds
Started Jul 14 05:09:24 PM PDT 24
Finished Jul 14 05:09:35 PM PDT 24
Peak memory 249172 kb
Host smart-4a79582b-fd6f-4e15-93d9-fef2014e5d34
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2033596393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2033596393
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.90608081
Short name T225
Test name
Test status
Simulation time 3699238427 ps
CPU time 157.93 seconds
Started Jul 14 05:09:15 PM PDT 24
Finished Jul 14 05:11:53 PM PDT 24
Peak memory 257028 kb
Host smart-c4656b74-56ff-4638-b38b-7d3c675503fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90608
081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.90608081
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2685590745
Short name T421
Test name
Test status
Simulation time 369773249 ps
CPU time 9.07 seconds
Started Jul 14 05:09:14 PM PDT 24
Finished Jul 14 05:09:24 PM PDT 24
Peak memory 249172 kb
Host smart-88774328-f2bb-4a72-93f6-e33501a92f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26855
90745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2685590745
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.186999123
Short name T217
Test name
Test status
Simulation time 29465647463 ps
CPU time 1140.56 seconds
Started Jul 14 05:09:22 PM PDT 24
Finished Jul 14 05:28:23 PM PDT 24
Peak memory 287604 kb
Host smart-ba36869d-5ead-491a-ad5d-51e9f4c1e8c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186999123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.186999123
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.927726501
Short name T311
Test name
Test status
Simulation time 3196082143 ps
CPU time 80.85 seconds
Started Jul 14 05:09:16 PM PDT 24
Finished Jul 14 05:10:38 PM PDT 24
Peak memory 255980 kb
Host smart-d3421c60-6a5c-4628-98dd-9b9f15eb0a49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927726501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.927726501
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2915516297
Short name T537
Test name
Test status
Simulation time 525327425 ps
CPU time 9.79 seconds
Started Jul 14 05:09:15 PM PDT 24
Finished Jul 14 05:09:25 PM PDT 24
Peak memory 249228 kb
Host smart-d8e391bb-edea-4366-945d-d539709d95d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29155
16297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2915516297
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3034207524
Short name T266
Test name
Test status
Simulation time 2713951097 ps
CPU time 35.07 seconds
Started Jul 14 05:09:16 PM PDT 24
Finished Jul 14 05:09:52 PM PDT 24
Peak memory 249252 kb
Host smart-137002c0-3da8-4366-86d3-d2704c55d7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30342
07524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3034207524
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.527436427
Short name T687
Test name
Test status
Simulation time 898793729 ps
CPU time 22.43 seconds
Started Jul 14 05:09:15 PM PDT 24
Finished Jul 14 05:09:38 PM PDT 24
Peak memory 256968 kb
Host smart-2cdcd1c1-33be-48f4-b1bf-51b0505d7920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52743
6427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.527436427
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.763121798
Short name T258
Test name
Test status
Simulation time 292262508882 ps
CPU time 4543.79 seconds
Started Jul 14 05:09:23 PM PDT 24
Finished Jul 14 06:25:08 PM PDT 24
Peak memory 306616 kb
Host smart-056e4afd-8f4e-43dd-ae8c-36dee5fc5eca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763121798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.763121798
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.4100896083
Short name T210
Test name
Test status
Simulation time 469007521 ps
CPU time 2.87 seconds
Started Jul 14 05:09:28 PM PDT 24
Finished Jul 14 05:09:32 PM PDT 24
Peak memory 249528 kb
Host smart-5e33bcae-9847-42af-97c3-0af78c0ce1e7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4100896083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.4100896083
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.4037676380
Short name T644
Test name
Test status
Simulation time 37076940794 ps
CPU time 1805.28 seconds
Started Jul 14 05:09:22 PM PDT 24
Finished Jul 14 05:39:29 PM PDT 24
Peak memory 289068 kb
Host smart-9b3a54bf-a7aa-4ef5-b809-3458f0bdf242
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037676380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.4037676380
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1712730266
Short name T635
Test name
Test status
Simulation time 106562168 ps
CPU time 8.44 seconds
Started Jul 14 05:09:29 PM PDT 24
Finished Jul 14 05:09:38 PM PDT 24
Peak memory 249212 kb
Host smart-8f6c4db1-fd3a-46f7-8000-6288050ffc36
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1712730266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1712730266
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3648255939
Short name T628
Test name
Test status
Simulation time 1641416235 ps
CPU time 154.78 seconds
Started Jul 14 05:09:25 PM PDT 24
Finished Jul 14 05:12:00 PM PDT 24
Peak memory 257372 kb
Host smart-72919dd2-de1e-44ef-8feb-77c2c7c67ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36482
55939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3648255939
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1057117143
Short name T503
Test name
Test status
Simulation time 1214534101 ps
CPU time 41.75 seconds
Started Jul 14 05:09:23 PM PDT 24
Finished Jul 14 05:10:05 PM PDT 24
Peak memory 249172 kb
Host smart-d1008af1-c6b3-4cee-bdcd-5912e2476e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10571
17143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1057117143
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1879347726
Short name T573
Test name
Test status
Simulation time 39252249380 ps
CPU time 1110.25 seconds
Started Jul 14 05:09:22 PM PDT 24
Finished Jul 14 05:27:53 PM PDT 24
Peak memory 290108 kb
Host smart-f1427c0c-d0e8-4d99-b7e0-383d49aca2d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879347726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1879347726
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2303750849
Short name T104
Test name
Test status
Simulation time 54678729775 ps
CPU time 3541.74 seconds
Started Jul 14 05:09:29 PM PDT 24
Finished Jul 14 06:08:32 PM PDT 24
Peak memory 290280 kb
Host smart-b4713836-e627-4e66-ae39-a8cd19436d6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303750849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2303750849
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1890233201
Short name T292
Test name
Test status
Simulation time 12018174869 ps
CPU time 490.36 seconds
Started Jul 14 05:09:23 PM PDT 24
Finished Jul 14 05:17:35 PM PDT 24
Peak memory 256316 kb
Host smart-f2905873-b3c5-43e5-b9b6-254d77cd7302
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890233201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1890233201
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3690239711
Short name T583
Test name
Test status
Simulation time 780503140 ps
CPU time 26.25 seconds
Started Jul 14 05:09:23 PM PDT 24
Finished Jul 14 05:09:50 PM PDT 24
Peak memory 249136 kb
Host smart-ba3df8f4-91dd-4bbd-ba0c-f7bbf90c0c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36902
39711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3690239711
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2413125107
Short name T517
Test name
Test status
Simulation time 3569597151 ps
CPU time 68.82 seconds
Started Jul 14 05:09:23 PM PDT 24
Finished Jul 14 05:10:32 PM PDT 24
Peak memory 249252 kb
Host smart-b6b195d7-293f-4ffc-affe-158cd69a6cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24131
25107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2413125107
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3210938560
Short name T604
Test name
Test status
Simulation time 1857202249 ps
CPU time 30.34 seconds
Started Jul 14 05:09:22 PM PDT 24
Finished Jul 14 05:09:53 PM PDT 24
Peak memory 249224 kb
Host smart-548e71e0-c41b-487f-b526-d86983c0c329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109
38560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3210938560
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2361543101
Short name T60
Test name
Test status
Simulation time 1721147740 ps
CPU time 33.58 seconds
Started Jul 14 05:09:24 PM PDT 24
Finished Jul 14 05:09:59 PM PDT 24
Peak memory 256296 kb
Host smart-9f8f3f68-94a2-4973-b00a-433a9a136d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23615
43101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2361543101
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.4129297282
Short name T103
Test name
Test status
Simulation time 55759416404 ps
CPU time 3268.59 seconds
Started Jul 14 05:09:29 PM PDT 24
Finished Jul 14 06:03:58 PM PDT 24
Peak memory 289872 kb
Host smart-52f8a7cb-ab12-4c4b-8de0-28343870d389
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129297282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.4129297282
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3476964995
Short name T199
Test name
Test status
Simulation time 20175402 ps
CPU time 3.43 seconds
Started Jul 14 05:09:49 PM PDT 24
Finished Jul 14 05:09:52 PM PDT 24
Peak memory 249452 kb
Host smart-6ea6d1a0-4cdc-4da6-aa26-187ff7ba7682
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3476964995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3476964995
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1793564355
Short name T359
Test name
Test status
Simulation time 32160199828 ps
CPU time 1410.11 seconds
Started Jul 14 05:09:47 PM PDT 24
Finished Jul 14 05:33:18 PM PDT 24
Peak memory 289556 kb
Host smart-200eb597-4dba-4756-868b-6a4815b7cf2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793564355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1793564355
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2272953373
Short name T189
Test name
Test status
Simulation time 144375904 ps
CPU time 9.82 seconds
Started Jul 14 05:09:47 PM PDT 24
Finished Jul 14 05:09:57 PM PDT 24
Peak memory 249152 kb
Host smart-81000263-a26a-4b4f-bd47-c47d351179db
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2272953373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2272953373
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1668650517
Short name T555
Test name
Test status
Simulation time 4541775822 ps
CPU time 157.42 seconds
Started Jul 14 05:09:45 PM PDT 24
Finished Jul 14 05:12:23 PM PDT 24
Peak memory 257008 kb
Host smart-d58c551d-d59e-48f8-a223-fe3e4b18eca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16686
50517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1668650517
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.4021468252
Short name T607
Test name
Test status
Simulation time 1042166452 ps
CPU time 60.19 seconds
Started Jul 14 05:09:39 PM PDT 24
Finished Jul 14 05:10:40 PM PDT 24
Peak memory 249620 kb
Host smart-ac879770-c694-419d-8a1d-ad7ea6810c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40214
68252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4021468252
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3824618763
Short name T545
Test name
Test status
Simulation time 59857726023 ps
CPU time 1139.04 seconds
Started Jul 14 05:09:46 PM PDT 24
Finished Jul 14 05:28:45 PM PDT 24
Peak memory 273852 kb
Host smart-9d919504-25f2-4d93-9040-5e2f0d1c9082
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824618763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3824618763
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1391261241
Short name T532
Test name
Test status
Simulation time 9013606467 ps
CPU time 1122.1 seconds
Started Jul 14 05:09:47 PM PDT 24
Finished Jul 14 05:28:29 PM PDT 24
Peak memory 290276 kb
Host smart-d24b59ca-eb60-4520-a85e-0217b109f2c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391261241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1391261241
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2754277634
Short name T667
Test name
Test status
Simulation time 57595283121 ps
CPU time 589.3 seconds
Started Jul 14 05:09:46 PM PDT 24
Finished Jul 14 05:19:36 PM PDT 24
Peak memory 248348 kb
Host smart-df3b3612-b784-4e1b-a569-64f8594979e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754277634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2754277634
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3469550271
Short name T436
Test name
Test status
Simulation time 4020106797 ps
CPU time 69.11 seconds
Started Jul 14 05:09:41 PM PDT 24
Finished Jul 14 05:10:51 PM PDT 24
Peak memory 256692 kb
Host smart-135a4852-3a85-4838-bae2-da11420a9d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34695
50271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3469550271
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3489136508
Short name T471
Test name
Test status
Simulation time 2005578995 ps
CPU time 34.64 seconds
Started Jul 14 05:09:41 PM PDT 24
Finished Jul 14 05:10:16 PM PDT 24
Peak memory 256612 kb
Host smart-8d182d3e-677a-4735-b3b5-616388e77d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34891
36508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3489136508
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.53263215
Short name T59
Test name
Test status
Simulation time 804913824 ps
CPU time 56.96 seconds
Started Jul 14 05:09:42 PM PDT 24
Finished Jul 14 05:10:39 PM PDT 24
Peak memory 257336 kb
Host smart-ec31d2f9-5d76-4278-80b4-e22cd02c593a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53263
215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.53263215
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3715209467
Short name T662
Test name
Test status
Simulation time 2230031566 ps
CPU time 115.39 seconds
Started Jul 14 05:09:46 PM PDT 24
Finished Jul 14 05:11:42 PM PDT 24
Peak memory 257472 kb
Host smart-f7da9dc6-b6de-4997-a330-f6c62536827a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715209467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3715209467
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.4269171513
Short name T84
Test name
Test status
Simulation time 36495156 ps
CPU time 3.63 seconds
Started Jul 14 05:09:59 PM PDT 24
Finished Jul 14 05:10:03 PM PDT 24
Peak memory 249552 kb
Host smart-c85bc9f9-b6dd-4844-9ed1-62d451078b9b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4269171513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.4269171513
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2094971797
Short name T502
Test name
Test status
Simulation time 225865031147 ps
CPU time 2048.86 seconds
Started Jul 14 05:09:54 PM PDT 24
Finished Jul 14 05:44:03 PM PDT 24
Peak memory 273412 kb
Host smart-aa50a52f-3edf-4fba-afe3-5b7204896859
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094971797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2094971797
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2334567138
Short name T406
Test name
Test status
Simulation time 181637499 ps
CPU time 11.33 seconds
Started Jul 14 05:10:03 PM PDT 24
Finished Jul 14 05:10:14 PM PDT 24
Peak memory 249156 kb
Host smart-cd7844fb-ef0a-40d9-a8a7-e4ec699f0f3c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2334567138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2334567138
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2675029658
Short name T589
Test name
Test status
Simulation time 5803304320 ps
CPU time 80.82 seconds
Started Jul 14 05:09:57 PM PDT 24
Finished Jul 14 05:11:18 PM PDT 24
Peak memory 257100 kb
Host smart-cbeb7a8a-eac5-4e13-b080-7aac2f8adc25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26750
29658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2675029658
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3478480659
Short name T63
Test name
Test status
Simulation time 362469398 ps
CPU time 13.35 seconds
Started Jul 14 05:09:55 PM PDT 24
Finished Jul 14 05:10:08 PM PDT 24
Peak memory 249008 kb
Host smart-97cc2bf9-2a79-489d-8a67-cc7c4dc812ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34784
80659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3478480659
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2308626895
Short name T329
Test name
Test status
Simulation time 16310773854 ps
CPU time 1475.43 seconds
Started Jul 14 05:09:59 PM PDT 24
Finished Jul 14 05:34:35 PM PDT 24
Peak memory 290132 kb
Host smart-0d6fd295-b5b7-4452-ba5f-0e33680fd4cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308626895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2308626895
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1061526476
Short name T588
Test name
Test status
Simulation time 349260755754 ps
CPU time 1980.3 seconds
Started Jul 14 05:10:01 PM PDT 24
Finished Jul 14 05:43:02 PM PDT 24
Peak memory 273904 kb
Host smart-579c09ca-a94c-4dff-a71a-d6141af231f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061526476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1061526476
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2866207309
Short name T295
Test name
Test status
Simulation time 8138669849 ps
CPU time 321.1 seconds
Started Jul 14 05:10:01 PM PDT 24
Finished Jul 14 05:15:22 PM PDT 24
Peak memory 249100 kb
Host smart-fa36f32f-669a-490f-9e66-c58b236881f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866207309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2866207309
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3024599354
Short name T399
Test name
Test status
Simulation time 129530285 ps
CPU time 9.5 seconds
Started Jul 14 05:09:56 PM PDT 24
Finished Jul 14 05:10:06 PM PDT 24
Peak memory 249244 kb
Host smart-0e23ad02-48b9-464a-9d69-b6a5a9d462ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30245
99354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3024599354
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3181041849
Short name T495
Test name
Test status
Simulation time 19313743 ps
CPU time 3.22 seconds
Started Jul 14 05:09:52 PM PDT 24
Finished Jul 14 05:09:56 PM PDT 24
Peak memory 240224 kb
Host smart-742f2b0b-dfd4-4734-80d2-0eb0bb673a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31810
41849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3181041849
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.525850638
Short name T446
Test name
Test status
Simulation time 680801740 ps
CPU time 43.45 seconds
Started Jul 14 05:09:53 PM PDT 24
Finished Jul 14 05:10:37 PM PDT 24
Peak memory 249128 kb
Host smart-dad54eb5-b735-4cbd-8f25-97bc4467c3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52585
0638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.525850638
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.453235553
Short name T273
Test name
Test status
Simulation time 25272880043 ps
CPU time 1349.78 seconds
Started Jul 14 05:09:58 PM PDT 24
Finished Jul 14 05:32:28 PM PDT 24
Peak memory 284156 kb
Host smart-d7b14238-1e87-4de7-837e-9d908c599b52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453235553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.453235553
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.804899889
Short name T561
Test name
Test status
Simulation time 51649144385 ps
CPU time 5312.6 seconds
Started Jul 14 05:10:11 PM PDT 24
Finished Jul 14 06:38:44 PM PDT 24
Peak memory 348500 kb
Host smart-0e36d371-97aa-4735-bb16-8a14888d9d0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804899889 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.804899889
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.560246472
Short name T195
Test name
Test status
Simulation time 72015027 ps
CPU time 2.46 seconds
Started Jul 14 05:06:41 PM PDT 24
Finished Jul 14 05:06:45 PM PDT 24
Peak memory 249432 kb
Host smart-7a15abb0-ee37-42b9-b834-59c7922c87c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=560246472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.560246472
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1258006831
Short name T613
Test name
Test status
Simulation time 18433005109 ps
CPU time 1782.64 seconds
Started Jul 14 05:06:40 PM PDT 24
Finished Jul 14 05:36:24 PM PDT 24
Peak memory 289392 kb
Host smart-c43a7613-03de-4c22-9eaf-598ff9d6db2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258006831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1258006831
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1171257183
Short name T376
Test name
Test status
Simulation time 3096250586 ps
CPU time 23.75 seconds
Started Jul 14 05:06:41 PM PDT 24
Finished Jul 14 05:07:06 PM PDT 24
Peak memory 249220 kb
Host smart-cf045b69-b3d3-4e99-8407-dd8f52fa846a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1171257183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1171257183
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2507070434
Short name T501
Test name
Test status
Simulation time 18227521889 ps
CPU time 315.79 seconds
Started Jul 14 05:06:41 PM PDT 24
Finished Jul 14 05:11:58 PM PDT 24
Peak memory 257360 kb
Host smart-8383478d-80e6-45b5-a6e8-50d0fca4fe82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25070
70434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2507070434
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2401773760
Short name T473
Test name
Test status
Simulation time 1251821485 ps
CPU time 18.63 seconds
Started Jul 14 05:06:43 PM PDT 24
Finished Jul 14 05:07:02 PM PDT 24
Peak memory 255416 kb
Host smart-3884f930-2b10-4ca2-a9d4-ddcbaa15aab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24017
73760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2401773760
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2199610055
Short name T630
Test name
Test status
Simulation time 16576788453 ps
CPU time 1493.63 seconds
Started Jul 14 05:06:41 PM PDT 24
Finished Jul 14 05:31:36 PM PDT 24
Peak memory 289120 kb
Host smart-ef052cd0-e1c5-4c98-910b-ba09e990c1ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199610055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2199610055
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1695416915
Short name T379
Test name
Test status
Simulation time 10693394761 ps
CPU time 1272.17 seconds
Started Jul 14 05:06:41 PM PDT 24
Finished Jul 14 05:27:55 PM PDT 24
Peak memory 284980 kb
Host smart-d438169a-7b04-44d7-b487-2324cecac96a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695416915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1695416915
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1112684959
Short name T9
Test name
Test status
Simulation time 16268197769 ps
CPU time 290.51 seconds
Started Jul 14 05:06:41 PM PDT 24
Finished Jul 14 05:11:32 PM PDT 24
Peak memory 257504 kb
Host smart-b7378533-5862-4e81-a10d-1e72acb21d76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112684959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1112684959
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1156138789
Short name T574
Test name
Test status
Simulation time 148963618 ps
CPU time 10.71 seconds
Started Jul 14 05:06:35 PM PDT 24
Finished Jul 14 05:06:46 PM PDT 24
Peak memory 249192 kb
Host smart-19c23101-d051-4637-a8db-986fefe05168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11561
38789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1156138789
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2012957289
Short name T389
Test name
Test status
Simulation time 1799507965 ps
CPU time 56.79 seconds
Started Jul 14 05:06:35 PM PDT 24
Finished Jul 14 05:07:32 PM PDT 24
Peak memory 256852 kb
Host smart-12412511-765a-4ce2-ae9f-8407ee3ec6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20129
57289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2012957289
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2875770442
Short name T29
Test name
Test status
Simulation time 812633752 ps
CPU time 14.4 seconds
Started Jul 14 05:06:41 PM PDT 24
Finished Jul 14 05:06:56 PM PDT 24
Peak memory 272420 kb
Host smart-eaa841a4-bc40-4744-a1dc-102f899436a1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2875770442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2875770442
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2638259342
Short name T660
Test name
Test status
Simulation time 450362177 ps
CPU time 16.55 seconds
Started Jul 14 05:06:40 PM PDT 24
Finished Jul 14 05:06:58 PM PDT 24
Peak memory 255712 kb
Host smart-569446ab-0dab-4998-bfb9-a7871e2d6df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26382
59342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2638259342
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3860339290
Short name T706
Test name
Test status
Simulation time 2431392603 ps
CPU time 29.94 seconds
Started Jul 14 05:06:35 PM PDT 24
Finished Jul 14 05:07:06 PM PDT 24
Peak memory 256932 kb
Host smart-b9eb513c-82ed-4e69-a363-0b8162e4085a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38603
39290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3860339290
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3907016283
Short name T20
Test name
Test status
Simulation time 34729701408 ps
CPU time 2306.04 seconds
Started Jul 14 05:06:41 PM PDT 24
Finished Jul 14 05:45:08 PM PDT 24
Peak memory 289500 kb
Host smart-e41b97fa-e230-414e-970a-0b4d765fc518
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907016283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3907016283
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2461245036
Short name T642
Test name
Test status
Simulation time 20578861017 ps
CPU time 1273.02 seconds
Started Jul 14 05:10:09 PM PDT 24
Finished Jul 14 05:31:23 PM PDT 24
Peak memory 273448 kb
Host smart-346f501b-06bf-4b7e-99e3-f36ffcf8c42d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461245036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2461245036
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3073048377
Short name T427
Test name
Test status
Simulation time 15826549225 ps
CPU time 239.65 seconds
Started Jul 14 05:10:09 PM PDT 24
Finished Jul 14 05:14:09 PM PDT 24
Peak memory 257408 kb
Host smart-51a3d963-02b6-43c7-9578-9a7155003531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30730
48377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3073048377
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1271497442
Short name T679
Test name
Test status
Simulation time 707101595 ps
CPU time 49.44 seconds
Started Jul 14 05:10:09 PM PDT 24
Finished Jul 14 05:10:58 PM PDT 24
Peak memory 248628 kb
Host smart-b846c42d-322a-44c8-9da7-146dd14b2647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12714
97442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1271497442
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2252480592
Short name T540
Test name
Test status
Simulation time 67392520568 ps
CPU time 1502.07 seconds
Started Jul 14 05:10:16 PM PDT 24
Finished Jul 14 05:35:18 PM PDT 24
Peak memory 289940 kb
Host smart-c3343e77-3623-48d8-b159-5a1f732673f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252480592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2252480592
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.480785117
Short name T27
Test name
Test status
Simulation time 118167940111 ps
CPU time 1180.26 seconds
Started Jul 14 05:10:15 PM PDT 24
Finished Jul 14 05:29:56 PM PDT 24
Peak memory 282668 kb
Host smart-e000d8e7-7205-4065-b2b8-2bce1b09d980
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480785117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.480785117
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3692262296
Short name T287
Test name
Test status
Simulation time 10882603984 ps
CPU time 403.41 seconds
Started Jul 14 05:10:16 PM PDT 24
Finished Jul 14 05:17:00 PM PDT 24
Peak memory 255928 kb
Host smart-72a2c36c-ed2d-4ad3-b82d-4fd51b140835
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692262296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3692262296
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1795211942
Short name T414
Test name
Test status
Simulation time 1090366513 ps
CPU time 26.36 seconds
Started Jul 14 05:10:10 PM PDT 24
Finished Jul 14 05:10:36 PM PDT 24
Peak memory 249152 kb
Host smart-6c440d00-a360-4a77-8159-ae00b59115a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17952
11942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1795211942
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2232610650
Short name T110
Test name
Test status
Simulation time 1021162151 ps
CPU time 27.43 seconds
Started Jul 14 05:10:10 PM PDT 24
Finished Jul 14 05:10:37 PM PDT 24
Peak memory 248696 kb
Host smart-4979d853-ed29-4c10-b4ed-628447f67aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22326
10650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2232610650
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.711973465
Short name T429
Test name
Test status
Simulation time 1335668587 ps
CPU time 36.37 seconds
Started Jul 14 05:10:07 PM PDT 24
Finished Jul 14 05:10:44 PM PDT 24
Peak memory 257356 kb
Host smart-463c31bd-c158-4b68-b7f2-26dceec9abb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71197
3465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.711973465
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3195237862
Short name T343
Test name
Test status
Simulation time 53009542 ps
CPU time 2.9 seconds
Started Jul 14 05:10:09 PM PDT 24
Finished Jul 14 05:10:13 PM PDT 24
Peak memory 249532 kb
Host smart-95852cf8-d226-44d8-9e5b-b16e3dba25fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31952
37862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3195237862
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1993798957
Short name T41
Test name
Test status
Simulation time 22346416964 ps
CPU time 830.51 seconds
Started Jul 14 05:10:23 PM PDT 24
Finished Jul 14 05:24:14 PM PDT 24
Peak memory 271004 kb
Host smart-88b1e38b-fd8a-49ce-8ee8-792ed1189cf8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993798957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1993798957
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1753344744
Short name T594
Test name
Test status
Simulation time 7407445869 ps
CPU time 128.67 seconds
Started Jul 14 05:10:24 PM PDT 24
Finished Jul 14 05:12:33 PM PDT 24
Peak memory 256896 kb
Host smart-fcbb7711-2522-4307-b5b6-e30d36399063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17533
44744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1753344744
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.112051565
Short name T30
Test name
Test status
Simulation time 1087766233 ps
CPU time 17.46 seconds
Started Jul 14 05:10:23 PM PDT 24
Finished Jul 14 05:10:41 PM PDT 24
Peak memory 254056 kb
Host smart-f81a1452-6949-4a51-8e6b-300c022da8c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11205
1565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.112051565
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1795064887
Short name T8
Test name
Test status
Simulation time 80265272562 ps
CPU time 1659.32 seconds
Started Jul 14 05:10:24 PM PDT 24
Finished Jul 14 05:38:04 PM PDT 24
Peak memory 289984 kb
Host smart-70230721-cdaf-457a-94e4-fb24ab9f5ac1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795064887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1795064887
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1270132677
Short name T682
Test name
Test status
Simulation time 9518066104 ps
CPU time 89.4 seconds
Started Jul 14 05:10:23 PM PDT 24
Finished Jul 14 05:11:53 PM PDT 24
Peak memory 249364 kb
Host smart-871864c1-e88c-4b9c-9401-e824484e1e6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270132677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1270132677
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2508819634
Short name T512
Test name
Test status
Simulation time 422440460 ps
CPU time 32.68 seconds
Started Jul 14 05:10:18 PM PDT 24
Finished Jul 14 05:10:51 PM PDT 24
Peak memory 256600 kb
Host smart-0e5e1588-526e-42c7-8b56-f8ad17a7fc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25088
19634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2508819634
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3126884360
Short name T586
Test name
Test status
Simulation time 627661209 ps
CPU time 30.55 seconds
Started Jul 14 05:10:23 PM PDT 24
Finished Jul 14 05:10:54 PM PDT 24
Peak memory 248764 kb
Host smart-c2dccf90-78fe-4406-8684-cbaaabf65eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31268
84360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3126884360
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3911023790
Short name T425
Test name
Test status
Simulation time 352351369 ps
CPU time 26.83 seconds
Started Jul 14 05:10:15 PM PDT 24
Finished Jul 14 05:10:43 PM PDT 24
Peak memory 249192 kb
Host smart-88249ac3-c2f8-4ac9-91fa-0fb8b7e7db6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39110
23790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3911023790
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3875175207
Short name T599
Test name
Test status
Simulation time 3153374919 ps
CPU time 51.55 seconds
Started Jul 14 05:10:24 PM PDT 24
Finished Jul 14 05:11:16 PM PDT 24
Peak memory 257580 kb
Host smart-cf9409b9-d143-4725-a587-49d1c2689297
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875175207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3875175207
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1586068116
Short name T79
Test name
Test status
Simulation time 34577537054 ps
CPU time 2272.55 seconds
Started Jul 14 05:10:28 PM PDT 24
Finished Jul 14 05:48:22 PM PDT 24
Peak memory 290052 kb
Host smart-45d4791e-b81e-4b79-a8a4-1541244e5286
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586068116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1586068116
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.550015044
Short name T412
Test name
Test status
Simulation time 1074969927 ps
CPU time 94.88 seconds
Started Jul 14 05:10:41 PM PDT 24
Finished Jul 14 05:12:16 PM PDT 24
Peak memory 257336 kb
Host smart-a61ad3c5-6b90-4a7f-822f-758cdbab922e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55001
5044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.550015044
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3580646839
Short name T226
Test name
Test status
Simulation time 1346942372 ps
CPU time 51.47 seconds
Started Jul 14 05:10:29 PM PDT 24
Finished Jul 14 05:11:21 PM PDT 24
Peak memory 249008 kb
Host smart-436eac37-982d-4e4e-869f-5e8f9ab54880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35806
46839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3580646839
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1630991617
Short name T303
Test name
Test status
Simulation time 177832060918 ps
CPU time 1342.23 seconds
Started Jul 14 05:10:28 PM PDT 24
Finished Jul 14 05:32:52 PM PDT 24
Peak memory 290076 kb
Host smart-cc8e3751-5f1b-4f13-88cb-11ec1a82e21a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630991617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1630991617
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1739442683
Short name T413
Test name
Test status
Simulation time 29684956845 ps
CPU time 2193.53 seconds
Started Jul 14 05:10:27 PM PDT 24
Finished Jul 14 05:47:01 PM PDT 24
Peak memory 286396 kb
Host smart-af70c0d6-3a2d-4814-8609-2d98505b516e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739442683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1739442683
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4001950745
Short name T456
Test name
Test status
Simulation time 547898414 ps
CPU time 18.15 seconds
Started Jul 14 05:10:30 PM PDT 24
Finished Jul 14 05:10:49 PM PDT 24
Peak memory 249184 kb
Host smart-a0d026ed-c885-4c3d-9208-4fbcad26f510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40019
50745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4001950745
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.4191407095
Short name T526
Test name
Test status
Simulation time 300571532 ps
CPU time 23.19 seconds
Started Jul 14 05:10:29 PM PDT 24
Finished Jul 14 05:10:53 PM PDT 24
Peak memory 255028 kb
Host smart-25b5279f-6960-46ed-becb-826a50efcbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41914
07095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.4191407095
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2555518202
Short name T374
Test name
Test status
Simulation time 106552498 ps
CPU time 15.8 seconds
Started Jul 14 05:10:23 PM PDT 24
Finished Jul 14 05:10:39 PM PDT 24
Peak memory 257340 kb
Host smart-8df6452f-e2e0-4c7a-80ed-b9928c7690e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25555
18202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2555518202
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.987305389
Short name T634
Test name
Test status
Simulation time 272670391826 ps
CPU time 3427.16 seconds
Started Jul 14 05:10:30 PM PDT 24
Finished Jul 14 06:07:38 PM PDT 24
Peak memory 290260 kb
Host smart-36a687c8-fb95-4523-8477-f4c429f76d3e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987305389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.987305389
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3547177901
Short name T676
Test name
Test status
Simulation time 60952875965 ps
CPU time 1825.81 seconds
Started Jul 14 05:10:44 PM PDT 24
Finished Jul 14 05:41:10 PM PDT 24
Peak memory 284208 kb
Host smart-4d07e160-e772-4435-b5f0-aa7baa76de18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547177901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3547177901
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2345489897
Short name T222
Test name
Test status
Simulation time 24932669261 ps
CPU time 330.91 seconds
Started Jul 14 05:10:40 PM PDT 24
Finished Jul 14 05:16:11 PM PDT 24
Peak memory 257448 kb
Host smart-46604654-ac64-42ba-92a7-3465f2eab59a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23454
89897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2345489897
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1791524997
Short name T710
Test name
Test status
Simulation time 2658333458 ps
CPU time 32.13 seconds
Started Jul 14 05:10:41 PM PDT 24
Finished Jul 14 05:11:14 PM PDT 24
Peak memory 249236 kb
Host smart-532ff5c5-e82b-4dd0-93d8-979e4b04ece4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17915
24997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1791524997
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2464916561
Short name T318
Test name
Test status
Simulation time 38161374472 ps
CPU time 2598.1 seconds
Started Jul 14 05:10:43 PM PDT 24
Finished Jul 14 05:54:02 PM PDT 24
Peak memory 290268 kb
Host smart-0185bd13-293e-43fd-9de0-5017dbe72911
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464916561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2464916561
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3306247365
Short name T477
Test name
Test status
Simulation time 21891234877 ps
CPU time 833.05 seconds
Started Jul 14 05:10:42 PM PDT 24
Finished Jul 14 05:24:35 PM PDT 24
Peak memory 270844 kb
Host smart-ffde7158-db24-424d-a316-987e12157f45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306247365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3306247365
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.351030530
Short name T312
Test name
Test status
Simulation time 56660254046 ps
CPU time 165.12 seconds
Started Jul 14 05:10:41 PM PDT 24
Finished Jul 14 05:13:26 PM PDT 24
Peak memory 255908 kb
Host smart-fa82d894-35e1-41fe-8b98-adc20db5fde2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351030530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.351030530
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3585833290
Short name T91
Test name
Test status
Simulation time 765705406 ps
CPU time 38.38 seconds
Started Jul 14 05:10:41 PM PDT 24
Finished Jul 14 05:11:20 PM PDT 24
Peak memory 256432 kb
Host smart-72979cdf-ba11-4419-ae5c-9d8743571fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35858
33290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3585833290
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3821387659
Short name T220
Test name
Test status
Simulation time 29166101 ps
CPU time 5.73 seconds
Started Jul 14 05:10:39 PM PDT 24
Finished Jul 14 05:10:45 PM PDT 24
Peak memory 240496 kb
Host smart-067e46cc-a711-403f-ace7-877fad3a802b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38213
87659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3821387659
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3301652455
Short name T520
Test name
Test status
Simulation time 534300745 ps
CPU time 18.32 seconds
Started Jul 14 05:10:45 PM PDT 24
Finished Jul 14 05:11:04 PM PDT 24
Peak memory 249252 kb
Host smart-a24e6d05-5968-4d6b-abda-7203574e2275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33016
52455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3301652455
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.632527553
Short name T415
Test name
Test status
Simulation time 508140871 ps
CPU time 29 seconds
Started Jul 14 05:10:28 PM PDT 24
Finished Jul 14 05:10:57 PM PDT 24
Peak memory 255876 kb
Host smart-b8bfa37c-681a-4086-9b36-321d174e698e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63252
7553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.632527553
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.260155186
Short name T52
Test name
Test status
Simulation time 55679408002 ps
CPU time 2137.72 seconds
Started Jul 14 05:10:54 PM PDT 24
Finished Jul 14 05:46:32 PM PDT 24
Peak memory 284840 kb
Host smart-ee987542-7493-42bd-93b2-2f292335bd27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260155186 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.260155186
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3238589735
Short name T39
Test name
Test status
Simulation time 93285170076 ps
CPU time 1715.62 seconds
Started Jul 14 05:11:01 PM PDT 24
Finished Jul 14 05:39:37 PM PDT 24
Peak memory 273784 kb
Host smart-7e80f14b-f122-4c99-a990-bfd0538ff1d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238589735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3238589735
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2381625058
Short name T350
Test name
Test status
Simulation time 44008139 ps
CPU time 4.75 seconds
Started Jul 14 05:11:00 PM PDT 24
Finished Jul 14 05:11:05 PM PDT 24
Peak memory 240536 kb
Host smart-63db232d-3dca-4aad-8b27-86a6ac4d69bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23816
25058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2381625058
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.799350122
Short name T544
Test name
Test status
Simulation time 140920222 ps
CPU time 7.29 seconds
Started Jul 14 05:10:52 PM PDT 24
Finished Jul 14 05:11:00 PM PDT 24
Peak memory 249040 kb
Host smart-eaa88774-ca00-4ee9-86db-a36e95d77ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79935
0122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.799350122
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.683241252
Short name T260
Test name
Test status
Simulation time 24473274015 ps
CPU time 1090.19 seconds
Started Jul 14 05:11:01 PM PDT 24
Finished Jul 14 05:29:11 PM PDT 24
Peak memory 283424 kb
Host smart-58632609-8d16-4539-b9d6-03d7d2f1e02d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683241252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.683241252
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.334230643
Short name T566
Test name
Test status
Simulation time 11837596538 ps
CPU time 1196.5 seconds
Started Jul 14 05:11:01 PM PDT 24
Finished Jul 14 05:30:58 PM PDT 24
Peak memory 272488 kb
Host smart-515bfc87-4d7b-4de8-a9cf-477a7a79a114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334230643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.334230643
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3833437242
Short name T448
Test name
Test status
Simulation time 3101221395 ps
CPU time 135.99 seconds
Started Jul 14 05:11:02 PM PDT 24
Finished Jul 14 05:13:18 PM PDT 24
Peak memory 249280 kb
Host smart-fea08563-0b0a-4e51-95dc-8b76d7c2dc06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833437242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3833437242
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1770955854
Short name T541
Test name
Test status
Simulation time 261861632 ps
CPU time 5.16 seconds
Started Jul 14 05:10:56 PM PDT 24
Finished Jul 14 05:11:01 PM PDT 24
Peak memory 249156 kb
Host smart-a7ce9297-2344-4a35-9a8f-46edbf1b25e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17709
55854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1770955854
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2732242943
Short name T5
Test name
Test status
Simulation time 173708709 ps
CPU time 4.76 seconds
Started Jul 14 05:10:54 PM PDT 24
Finished Jul 14 05:10:59 PM PDT 24
Peak memory 249164 kb
Host smart-045d0103-9cf9-4910-ae0b-1156bd51657d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27322
42943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2732242943
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1340037236
Short name T274
Test name
Test status
Simulation time 3100487870 ps
CPU time 55.81 seconds
Started Jul 14 05:11:01 PM PDT 24
Finished Jul 14 05:11:57 PM PDT 24
Peak memory 257488 kb
Host smart-e3d8449e-30cb-4f82-89e3-68051de20050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13400
37236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1340037236
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3511262744
Short name T472
Test name
Test status
Simulation time 8143352350 ps
CPU time 40.94 seconds
Started Jul 14 05:10:53 PM PDT 24
Finished Jul 14 05:11:34 PM PDT 24
Peak memory 257192 kb
Host smart-827959d2-3932-4f19-b128-b948717d7c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35112
62744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3511262744
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1051436474
Short name T182
Test name
Test status
Simulation time 90405627681 ps
CPU time 3155.6 seconds
Started Jul 14 05:11:00 PM PDT 24
Finished Jul 14 06:03:37 PM PDT 24
Peak memory 303748 kb
Host smart-fc5f2331-292f-4b89-bbf4-4958694217d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051436474 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1051436474
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.4099153932
Short name T564
Test name
Test status
Simulation time 76112790111 ps
CPU time 1268.67 seconds
Started Jul 14 05:11:17 PM PDT 24
Finished Jul 14 05:32:26 PM PDT 24
Peak memory 273352 kb
Host smart-490912f7-5071-444a-8ac0-c9e755b50ce1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099153932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4099153932
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2078101608
Short name T505
Test name
Test status
Simulation time 3187294274 ps
CPU time 136.15 seconds
Started Jul 14 05:11:17 PM PDT 24
Finished Jul 14 05:13:33 PM PDT 24
Peak memory 256852 kb
Host smart-d0227003-5975-4e22-a982-86000f82a66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20781
01608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2078101608
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4033945007
Short name T678
Test name
Test status
Simulation time 2285356914 ps
CPU time 39.68 seconds
Started Jul 14 05:11:10 PM PDT 24
Finished Jul 14 05:11:50 PM PDT 24
Peak memory 249324 kb
Host smart-984132e6-f9a3-452a-b7e2-2d44932ae6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40339
45007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4033945007
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1121427427
Short name T426
Test name
Test status
Simulation time 28958609154 ps
CPU time 1831.06 seconds
Started Jul 14 05:11:18 PM PDT 24
Finished Jul 14 05:41:50 PM PDT 24
Peak memory 285448 kb
Host smart-d5c5cafb-b460-4618-a4ab-0d570cb6a5c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121427427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1121427427
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.161471752
Short name T700
Test name
Test status
Simulation time 640490328 ps
CPU time 15.3 seconds
Started Jul 14 05:11:01 PM PDT 24
Finished Jul 14 05:11:16 PM PDT 24
Peak memory 257356 kb
Host smart-e6cc040d-1b38-465a-b12b-c131c3e49431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16147
1752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.161471752
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3312405762
Short name T398
Test name
Test status
Simulation time 3224264086 ps
CPU time 42.44 seconds
Started Jul 14 05:11:10 PM PDT 24
Finished Jul 14 05:11:53 PM PDT 24
Peak memory 249224 kb
Host smart-cd8b7593-fa92-4f27-802e-45e868e2dee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33124
05762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3312405762
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2639179726
Short name T420
Test name
Test status
Simulation time 781145290 ps
CPU time 53.69 seconds
Started Jul 14 05:11:16 PM PDT 24
Finished Jul 14 05:12:10 PM PDT 24
Peak memory 257368 kb
Host smart-8c601561-c91f-4937-b9ac-c49f8fe31a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26391
79726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2639179726
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1590620604
Short name T470
Test name
Test status
Simulation time 1038438945 ps
CPU time 33.99 seconds
Started Jul 14 05:11:00 PM PDT 24
Finished Jul 14 05:11:34 PM PDT 24
Peak memory 257324 kb
Host smart-1b866c61-ba9a-44f7-8496-e1fb3ec323a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15906
20604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1590620604
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3854751659
Short name T712
Test name
Test status
Simulation time 138890933223 ps
CPU time 2325.9 seconds
Started Jul 14 05:11:18 PM PDT 24
Finished Jul 14 05:50:05 PM PDT 24
Peak memory 289520 kb
Host smart-8ce024f8-dbbf-4595-a5a0-880c0eec1ab8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854751659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3854751659
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3313954330
Short name T577
Test name
Test status
Simulation time 159909287117 ps
CPU time 2611.8 seconds
Started Jul 14 05:11:26 PM PDT 24
Finished Jul 14 05:54:58 PM PDT 24
Peak memory 290028 kb
Host smart-525ee9c3-1c45-4086-bbd5-67499288521e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313954330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3313954330
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3358572803
Short name T611
Test name
Test status
Simulation time 27351500601 ps
CPU time 247.53 seconds
Started Jul 14 05:11:20 PM PDT 24
Finished Jul 14 05:15:28 PM PDT 24
Peak memory 257412 kb
Host smart-2174a092-c2b4-4f2d-8585-d1e22fb2d459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33585
72803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3358572803
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1720550713
Short name T345
Test name
Test status
Simulation time 246461338 ps
CPU time 6.13 seconds
Started Jul 14 05:11:21 PM PDT 24
Finished Jul 14 05:11:27 PM PDT 24
Peak memory 249540 kb
Host smart-1691a85c-b796-411b-955b-1634f9941316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17205
50713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1720550713
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1281544040
Short name T519
Test name
Test status
Simulation time 25745189998 ps
CPU time 1732.5 seconds
Started Jul 14 05:11:25 PM PDT 24
Finished Jul 14 05:40:18 PM PDT 24
Peak memory 273216 kb
Host smart-d1a891e3-ab05-4c2c-81aa-40fe7d1b496a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281544040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1281544040
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1386994712
Short name T93
Test name
Test status
Simulation time 23711357970 ps
CPU time 1586.45 seconds
Started Jul 14 05:11:26 PM PDT 24
Finished Jul 14 05:37:53 PM PDT 24
Peak memory 273908 kb
Host smart-974238df-21f7-47d7-a587-d8b5b2a67ff5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386994712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1386994712
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.4191064296
Short name T483
Test name
Test status
Simulation time 4622995084 ps
CPU time 179.79 seconds
Started Jul 14 05:11:24 PM PDT 24
Finished Jul 14 05:14:25 PM PDT 24
Peak memory 256124 kb
Host smart-ef217762-4b66-4052-bafa-c432674315f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191064296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.4191064296
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.720779450
Short name T538
Test name
Test status
Simulation time 102259676 ps
CPU time 13.77 seconds
Started Jul 14 05:11:22 PM PDT 24
Finished Jul 14 05:11:36 PM PDT 24
Peak memory 249116 kb
Host smart-e552e6d4-6686-4030-b8e1-93015a81d37d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72077
9450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.720779450
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.4022937636
Short name T349
Test name
Test status
Simulation time 2872540943 ps
CPU time 48.06 seconds
Started Jul 14 05:11:23 PM PDT 24
Finished Jul 14 05:12:12 PM PDT 24
Peak memory 257172 kb
Host smart-75d3698d-9cab-40b1-9b25-6e77837da603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40229
37636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4022937636
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.675834687
Short name T521
Test name
Test status
Simulation time 1182084993 ps
CPU time 25.72 seconds
Started Jul 14 05:11:26 PM PDT 24
Finished Jul 14 05:11:52 PM PDT 24
Peak memory 249164 kb
Host smart-2f5ac071-aaeb-4b17-bd22-df4ec1e0f281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67583
4687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.675834687
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2040338323
Short name T494
Test name
Test status
Simulation time 1813295552 ps
CPU time 56.86 seconds
Started Jul 14 05:11:22 PM PDT 24
Finished Jul 14 05:12:19 PM PDT 24
Peak memory 257328 kb
Host smart-f79a34f1-670f-46fa-9c65-f3d0fe0b372e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20403
38323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2040338323
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3980833696
Short name T252
Test name
Test status
Simulation time 813531270050 ps
CPU time 2662.08 seconds
Started Jul 14 05:11:25 PM PDT 24
Finished Jul 14 05:55:48 PM PDT 24
Peak memory 298516 kb
Host smart-73bc46cc-8add-486c-aff7-1b52ad694fb8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980833696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3980833696
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1160416448
Short name T181
Test name
Test status
Simulation time 148608140554 ps
CPU time 4005.14 seconds
Started Jul 14 05:11:27 PM PDT 24
Finished Jul 14 06:18:13 PM PDT 24
Peak memory 331112 kb
Host smart-79511e69-a83f-468e-b2f6-3450dd2e09ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160416448 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1160416448
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2933658275
Short name T548
Test name
Test status
Simulation time 6078124519 ps
CPU time 827.93 seconds
Started Jul 14 05:11:33 PM PDT 24
Finished Jul 14 05:25:21 PM PDT 24
Peak memory 272908 kb
Host smart-e2bb487f-dd97-4ebd-9992-188bb67bba8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933658275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2933658275
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.4055521298
Short name T453
Test name
Test status
Simulation time 4991816839 ps
CPU time 72.53 seconds
Started Jul 14 05:11:36 PM PDT 24
Finished Jul 14 05:12:48 PM PDT 24
Peak memory 256944 kb
Host smart-e32ebf8e-4a72-4b84-882a-9b8ba75e093c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40555
21298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.4055521298
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3348945113
Short name T606
Test name
Test status
Simulation time 12221663584 ps
CPU time 40.02 seconds
Started Jul 14 05:11:33 PM PDT 24
Finished Jul 14 05:12:14 PM PDT 24
Peak memory 257316 kb
Host smart-b044c7c0-1d42-4004-92bb-f3e7c8e575c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33489
45113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3348945113
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1725955668
Short name T603
Test name
Test status
Simulation time 60498553966 ps
CPU time 1207.64 seconds
Started Jul 14 05:11:43 PM PDT 24
Finished Jul 14 05:31:52 PM PDT 24
Peak memory 281960 kb
Host smart-a5198d35-4a78-4132-8892-e54c4fb7a07c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725955668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1725955668
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1350899587
Short name T699
Test name
Test status
Simulation time 11747149003 ps
CPU time 1093.5 seconds
Started Jul 14 05:11:44 PM PDT 24
Finished Jul 14 05:29:58 PM PDT 24
Peak memory 289908 kb
Host smart-b2602a5b-e6fe-4355-9242-8fbf28de17de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350899587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1350899587
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.4244988102
Short name T444
Test name
Test status
Simulation time 3132396170 ps
CPU time 133.71 seconds
Started Jul 14 05:11:31 PM PDT 24
Finished Jul 14 05:13:45 PM PDT 24
Peak memory 256276 kb
Host smart-6bba35a5-db4a-4671-a4e2-8e18c39d09a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244988102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.4244988102
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.859356613
Short name T435
Test name
Test status
Simulation time 965878653 ps
CPU time 56.22 seconds
Started Jul 14 05:11:32 PM PDT 24
Finished Jul 14 05:12:28 PM PDT 24
Peak memory 256704 kb
Host smart-379e1b31-353c-4133-9fd9-6c445ce8f0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85935
6613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.859356613
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.362309901
Short name T615
Test name
Test status
Simulation time 1887318974 ps
CPU time 21.86 seconds
Started Jul 14 05:11:32 PM PDT 24
Finished Jul 14 05:11:54 PM PDT 24
Peak memory 248372 kb
Host smart-f872f1bf-6fd1-4b79-bf99-5fcef0f7f9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36230
9901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.362309901
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.4246398767
Short name T248
Test name
Test status
Simulation time 1639152729 ps
CPU time 44.4 seconds
Started Jul 14 05:11:33 PM PDT 24
Finished Jul 14 05:12:18 PM PDT 24
Peak memory 248588 kb
Host smart-7a1c4b4b-12b8-4eb2-9748-56d1d56d830f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42463
98767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.4246398767
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1217170701
Short name T500
Test name
Test status
Simulation time 1807756262 ps
CPU time 19.24 seconds
Started Jul 14 05:11:34 PM PDT 24
Finished Jul 14 05:11:54 PM PDT 24
Peak memory 256704 kb
Host smart-c07e744e-c2aa-403c-b9c3-9f0d2bdbcd71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12171
70701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1217170701
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3635693727
Short name T7
Test name
Test status
Simulation time 161923318290 ps
CPU time 1403 seconds
Started Jul 14 05:11:44 PM PDT 24
Finished Jul 14 05:35:07 PM PDT 24
Peak memory 273804 kb
Host smart-986b4133-bef7-4d52-840d-3afd6b64a474
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635693727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3635693727
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3033219087
Short name T581
Test name
Test status
Simulation time 31785677959 ps
CPU time 2181.76 seconds
Started Jul 14 05:11:48 PM PDT 24
Finished Jul 14 05:48:10 PM PDT 24
Peak memory 289956 kb
Host smart-53cb2a3b-bcda-4d49-8e85-751f2d3d26df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033219087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3033219087
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.413805909
Short name T459
Test name
Test status
Simulation time 45592828 ps
CPU time 5.21 seconds
Started Jul 14 05:11:44 PM PDT 24
Finished Jul 14 05:11:50 PM PDT 24
Peak memory 252160 kb
Host smart-3aaf0f84-18f0-456e-a2bd-8ae7d90f4ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41380
5909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.413805909
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2364462838
Short name T490
Test name
Test status
Simulation time 139962559 ps
CPU time 8.38 seconds
Started Jul 14 05:11:44 PM PDT 24
Finished Jul 14 05:11:53 PM PDT 24
Peak memory 254136 kb
Host smart-7bf54504-0e43-4393-af2a-7ef486102257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23644
62838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2364462838
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.933060636
Short name T567
Test name
Test status
Simulation time 314278825757 ps
CPU time 2081.95 seconds
Started Jul 14 05:11:48 PM PDT 24
Finished Jul 14 05:46:30 PM PDT 24
Peak memory 289292 kb
Host smart-1c037efc-05d5-4b20-b028-3d818a2df31e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933060636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.933060636
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.4174339292
Short name T400
Test name
Test status
Simulation time 13922718681 ps
CPU time 1497.08 seconds
Started Jul 14 05:11:49 PM PDT 24
Finished Jul 14 05:36:47 PM PDT 24
Peak memory 289548 kb
Host smart-dc145383-1a05-45fc-aa32-953434db4227
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174339292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.4174339292
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2836961350
Short name T571
Test name
Test status
Simulation time 13455455476 ps
CPU time 141.95 seconds
Started Jul 14 05:11:46 PM PDT 24
Finished Jul 14 05:14:08 PM PDT 24
Peak memory 256256 kb
Host smart-d338ccc0-6ff6-45dc-b795-d5ad08e5a6c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836961350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2836961350
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.356536820
Short name T649
Test name
Test status
Simulation time 694723884 ps
CPU time 18.8 seconds
Started Jul 14 05:11:44 PM PDT 24
Finished Jul 14 05:12:04 PM PDT 24
Peak memory 256688 kb
Host smart-37d39175-b228-4adb-8a73-531a511c8383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35653
6820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.356536820
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.4065000461
Short name T593
Test name
Test status
Simulation time 567161068 ps
CPU time 35.49 seconds
Started Jul 14 05:11:44 PM PDT 24
Finished Jul 14 05:12:20 PM PDT 24
Peak memory 255712 kb
Host smart-493ee8ca-0605-4722-b0e5-0ed0ffa486a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40650
00461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4065000461
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2858387934
Short name T54
Test name
Test status
Simulation time 1078326754 ps
CPU time 62.42 seconds
Started Jul 14 05:11:48 PM PDT 24
Finished Jul 14 05:12:51 PM PDT 24
Peak memory 249184 kb
Host smart-df90c008-3d44-4969-8289-8b28dd6d6647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28583
87934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2858387934
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3268759751
Short name T408
Test name
Test status
Simulation time 651531716 ps
CPU time 13.93 seconds
Started Jul 14 05:11:42 PM PDT 24
Finished Jul 14 05:11:57 PM PDT 24
Peak memory 257300 kb
Host smart-18e3829e-7e73-43f1-a69b-a62650b606b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32687
59751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3268759751
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1374680584
Short name T271
Test name
Test status
Simulation time 29942253183 ps
CPU time 1804.29 seconds
Started Jul 14 05:11:50 PM PDT 24
Finished Jul 14 05:41:55 PM PDT 24
Peak memory 298464 kb
Host smart-ad0a36d1-8af0-4162-bd01-8ad4fd0d2c4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374680584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1374680584
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.267601908
Short name T550
Test name
Test status
Simulation time 88436625752 ps
CPU time 7246.36 seconds
Started Jul 14 05:11:49 PM PDT 24
Finished Jul 14 07:12:37 PM PDT 24
Peak memory 338824 kb
Host smart-0d9fea65-3ce5-4f95-a6d3-235b237702b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267601908 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.267601908
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2691132360
Short name T401
Test name
Test status
Simulation time 4288254009 ps
CPU time 445.99 seconds
Started Jul 14 05:12:01 PM PDT 24
Finished Jul 14 05:19:27 PM PDT 24
Peak memory 265748 kb
Host smart-ad097cb5-adc8-437c-a992-fc8cf09ad2fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691132360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2691132360
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3147882711
Short name T539
Test name
Test status
Simulation time 15966982788 ps
CPU time 195.07 seconds
Started Jul 14 05:11:59 PM PDT 24
Finished Jul 14 05:15:14 PM PDT 24
Peak memory 257536 kb
Host smart-f449b60c-9e7b-4df6-b365-c5acfbf22dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31478
82711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3147882711
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3889396787
Short name T673
Test name
Test status
Simulation time 1877344507 ps
CPU time 31.35 seconds
Started Jul 14 05:12:01 PM PDT 24
Finished Jul 14 05:12:33 PM PDT 24
Peak memory 257364 kb
Host smart-cf312975-cfa1-43b4-b0f7-883a4f932630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38893
96787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3889396787
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2017900325
Short name T6
Test name
Test status
Simulation time 58199583040 ps
CPU time 1325.3 seconds
Started Jul 14 05:12:02 PM PDT 24
Finished Jul 14 05:34:08 PM PDT 24
Peak memory 289620 kb
Host smart-7c4f75c6-7766-460a-8999-b053f9889f14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017900325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2017900325
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2168186350
Short name T651
Test name
Test status
Simulation time 19993349183 ps
CPU time 1844.52 seconds
Started Jul 14 05:12:02 PM PDT 24
Finished Jul 14 05:42:47 PM PDT 24
Peak memory 289928 kb
Host smart-13e6a2c5-ca07-4412-b4c4-420d9bfb0834
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168186350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2168186350
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2941479007
Short name T297
Test name
Test status
Simulation time 4622878727 ps
CPU time 190.32 seconds
Started Jul 14 05:12:04 PM PDT 24
Finished Jul 14 05:15:15 PM PDT 24
Peak memory 249280 kb
Host smart-6fedec72-4d19-41fb-908f-31f56724880a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941479007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2941479007
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.294952557
Short name T522
Test name
Test status
Simulation time 610577199 ps
CPU time 34.03 seconds
Started Jul 14 05:12:00 PM PDT 24
Finished Jul 14 05:12:35 PM PDT 24
Peak memory 249192 kb
Host smart-3ddc47ed-3b5d-4a4e-8d05-799737190339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29495
2557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.294952557
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1651293118
Short name T467
Test name
Test status
Simulation time 365769600 ps
CPU time 15.71 seconds
Started Jul 14 05:11:59 PM PDT 24
Finished Jul 14 05:12:15 PM PDT 24
Peak memory 257276 kb
Host smart-5e259cc8-ec0b-4bc9-ba76-820c2541b9ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16512
93118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1651293118
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2580045113
Short name T313
Test name
Test status
Simulation time 243155044 ps
CPU time 8.79 seconds
Started Jul 14 05:12:03 PM PDT 24
Finished Jul 14 05:12:12 PM PDT 24
Peak memory 248588 kb
Host smart-30bd45b7-2af8-40cb-9eb9-e00a7967ab4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25800
45113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2580045113
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2653960968
Short name T515
Test name
Test status
Simulation time 314995843 ps
CPU time 23.32 seconds
Started Jul 14 05:11:48 PM PDT 24
Finished Jul 14 05:12:11 PM PDT 24
Peak memory 256920 kb
Host smart-84e2b01a-99ec-458f-acfc-37e19db474ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26539
60968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2653960968
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3982147249
Short name T42
Test name
Test status
Simulation time 42699793725 ps
CPU time 1532.79 seconds
Started Jul 14 05:12:02 PM PDT 24
Finished Jul 14 05:37:35 PM PDT 24
Peak memory 273844 kb
Host smart-dedf60f9-2dd4-4ae7-980a-1474e9590bf7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982147249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3982147249
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2910658306
Short name T206
Test name
Test status
Simulation time 88043608 ps
CPU time 3.9 seconds
Started Jul 14 05:06:50 PM PDT 24
Finished Jul 14 05:06:55 PM PDT 24
Peak memory 249548 kb
Host smart-3a654192-9483-407c-9558-381abeab6a56
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2910658306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2910658306
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2711007419
Short name T702
Test name
Test status
Simulation time 38940321569 ps
CPU time 1327.8 seconds
Started Jul 14 05:06:48 PM PDT 24
Finished Jul 14 05:28:57 PM PDT 24
Peak memory 273964 kb
Host smart-90dc6a33-cd17-46e4-9e4e-eea7b28a301f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711007419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2711007419
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3659193683
Short name T623
Test name
Test status
Simulation time 294731195 ps
CPU time 14.79 seconds
Started Jul 14 05:06:48 PM PDT 24
Finished Jul 14 05:07:04 PM PDT 24
Peak memory 249164 kb
Host smart-0b77bb7b-23fc-4bca-9372-6cb522bfbfb9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3659193683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3659193683
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.411130350
Short name T626
Test name
Test status
Simulation time 8408573014 ps
CPU time 189.13 seconds
Started Jul 14 05:06:41 PM PDT 24
Finished Jul 14 05:09:52 PM PDT 24
Peak memory 257408 kb
Host smart-eef6248e-fe8f-48bc-b68d-dd93fb830809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41113
0350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.411130350
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3849712924
Short name T352
Test name
Test status
Simulation time 736642673 ps
CPU time 39.87 seconds
Started Jul 14 05:06:40 PM PDT 24
Finished Jul 14 05:07:21 PM PDT 24
Peak memory 256600 kb
Host smart-9da50920-4194-4020-8ffd-8cd493f76981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38497
12924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3849712924
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2250795004
Short name T317
Test name
Test status
Simulation time 30315849960 ps
CPU time 1744.8 seconds
Started Jul 14 05:06:47 PM PDT 24
Finished Jul 14 05:35:53 PM PDT 24
Peak memory 273288 kb
Host smart-04078613-788b-4c64-824b-ea024a0c294d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250795004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2250795004
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2496853750
Short name T694
Test name
Test status
Simulation time 188994988250 ps
CPU time 2912.81 seconds
Started Jul 14 05:06:48 PM PDT 24
Finished Jul 14 05:55:23 PM PDT 24
Peak memory 289804 kb
Host smart-f1423bc2-4171-4745-ade5-e77f32cdd251
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496853750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2496853750
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.348131481
Short name T293
Test name
Test status
Simulation time 135889431839 ps
CPU time 484.22 seconds
Started Jul 14 05:06:51 PM PDT 24
Finished Jul 14 05:14:56 PM PDT 24
Peak memory 249088 kb
Host smart-d0ebcb2d-1e1d-4ac6-81e2-1557d8db13ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348131481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.348131481
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.17728227
Short name T716
Test name
Test status
Simulation time 19401873 ps
CPU time 2.98 seconds
Started Jul 14 05:06:41 PM PDT 24
Finished Jul 14 05:06:46 PM PDT 24
Peak memory 249236 kb
Host smart-834071bd-2551-4a2b-ae70-b90127220910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17728
227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.17728227
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.708510323
Short name T221
Test name
Test status
Simulation time 1550494594 ps
CPU time 42.69 seconds
Started Jul 14 05:06:41 PM PDT 24
Finished Jul 14 05:07:25 PM PDT 24
Peak memory 249168 kb
Host smart-b97a46d6-7f58-4f1b-8641-dfe3cbef52bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70851
0323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.708510323
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2716159205
Short name T12
Test name
Test status
Simulation time 1406699729 ps
CPU time 22.35 seconds
Started Jul 14 05:06:47 PM PDT 24
Finished Jul 14 05:07:11 PM PDT 24
Peak memory 270760 kb
Host smart-332cac09-31a5-4b07-b27b-bc08eda2746e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2716159205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2716159205
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3545727642
Short name T75
Test name
Test status
Simulation time 597504412 ps
CPU time 38.77 seconds
Started Jul 14 05:06:45 PM PDT 24
Finished Jul 14 05:07:25 PM PDT 24
Peak memory 256968 kb
Host smart-5e7102dc-d71f-4b70-b9fd-effecc128b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35457
27642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3545727642
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.876793991
Short name T631
Test name
Test status
Simulation time 2751575330 ps
CPU time 45.96 seconds
Started Jul 14 05:06:45 PM PDT 24
Finished Jul 14 05:07:32 PM PDT 24
Peak memory 249276 kb
Host smart-d92e7b82-70f3-47f5-aa32-f9a15d8d50eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87679
3991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.876793991
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2843236081
Short name T486
Test name
Test status
Simulation time 6224359577 ps
CPU time 89.56 seconds
Started Jul 14 05:06:49 PM PDT 24
Finished Jul 14 05:08:19 PM PDT 24
Peak memory 257440 kb
Host smart-4e8dde3a-99af-46db-8e00-99748bf643cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843236081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2843236081
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1430689886
Short name T458
Test name
Test status
Simulation time 24799625540 ps
CPU time 798.31 seconds
Started Jul 14 05:12:15 PM PDT 24
Finished Jul 14 05:25:34 PM PDT 24
Peak memory 273728 kb
Host smart-5d72659c-c4cd-46b5-93a5-0f0fad031f03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430689886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1430689886
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3247717985
Short name T598
Test name
Test status
Simulation time 1516410782 ps
CPU time 89.56 seconds
Started Jul 14 05:12:15 PM PDT 24
Finished Jul 14 05:13:45 PM PDT 24
Peak memory 257440 kb
Host smart-5e8ebf2a-9866-4a3b-b39a-3fa1db389b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32477
17985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3247717985
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3210169019
Short name T383
Test name
Test status
Simulation time 941050168 ps
CPU time 32.58 seconds
Started Jul 14 05:12:10 PM PDT 24
Finished Jul 14 05:12:43 PM PDT 24
Peak memory 249572 kb
Host smart-6fd57c5f-928e-4e18-bdb1-7d6fc2dc49a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32101
69019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3210169019
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.735631948
Short name T319
Test name
Test status
Simulation time 45407721812 ps
CPU time 2476.69 seconds
Started Jul 14 05:12:15 PM PDT 24
Finished Jul 14 05:53:32 PM PDT 24
Peak memory 289944 kb
Host smart-e094bd83-672a-4608-bdd5-0379fdf3afb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735631948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.735631948
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.623491821
Short name T481
Test name
Test status
Simulation time 39054207206 ps
CPU time 2436.99 seconds
Started Jul 14 05:12:17 PM PDT 24
Finished Jul 14 05:52:55 PM PDT 24
Peak memory 290012 kb
Host smart-a4ea066f-cdb2-40b5-be09-e135d77d2cc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623491821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.623491821
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1907861501
Short name T10
Test name
Test status
Simulation time 7015258370 ps
CPU time 311.41 seconds
Started Jul 14 05:12:15 PM PDT 24
Finished Jul 14 05:17:27 PM PDT 24
Peak memory 249336 kb
Host smart-6804e092-cf83-431b-9e2c-55937394cbd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907861501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1907861501
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3825883151
Short name T525
Test name
Test status
Simulation time 1507265203 ps
CPU time 24.98 seconds
Started Jul 14 05:12:09 PM PDT 24
Finished Jul 14 05:12:34 PM PDT 24
Peak memory 255764 kb
Host smart-3cc31ac4-b945-4173-ae05-b20170aa6a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38258
83151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3825883151
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.4072178727
Short name T469
Test name
Test status
Simulation time 2772938952 ps
CPU time 66.24 seconds
Started Jul 14 05:12:09 PM PDT 24
Finished Jul 14 05:13:16 PM PDT 24
Peak memory 257500 kb
Host smart-a2d1c98c-7d06-4540-9d31-61beb84b3ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40721
78727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.4072178727
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1657436697
Short name T715
Test name
Test status
Simulation time 199759962 ps
CPU time 11.37 seconds
Started Jul 14 05:12:16 PM PDT 24
Finished Jul 14 05:12:28 PM PDT 24
Peak memory 256468 kb
Host smart-5faf1221-2c0e-4880-84b8-5b10ccb1aeac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16574
36697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1657436697
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.835098828
Short name T457
Test name
Test status
Simulation time 3085157615 ps
CPU time 41.62 seconds
Started Jul 14 05:12:03 PM PDT 24
Finished Jul 14 05:12:45 PM PDT 24
Peak memory 257356 kb
Host smart-a6dd06d1-810b-4d3e-a289-b33d46754699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83509
8828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.835098828
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.542499373
Short name T484
Test name
Test status
Simulation time 17513814618 ps
CPU time 292.13 seconds
Started Jul 14 05:12:17 PM PDT 24
Finished Jul 14 05:17:09 PM PDT 24
Peak memory 257372 kb
Host smart-50cb6b6e-4963-4d71-a589-b31904589b54
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542499373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.542499373
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1423274921
Short name T585
Test name
Test status
Simulation time 27532404957 ps
CPU time 1916.89 seconds
Started Jul 14 05:12:26 PM PDT 24
Finished Jul 14 05:44:23 PM PDT 24
Peak memory 285792 kb
Host smart-66159de5-f2c9-4b36-a7c2-1782c238dd47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423274921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1423274921
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2220105401
Short name T618
Test name
Test status
Simulation time 1751553798 ps
CPU time 58.44 seconds
Started Jul 14 05:12:18 PM PDT 24
Finished Jul 14 05:13:17 PM PDT 24
Peak memory 256880 kb
Host smart-1439f77e-0004-4032-936e-957b19b9ce2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22201
05401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2220105401
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1444290758
Short name T430
Test name
Test status
Simulation time 1661053238 ps
CPU time 24.42 seconds
Started Jul 14 05:12:19 PM PDT 24
Finished Jul 14 05:12:43 PM PDT 24
Peak memory 249268 kb
Host smart-a04bd723-1019-4b59-a573-97a6d2eb5718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14442
90758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1444290758
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.654999586
Short name T322
Test name
Test status
Simulation time 41155356364 ps
CPU time 2521.38 seconds
Started Jul 14 05:12:29 PM PDT 24
Finished Jul 14 05:54:31 PM PDT 24
Peak memory 289540 kb
Host smart-ea68d0f9-1b95-445f-9489-7a718790ee4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654999586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.654999586
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2591447708
Short name T14
Test name
Test status
Simulation time 284411441507 ps
CPU time 2863.61 seconds
Started Jul 14 05:12:37 PM PDT 24
Finished Jul 14 06:00:22 PM PDT 24
Peak memory 285200 kb
Host smart-da2d9895-9543-4719-a583-a357e6f85b4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591447708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2591447708
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.688057046
Short name T657
Test name
Test status
Simulation time 36084999372 ps
CPU time 372.96 seconds
Started Jul 14 05:12:26 PM PDT 24
Finished Jul 14 05:18:39 PM PDT 24
Peak memory 249248 kb
Host smart-1cce980a-1a73-4392-8e8a-adc674ac69e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688057046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.688057046
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.4121153852
Short name T705
Test name
Test status
Simulation time 586727662 ps
CPU time 10.87 seconds
Started Jul 14 05:12:16 PM PDT 24
Finished Jul 14 05:12:28 PM PDT 24
Peak memory 252968 kb
Host smart-79181957-d00d-4410-997b-c01abc2ce6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41211
53852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.4121153852
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3578987312
Short name T601
Test name
Test status
Simulation time 237858917 ps
CPU time 19.59 seconds
Started Jul 14 05:12:19 PM PDT 24
Finished Jul 14 05:12:39 PM PDT 24
Peak memory 249184 kb
Host smart-c6ac53c3-c7b0-4293-984e-fd2db5c20325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35789
87312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3578987312
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3778130279
Short name T381
Test name
Test status
Simulation time 1136014270 ps
CPU time 71.18 seconds
Started Jul 14 05:12:20 PM PDT 24
Finished Jul 14 05:13:32 PM PDT 24
Peak memory 256856 kb
Host smart-61ae27aa-985b-4a30-b299-43f2fb9c5adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37781
30279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3778130279
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2487985198
Short name T31
Test name
Test status
Simulation time 856841878 ps
CPU time 15.72 seconds
Started Jul 14 05:12:15 PM PDT 24
Finished Jul 14 05:12:31 PM PDT 24
Peak memory 249568 kb
Host smart-e0ce6f92-b4a9-4b46-920c-8f2381aa79b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24879
85198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2487985198
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1718721741
Short name T48
Test name
Test status
Simulation time 210390298853 ps
CPU time 3313.86 seconds
Started Jul 14 05:12:29 PM PDT 24
Finished Jul 14 06:07:43 PM PDT 24
Peak memory 289832 kb
Host smart-88f68163-611b-4af4-8883-19dbcb99e259
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718721741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1718721741
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.666082041
Short name T637
Test name
Test status
Simulation time 37341671164 ps
CPU time 2182.49 seconds
Started Jul 14 05:12:37 PM PDT 24
Finished Jul 14 05:49:01 PM PDT 24
Peak memory 282808 kb
Host smart-42a916c3-9086-47bf-bad8-7b7c5631890f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666082041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.666082041
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2894063224
Short name T646
Test name
Test status
Simulation time 18911045919 ps
CPU time 288.82 seconds
Started Jul 14 05:12:37 PM PDT 24
Finished Jul 14 05:17:27 PM PDT 24
Peak memory 257416 kb
Host smart-997bbff3-1381-477b-a1a9-dd91a5189afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28940
63224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2894063224
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2417646472
Short name T1
Test name
Test status
Simulation time 676127593 ps
CPU time 21.43 seconds
Started Jul 14 05:12:28 PM PDT 24
Finished Jul 14 05:12:50 PM PDT 24
Peak memory 256916 kb
Host smart-7ded364e-5220-4a3e-8025-adbebd1453b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24176
46472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2417646472
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2924425568
Short name T498
Test name
Test status
Simulation time 9749230967 ps
CPU time 691.61 seconds
Started Jul 14 05:12:36 PM PDT 24
Finished Jul 14 05:24:08 PM PDT 24
Peak memory 273060 kb
Host smart-ce64c46d-ca10-4680-8327-cfa21bd019ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924425568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2924425568
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3576342551
Short name T281
Test name
Test status
Simulation time 31026683967 ps
CPU time 1077.61 seconds
Started Jul 14 05:12:35 PM PDT 24
Finished Jul 14 05:30:34 PM PDT 24
Peak memory 286760 kb
Host smart-cf5980b4-e841-46f4-8500-6f58ca81e5fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576342551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3576342551
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2158700414
Short name T289
Test name
Test status
Simulation time 47785670842 ps
CPU time 444.18 seconds
Started Jul 14 05:12:35 PM PDT 24
Finished Jul 14 05:20:00 PM PDT 24
Peak memory 249332 kb
Host smart-2c0ba2a2-83b0-4e15-b401-fe4d7cbb56d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158700414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2158700414
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3821773087
Short name T614
Test name
Test status
Simulation time 176643204 ps
CPU time 20.65 seconds
Started Jul 14 05:12:28 PM PDT 24
Finished Jul 14 05:12:49 PM PDT 24
Peak memory 256644 kb
Host smart-e0cdd486-ec7b-4ae5-9cc4-32d941f200c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38217
73087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3821773087
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.190643626
Short name T403
Test name
Test status
Simulation time 225283587 ps
CPU time 17.27 seconds
Started Jul 14 05:12:37 PM PDT 24
Finished Jul 14 05:12:55 PM PDT 24
Peak memory 254876 kb
Host smart-77de3c17-d9bb-448f-8708-757e7a5c08b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19064
3626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.190643626
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2924888368
Short name T242
Test name
Test status
Simulation time 1028246719 ps
CPU time 25.24 seconds
Started Jul 14 05:12:29 PM PDT 24
Finished Jul 14 05:12:55 PM PDT 24
Peak memory 249200 kb
Host smart-08c54517-7718-4f98-b54a-bf1b465e5e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29248
88368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2924888368
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.393407743
Short name T38
Test name
Test status
Simulation time 3046958199 ps
CPU time 45.44 seconds
Started Jul 14 05:12:37 PM PDT 24
Finished Jul 14 05:13:24 PM PDT 24
Peak memory 249252 kb
Host smart-7d58b366-ca79-4481-bc71-a87dd4cd0235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39340
7743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.393407743
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.3441880162
Short name T691
Test name
Test status
Simulation time 539357631428 ps
CPU time 5333.54 seconds
Started Jul 14 05:12:37 PM PDT 24
Finished Jul 14 06:41:32 PM PDT 24
Peak memory 321948 kb
Host smart-e15dfd63-6b24-4320-a898-17fa3c8c75e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441880162 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.3441880162
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2775489314
Short name T410
Test name
Test status
Simulation time 50258373398 ps
CPU time 2863.39 seconds
Started Jul 14 05:12:41 PM PDT 24
Finished Jul 14 06:00:25 PM PDT 24
Peak memory 289764 kb
Host smart-1e3758cf-c768-46ac-86b9-433a9eb77810
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775489314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2775489314
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1605615946
Short name T466
Test name
Test status
Simulation time 17686994798 ps
CPU time 297.85 seconds
Started Jul 14 05:12:35 PM PDT 24
Finished Jul 14 05:17:34 PM PDT 24
Peak memory 257568 kb
Host smart-359ef97d-e7d4-4e04-9a4b-f97fe00fa79f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16056
15946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1605615946
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.638307417
Short name T556
Test name
Test status
Simulation time 325474552 ps
CPU time 23.33 seconds
Started Jul 14 05:12:36 PM PDT 24
Finished Jul 14 05:13:01 PM PDT 24
Peak memory 249132 kb
Host smart-0bab0fa1-bbb0-42a0-a9ba-11b2df94e94e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63830
7417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.638307417
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3096016247
Short name T552
Test name
Test status
Simulation time 27285112476 ps
CPU time 1606.69 seconds
Started Jul 14 05:12:41 PM PDT 24
Finished Jul 14 05:39:28 PM PDT 24
Peak memory 289752 kb
Host smart-4c78dc56-7aba-4b28-9228-622b14abdc4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096016247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3096016247
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2145755741
Short name T310
Test name
Test status
Simulation time 24817642026 ps
CPU time 534.81 seconds
Started Jul 14 05:12:39 PM PDT 24
Finished Jul 14 05:21:35 PM PDT 24
Peak memory 256400 kb
Host smart-36b3fb91-45b1-4ca1-9515-21e495ba6f00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145755741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2145755741
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.4241378516
Short name T580
Test name
Test status
Simulation time 575441922 ps
CPU time 16.66 seconds
Started Jul 14 05:12:36 PM PDT 24
Finished Jul 14 05:12:53 PM PDT 24
Peak memory 256540 kb
Host smart-1cf703fc-7e28-4b89-9173-970059f9ed45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42413
78516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.4241378516
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3261124252
Short name T711
Test name
Test status
Simulation time 1278259573 ps
CPU time 21.95 seconds
Started Jul 14 05:12:36 PM PDT 24
Finished Jul 14 05:12:59 PM PDT 24
Peak memory 248684 kb
Host smart-255597d9-c1a9-4509-9b46-cf3cef95dfa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32611
24252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3261124252
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2999040212
Short name T533
Test name
Test status
Simulation time 2069911822 ps
CPU time 23.03 seconds
Started Jul 14 05:12:41 PM PDT 24
Finished Jul 14 05:13:05 PM PDT 24
Peak memory 256576 kb
Host smart-d9be23a5-c7a3-488a-a962-6cde165e7ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29990
40212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2999040212
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2145610787
Short name T596
Test name
Test status
Simulation time 1274060541 ps
CPU time 27.67 seconds
Started Jul 14 05:12:37 PM PDT 24
Finished Jul 14 05:13:06 PM PDT 24
Peak memory 249092 kb
Host smart-5408db03-4b9a-42f0-a934-b4982e13b5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21456
10787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2145610787
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.4012139592
Short name T76
Test name
Test status
Simulation time 40877665973 ps
CPU time 2684.55 seconds
Started Jul 14 05:12:49 PM PDT 24
Finished Jul 14 05:57:34 PM PDT 24
Peak memory 290140 kb
Host smart-278b1bab-85b4-4f4d-8225-c66079907d8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012139592 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.4012139592
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.589532492
Short name T259
Test name
Test status
Simulation time 641840847949 ps
CPU time 2974.84 seconds
Started Jul 14 05:12:47 PM PDT 24
Finished Jul 14 06:02:23 PM PDT 24
Peak memory 284676 kb
Host smart-5bf3c0bf-a6de-44f0-bd0b-f6674b85ce20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589532492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.589532492
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1596390981
Short name T474
Test name
Test status
Simulation time 1074240797 ps
CPU time 61.12 seconds
Started Jul 14 05:12:49 PM PDT 24
Finished Jul 14 05:13:50 PM PDT 24
Peak memory 256944 kb
Host smart-dc331788-7e9a-48df-ad64-1037c0158021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15963
90981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1596390981
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3394265642
Short name T431
Test name
Test status
Simulation time 2577212852 ps
CPU time 77.06 seconds
Started Jul 14 05:12:48 PM PDT 24
Finished Jul 14 05:14:06 PM PDT 24
Peak memory 249308 kb
Host smart-208731ed-0f55-48a2-954d-91597f4ddf22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33942
65642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3394265642
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4273946249
Short name T609
Test name
Test status
Simulation time 55226789664 ps
CPU time 1345.32 seconds
Started Jul 14 05:12:52 PM PDT 24
Finished Jul 14 05:35:18 PM PDT 24
Peak memory 286952 kb
Host smart-58d501db-dda5-4608-83d2-0fe429a340ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273946249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4273946249
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2932309032
Short name T547
Test name
Test status
Simulation time 432463472 ps
CPU time 45.72 seconds
Started Jul 14 05:12:49 PM PDT 24
Finished Jul 14 05:13:35 PM PDT 24
Peak memory 257360 kb
Host smart-f59d24a5-6010-4b9a-8699-5311790832a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29323
09032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2932309032
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1961669647
Short name T703
Test name
Test status
Simulation time 165103572 ps
CPU time 4.5 seconds
Started Jul 14 05:12:50 PM PDT 24
Finished Jul 14 05:12:55 PM PDT 24
Peak memory 240472 kb
Host smart-a88efb3b-c5e0-40f8-90ff-5a2a4523f204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19616
69647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1961669647
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1252763734
Short name T402
Test name
Test status
Simulation time 1893507242 ps
CPU time 30.12 seconds
Started Jul 14 05:12:49 PM PDT 24
Finished Jul 14 05:13:20 PM PDT 24
Peak memory 256852 kb
Host smart-9b237a24-8190-4af4-bfbc-3095aba3637e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12527
63734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1252763734
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1883841017
Short name T65
Test name
Test status
Simulation time 895256483 ps
CPU time 67.39 seconds
Started Jul 14 05:12:48 PM PDT 24
Finished Jul 14 05:13:56 PM PDT 24
Peak memory 249248 kb
Host smart-dc409ef6-a1d6-440e-a2c5-321264de0b87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18838
41017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1883841017
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3862368378
Short name T47
Test name
Test status
Simulation time 71810228810 ps
CPU time 2033.62 seconds
Started Jul 14 05:13:01 PM PDT 24
Finished Jul 14 05:46:56 PM PDT 24
Peak memory 303388 kb
Host smart-26c89684-7c25-41cd-b0f4-9d9b0bd17ff2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862368378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3862368378
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2068261075
Short name T643
Test name
Test status
Simulation time 155717950304 ps
CPU time 2340.46 seconds
Started Jul 14 05:13:00 PM PDT 24
Finished Jul 14 05:52:02 PM PDT 24
Peak memory 289544 kb
Host smart-5478a89d-69e4-4cde-800a-ad5b837ad919
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068261075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2068261075
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.81052169
Short name T34
Test name
Test status
Simulation time 1548145985 ps
CPU time 156.54 seconds
Started Jul 14 05:13:01 PM PDT 24
Finished Jul 14 05:15:38 PM PDT 24
Peak memory 257336 kb
Host smart-469e4cd2-b438-4a0a-9aec-cff1800d5aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81052
169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.81052169
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2072442764
Short name T590
Test name
Test status
Simulation time 1655817928 ps
CPU time 49.04 seconds
Started Jul 14 05:12:53 PM PDT 24
Finished Jul 14 05:13:43 PM PDT 24
Peak memory 256876 kb
Host smart-3c801a2d-835b-46d8-ba8d-9bf52ced8097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20724
42764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2072442764
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3024145714
Short name T326
Test name
Test status
Simulation time 224969935993 ps
CPU time 1634.79 seconds
Started Jul 14 05:13:00 PM PDT 24
Finished Jul 14 05:40:16 PM PDT 24
Peak memory 289360 kb
Host smart-a9c2711d-bfc8-433c-a10f-b08cd398661f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024145714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3024145714
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.109349348
Short name T493
Test name
Test status
Simulation time 70110158484 ps
CPU time 1442.05 seconds
Started Jul 14 05:13:06 PM PDT 24
Finished Jul 14 05:37:09 PM PDT 24
Peak memory 289960 kb
Host smart-f079e19c-cf24-4079-bb8f-cd256eb4fc48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109349348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.109349348
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2965964696
Short name T188
Test name
Test status
Simulation time 10333898255 ps
CPU time 422.34 seconds
Started Jul 14 05:13:01 PM PDT 24
Finished Jul 14 05:20:04 PM PDT 24
Peak memory 256636 kb
Host smart-824c08d1-d55c-45c2-90aa-e196908b9a27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965964696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2965964696
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.909115757
Short name T516
Test name
Test status
Simulation time 2981633659 ps
CPU time 48.94 seconds
Started Jul 14 05:12:53 PM PDT 24
Finished Jul 14 05:13:43 PM PDT 24
Peak memory 249388 kb
Host smart-b12273a2-8434-4984-907d-d7b073512502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90911
5757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.909115757
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1904452302
Short name T218
Test name
Test status
Simulation time 1493482141 ps
CPU time 24.11 seconds
Started Jul 14 05:12:54 PM PDT 24
Finished Jul 14 05:13:19 PM PDT 24
Peak memory 255720 kb
Host smart-3c65cf28-3c7a-443f-a6ac-ecc0dba55a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19044
52302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1904452302
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.810785332
Short name T270
Test name
Test status
Simulation time 766369211 ps
CPU time 42.21 seconds
Started Jul 14 05:12:53 PM PDT 24
Finished Jul 14 05:13:36 PM PDT 24
Peak memory 249760 kb
Host smart-48dd4009-9a26-477d-b80b-c91fab318faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81078
5332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.810785332
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1657697849
Short name T365
Test name
Test status
Simulation time 1388054014 ps
CPU time 29.38 seconds
Started Jul 14 05:13:01 PM PDT 24
Finished Jul 14 05:13:31 PM PDT 24
Peak memory 257296 kb
Host smart-3d6bcdcf-ee08-4e38-a7d9-21d68eb1cf8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16576
97849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1657697849
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2608861833
Short name T19
Test name
Test status
Simulation time 233359110640 ps
CPU time 2216.68 seconds
Started Jul 14 05:13:07 PM PDT 24
Finished Jul 14 05:50:04 PM PDT 24
Peak memory 287456 kb
Host smart-c2c60545-b163-405c-b4c5-fa6d80c4451d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608861833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2608861833
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1418075317
Short name T214
Test name
Test status
Simulation time 16446193568 ps
CPU time 1504.41 seconds
Started Jul 14 05:13:15 PM PDT 24
Finished Jul 14 05:38:19 PM PDT 24
Peak memory 289916 kb
Host smart-50ed8f64-0419-473b-90e0-67b0458cb8f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418075317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1418075317
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1826379195
Short name T377
Test name
Test status
Simulation time 7236926505 ps
CPU time 164.19 seconds
Started Jul 14 05:13:12 PM PDT 24
Finished Jul 14 05:15:56 PM PDT 24
Peak memory 257076 kb
Host smart-7aa95f30-b383-4705-b006-676a40973de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18263
79195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1826379195
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.408427793
Short name T409
Test name
Test status
Simulation time 161083532 ps
CPU time 15.19 seconds
Started Jul 14 05:13:11 PM PDT 24
Finished Jul 14 05:13:26 PM PDT 24
Peak memory 256820 kb
Host smart-f8aece5a-4d7d-43e7-ad41-729621400284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40842
7793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.408427793
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.995339429
Short name T283
Test name
Test status
Simulation time 802329221771 ps
CPU time 2984.13 seconds
Started Jul 14 05:13:20 PM PDT 24
Finished Jul 14 06:03:05 PM PDT 24
Peak memory 289676 kb
Host smart-ad6cdb33-2b69-44e8-bf49-335e4fcbf828
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995339429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.995339429
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1939727376
Short name T83
Test name
Test status
Simulation time 28604293509 ps
CPU time 2213.2 seconds
Started Jul 14 05:13:20 PM PDT 24
Finished Jul 14 05:50:14 PM PDT 24
Peak memory 285728 kb
Host smart-a68ba3a4-102b-4e9f-80db-11a672a645b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939727376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1939727376
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2563802148
Short name T304
Test name
Test status
Simulation time 47823541414 ps
CPU time 462.42 seconds
Started Jul 14 05:13:12 PM PDT 24
Finished Jul 14 05:20:55 PM PDT 24
Peak memory 255940 kb
Host smart-10e6c0db-4a97-47de-9602-d623d47dc910
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563802148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2563802148
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2612167315
Short name T666
Test name
Test status
Simulation time 1278424571 ps
CPU time 20.13 seconds
Started Jul 14 05:13:05 PM PDT 24
Finished Jul 14 05:13:26 PM PDT 24
Peak memory 249248 kb
Host smart-bcd8a241-1bb4-41bd-a9e1-ae8671b52a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26121
67315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2612167315
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.502701796
Short name T496
Test name
Test status
Simulation time 781461980 ps
CPU time 49.74 seconds
Started Jul 14 05:13:15 PM PDT 24
Finished Jul 14 05:14:05 PM PDT 24
Peak memory 256692 kb
Host smart-c8c4381d-d4a1-44cd-b5e6-ea0b3cb67045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50270
1796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.502701796
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.695572065
Short name T639
Test name
Test status
Simulation time 160039030 ps
CPU time 12.76 seconds
Started Jul 14 05:13:14 PM PDT 24
Finished Jul 14 05:13:27 PM PDT 24
Peak memory 249192 kb
Host smart-5db5cdbf-55a9-450a-b2ac-115baca4905b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69557
2065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.695572065
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.4066833012
Short name T582
Test name
Test status
Simulation time 7773072700 ps
CPU time 57.89 seconds
Started Jul 14 05:13:05 PM PDT 24
Finished Jul 14 05:14:04 PM PDT 24
Peak memory 257352 kb
Host smart-ae577ebb-1a15-4e6d-8877-fb0004c6e290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40668
33012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.4066833012
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1375080959
Short name T269
Test name
Test status
Simulation time 13347135793 ps
CPU time 169.82 seconds
Started Jul 14 05:13:20 PM PDT 24
Finished Jul 14 05:16:10 PM PDT 24
Peak memory 257496 kb
Host smart-2e3b354e-9a1b-44fa-927d-d81a6d42e04e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375080959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1375080959
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2496534229
Short name T578
Test name
Test status
Simulation time 188309169504 ps
CPU time 2435.48 seconds
Started Jul 14 05:13:31 PM PDT 24
Finished Jul 14 05:54:07 PM PDT 24
Peak memory 285188 kb
Host smart-6725f0f1-3d67-48de-a679-18c4ae54e095
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496534229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2496534229
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1380716359
Short name T366
Test name
Test status
Simulation time 829200747 ps
CPU time 67.03 seconds
Started Jul 14 05:13:24 PM PDT 24
Finished Jul 14 05:14:32 PM PDT 24
Peak memory 256680 kb
Host smart-3856c159-a33f-4130-a54a-e30b21918c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13807
16359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1380716359
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3295386375
Short name T378
Test name
Test status
Simulation time 90100824 ps
CPU time 7.55 seconds
Started Jul 14 05:13:24 PM PDT 24
Finished Jul 14 05:13:32 PM PDT 24
Peak memory 253276 kb
Host smart-bb88d8db-d17d-410e-8f64-7936e5e0061b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32953
86375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3295386375
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2613258568
Short name T321
Test name
Test status
Simulation time 50664405465 ps
CPU time 2737.24 seconds
Started Jul 14 05:13:31 PM PDT 24
Finished Jul 14 05:59:09 PM PDT 24
Peak memory 290244 kb
Host smart-0da7cb9a-da99-4641-b992-3bc6caafa69f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613258568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2613258568
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2181309978
Short name T487
Test name
Test status
Simulation time 212977796694 ps
CPU time 3136.05 seconds
Started Jul 14 05:13:29 PM PDT 24
Finished Jul 14 06:05:46 PM PDT 24
Peak memory 290152 kb
Host smart-10f0eb2a-48a0-4247-be96-586569c66743
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181309978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2181309978
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.481376494
Short name T536
Test name
Test status
Simulation time 747176645 ps
CPU time 45 seconds
Started Jul 14 05:13:23 PM PDT 24
Finished Jul 14 05:14:08 PM PDT 24
Peak memory 257372 kb
Host smart-1dd00a12-2790-477d-92f1-c62dde1f31e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48137
6494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.481376494
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2805313001
Short name T569
Test name
Test status
Simulation time 1402302754 ps
CPU time 25.7 seconds
Started Jul 14 05:13:23 PM PDT 24
Finished Jul 14 05:13:49 PM PDT 24
Peak memory 249244 kb
Host smart-17efb999-bf2e-41db-988f-9fabd3a0299c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28053
13001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2805313001
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.142254221
Short name T244
Test name
Test status
Simulation time 1234184637 ps
CPU time 36.52 seconds
Started Jul 14 05:13:23 PM PDT 24
Finished Jul 14 05:14:00 PM PDT 24
Peak memory 248756 kb
Host smart-13b45bd5-e741-4706-8ee1-9a2927ca7e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14225
4221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.142254221
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3475649081
Short name T641
Test name
Test status
Simulation time 1683469451 ps
CPU time 35.39 seconds
Started Jul 14 05:13:19 PM PDT 24
Finished Jul 14 05:13:55 PM PDT 24
Peak memory 256864 kb
Host smart-75ad86ec-a013-422b-b266-8bdd0db70aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34756
49081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3475649081
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3598530180
Short name T249
Test name
Test status
Simulation time 85720146214 ps
CPU time 2538.71 seconds
Started Jul 14 05:13:30 PM PDT 24
Finished Jul 14 05:55:49 PM PDT 24
Peak memory 298256 kb
Host smart-6c486bbc-805a-4eb6-83b6-29c9a29a0f8e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598530180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3598530180
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.994157524
Short name T97
Test name
Test status
Simulation time 25974713287 ps
CPU time 1862.51 seconds
Started Jul 14 05:13:32 PM PDT 24
Finished Jul 14 05:44:35 PM PDT 24
Peak memory 282080 kb
Host smart-2c1f3679-ab27-459e-a666-389ed64172e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994157524 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.994157524
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2984993337
Short name T557
Test name
Test status
Simulation time 8221399298 ps
CPU time 1037.21 seconds
Started Jul 14 05:13:42 PM PDT 24
Finished Jul 14 05:31:00 PM PDT 24
Peak memory 282720 kb
Host smart-4e548903-4a2f-47f7-80a6-a84373fa00dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984993337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2984993337
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.771664934
Short name T375
Test name
Test status
Simulation time 1234437379 ps
CPU time 134.35 seconds
Started Jul 14 05:13:43 PM PDT 24
Finished Jul 14 05:15:58 PM PDT 24
Peak memory 256472 kb
Host smart-99d31a8e-99e2-471a-bb82-e1bed95d7df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77166
4934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.771664934
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1852976450
Short name T434
Test name
Test status
Simulation time 850785134 ps
CPU time 56.33 seconds
Started Jul 14 05:13:39 PM PDT 24
Finished Jul 14 05:14:35 PM PDT 24
Peak memory 248804 kb
Host smart-747d4c45-40ca-473d-9a98-2927589bff24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18529
76450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1852976450
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4177695942
Short name T572
Test name
Test status
Simulation time 107683241308 ps
CPU time 1664.05 seconds
Started Jul 14 05:13:52 PM PDT 24
Finished Jul 14 05:41:36 PM PDT 24
Peak memory 273148 kb
Host smart-591c33d4-702b-4c1b-9855-5370c8626e11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177695942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4177695942
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3616831766
Short name T407
Test name
Test status
Simulation time 35143445700 ps
CPU time 1301.8 seconds
Started Jul 14 05:13:59 PM PDT 24
Finished Jul 14 05:35:41 PM PDT 24
Peak memory 273768 kb
Host smart-20b183aa-ee96-4bd9-baec-ca05edb3f766
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616831766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3616831766
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2351525280
Short name T291
Test name
Test status
Simulation time 39863012255 ps
CPU time 428.82 seconds
Started Jul 14 05:13:50 PM PDT 24
Finished Jul 14 05:20:59 PM PDT 24
Peak memory 249284 kb
Host smart-61245cc1-e7ce-4b32-bbd5-538b8efcc01b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351525280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2351525280
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2143362369
Short name T348
Test name
Test status
Simulation time 371384328 ps
CPU time 30.1 seconds
Started Jul 14 05:13:35 PM PDT 24
Finished Jul 14 05:14:06 PM PDT 24
Peak memory 249204 kb
Host smart-692a4fba-8e85-4655-9770-00760d321dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21433
62369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2143362369
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2804550439
Short name T698
Test name
Test status
Simulation time 199252959 ps
CPU time 14.05 seconds
Started Jul 14 05:13:38 PM PDT 24
Finished Jul 14 05:13:53 PM PDT 24
Peak memory 248580 kb
Host smart-0891f9e5-a9f0-488c-8d6f-c9f829628e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28045
50439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2804550439
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.786348526
Short name T46
Test name
Test status
Simulation time 797745295 ps
CPU time 34.84 seconds
Started Jul 14 05:13:42 PM PDT 24
Finished Jul 14 05:14:17 PM PDT 24
Peak memory 255960 kb
Host smart-51fcc1b1-d5fd-4b86-b18d-42ba031f0129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78634
8526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.786348526
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3696123198
Short name T475
Test name
Test status
Simulation time 497774545 ps
CPU time 26.3 seconds
Started Jul 14 05:13:38 PM PDT 24
Finished Jul 14 05:14:05 PM PDT 24
Peak memory 256016 kb
Host smart-2a5a5eb7-8cbb-44e5-95ed-74223a48891e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36961
23198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3696123198
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.859677984
Short name T106
Test name
Test status
Simulation time 125733014230 ps
CPU time 3838.15 seconds
Started Jul 14 05:13:57 PM PDT 24
Finished Jul 14 06:17:56 PM PDT 24
Peak memory 331300 kb
Host smart-523a877d-7288-4055-9665-8417a759582f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859677984 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.859677984
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1929344712
Short name T395
Test name
Test status
Simulation time 2618680692 ps
CPU time 126.34 seconds
Started Jul 14 05:13:58 PM PDT 24
Finished Jul 14 05:16:04 PM PDT 24
Peak memory 257028 kb
Host smart-c8a8d7e6-1bde-4ed0-a1cc-a3519dbd7d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19293
44712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1929344712
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2518320418
Short name T665
Test name
Test status
Simulation time 6956837199 ps
CPU time 43.97 seconds
Started Jul 14 05:13:58 PM PDT 24
Finished Jul 14 05:14:42 PM PDT 24
Peak memory 257388 kb
Host smart-793413b8-009f-4081-bc36-b2daacce0691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25183
20418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2518320418
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1484869271
Short name T332
Test name
Test status
Simulation time 226416024362 ps
CPU time 1875.02 seconds
Started Jul 14 05:14:04 PM PDT 24
Finished Jul 14 05:45:20 PM PDT 24
Peak memory 282372 kb
Host smart-d08b5518-9679-4585-be2e-e7c464797205
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484869271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1484869271
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.4260315664
Short name T85
Test name
Test status
Simulation time 68993171297 ps
CPU time 1144.24 seconds
Started Jul 14 05:14:03 PM PDT 24
Finished Jul 14 05:33:08 PM PDT 24
Peak memory 266588 kb
Host smart-af318fe4-2b26-4ada-ab72-4513f378622b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260315664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.4260315664
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2551934967
Short name T265
Test name
Test status
Simulation time 4302159001 ps
CPU time 61.95 seconds
Started Jul 14 05:13:59 PM PDT 24
Finished Jul 14 05:15:01 PM PDT 24
Peak memory 256708 kb
Host smart-69c708af-62e1-47ae-a694-3c5248547e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25519
34967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2551934967
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1124992880
Short name T58
Test name
Test status
Simulation time 674299358 ps
CPU time 18.21 seconds
Started Jul 14 05:14:01 PM PDT 24
Finished Jul 14 05:14:19 PM PDT 24
Peak memory 248952 kb
Host smart-9544332e-caec-40de-96fa-411cb9b55bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11249
92880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1124992880
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.4230412679
Short name T246
Test name
Test status
Simulation time 247820425 ps
CPU time 46.11 seconds
Started Jul 14 05:14:00 PM PDT 24
Finished Jul 14 05:14:46 PM PDT 24
Peak memory 249040 kb
Host smart-ae5cb2fb-ce19-4165-9b55-376ce6e618ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42304
12679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.4230412679
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1636892896
Short name T387
Test name
Test status
Simulation time 697192184 ps
CPU time 18.19 seconds
Started Jul 14 05:13:57 PM PDT 24
Finished Jul 14 05:14:16 PM PDT 24
Peak memory 257348 kb
Host smart-1baa0351-08c3-4f9b-bb86-f01ec15dfcf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16368
92896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1636892896
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1688172151
Short name T51
Test name
Test status
Simulation time 55792824363 ps
CPU time 1488.88 seconds
Started Jul 14 05:14:02 PM PDT 24
Finished Jul 14 05:38:51 PM PDT 24
Peak memory 290256 kb
Host smart-7807c0c5-3e0c-4b73-8538-293c2e9853fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688172151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1688172151
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3596035386
Short name T198
Test name
Test status
Simulation time 14923690 ps
CPU time 2.74 seconds
Started Jul 14 05:06:56 PM PDT 24
Finished Jul 14 05:06:59 PM PDT 24
Peak memory 249428 kb
Host smart-3833289d-9f47-4750-bf6a-f911f59f3b79
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3596035386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3596035386
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1904769670
Short name T560
Test name
Test status
Simulation time 142353027125 ps
CPU time 2587.19 seconds
Started Jul 14 05:06:48 PM PDT 24
Finished Jul 14 05:49:57 PM PDT 24
Peak memory 281952 kb
Host smart-cc973fb1-9b35-4081-8518-036df16d9f2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904769670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1904769670
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.899146726
Short name T416
Test name
Test status
Simulation time 919321113 ps
CPU time 12.94 seconds
Started Jul 14 05:06:54 PM PDT 24
Finished Jul 14 05:07:07 PM PDT 24
Peak memory 249164 kb
Host smart-ee410d36-dd00-4c91-a236-7125777fb31c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=899146726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.899146726
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2640507047
Short name T216
Test name
Test status
Simulation time 22971297548 ps
CPU time 240.44 seconds
Started Jul 14 05:06:50 PM PDT 24
Finished Jul 14 05:10:51 PM PDT 24
Peak memory 257448 kb
Host smart-a196560c-3873-446d-be76-36a8ce94165a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26405
07047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2640507047
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2831822868
Short name T455
Test name
Test status
Simulation time 1584677098 ps
CPU time 33.82 seconds
Started Jul 14 05:06:47 PM PDT 24
Finished Jul 14 05:07:22 PM PDT 24
Peak memory 248652 kb
Host smart-acb3ee88-aef8-43b7-9155-ec8063680034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28318
22868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2831822868
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3887291387
Short name T629
Test name
Test status
Simulation time 41964872371 ps
CPU time 1303.02 seconds
Started Jul 14 05:06:49 PM PDT 24
Finished Jul 14 05:28:33 PM PDT 24
Peak memory 273124 kb
Host smart-1ae7fb05-8ee1-445f-99ce-1a45dc3546c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887291387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3887291387
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3792050241
Short name T262
Test name
Test status
Simulation time 41994317175 ps
CPU time 1938.41 seconds
Started Jul 14 05:07:01 PM PDT 24
Finished Jul 14 05:39:21 PM PDT 24
Peak memory 273812 kb
Host smart-656a05c9-f9e6-4347-a45a-7e8fc98d7213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792050241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3792050241
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2505079085
Short name T674
Test name
Test status
Simulation time 13030399244 ps
CPU time 280.17 seconds
Started Jul 14 05:06:48 PM PDT 24
Finished Jul 14 05:11:29 PM PDT 24
Peak memory 249348 kb
Host smart-540bf6ab-cbdc-47e3-82a4-b30a78935b32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505079085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2505079085
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3664184968
Short name T553
Test name
Test status
Simulation time 356178797 ps
CPU time 6.85 seconds
Started Jul 14 05:06:49 PM PDT 24
Finished Jul 14 05:06:57 PM PDT 24
Peak memory 249128 kb
Host smart-7ebbe27f-ed71-4b11-867c-ad55130790d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36641
84968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3664184968
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.30174285
Short name T71
Test name
Test status
Simulation time 304508597 ps
CPU time 8.46 seconds
Started Jul 14 05:06:47 PM PDT 24
Finished Jul 14 05:06:57 PM PDT 24
Peak memory 249116 kb
Host smart-37904bf5-9a52-48f9-ac78-331f5fa29768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30174
285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.30174285
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2521628036
Short name T11
Test name
Test status
Simulation time 700860110 ps
CPU time 13.33 seconds
Started Jul 14 05:06:55 PM PDT 24
Finished Jul 14 05:07:09 PM PDT 24
Peak memory 271244 kb
Host smart-7a653e53-66ae-41cb-a67e-bdfbab26f59b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2521628036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2521628036
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.283367151
Short name T576
Test name
Test status
Simulation time 2095636140 ps
CPU time 55.43 seconds
Started Jul 14 05:06:47 PM PDT 24
Finished Jul 14 05:07:44 PM PDT 24
Peak memory 256808 kb
Host smart-2a3405da-6965-4fc8-aa5e-69e4d05847df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28336
7151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.283367151
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2693802383
Short name T18
Test name
Test status
Simulation time 382681231 ps
CPU time 29.89 seconds
Started Jul 14 05:06:50 PM PDT 24
Finished Jul 14 05:07:21 PM PDT 24
Peak memory 256476 kb
Host smart-361c7c35-e2a8-4346-b090-c8db8a3425e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26938
02383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2693802383
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3532324254
Short name T193
Test name
Test status
Simulation time 109689013062 ps
CPU time 1169.43 seconds
Started Jul 14 05:06:55 PM PDT 24
Finished Jul 14 05:26:25 PM PDT 24
Peak memory 273168 kb
Host smart-e5ba4eca-7612-47cf-8b08-06a12dd5dba5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532324254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3532324254
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.4076183127
Short name T275
Test name
Test status
Simulation time 112808556233 ps
CPU time 8732.88 seconds
Started Jul 14 05:06:54 PM PDT 24
Finished Jul 14 07:32:29 PM PDT 24
Peak memory 339608 kb
Host smart-1d736d87-529f-476e-a01b-c02aab68f08e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076183127 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.4076183127
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3832114200
Short name T363
Test name
Test status
Simulation time 34196890403 ps
CPU time 2119.19 seconds
Started Jul 14 05:14:08 PM PDT 24
Finished Jul 14 05:49:28 PM PDT 24
Peak memory 273136 kb
Host smart-d98f83e8-2a36-4818-b015-726f20b1d131
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832114200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3832114200
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.533533926
Short name T558
Test name
Test status
Simulation time 1539178367 ps
CPU time 140.98 seconds
Started Jul 14 05:14:12 PM PDT 24
Finished Jul 14 05:16:34 PM PDT 24
Peak memory 257188 kb
Host smart-7f6df7a1-4db6-47c7-becf-c0049c0fd1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53353
3926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.533533926
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1267570360
Short name T675
Test name
Test status
Simulation time 399692451 ps
CPU time 22.31 seconds
Started Jul 14 05:14:09 PM PDT 24
Finished Jul 14 05:14:32 PM PDT 24
Peak memory 249176 kb
Host smart-991e2acf-d2d4-4bab-aaba-21c171ed2e11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12675
70360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1267570360
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2419545501
Short name T492
Test name
Test status
Simulation time 59056962942 ps
CPU time 854.33 seconds
Started Jul 14 05:14:13 PM PDT 24
Finished Jul 14 05:28:27 PM PDT 24
Peak memory 273904 kb
Host smart-ae610d51-7155-4998-99a6-633c28b2faac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419545501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2419545501
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.275469630
Short name T655
Test name
Test status
Simulation time 118810277833 ps
CPU time 1705.54 seconds
Started Jul 14 05:14:19 PM PDT 24
Finished Jul 14 05:42:45 PM PDT 24
Peak memory 269824 kb
Host smart-5b8a4c16-c124-41d3-8eb2-16a3bd3c06a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275469630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.275469630
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2299177362
Short name T305
Test name
Test status
Simulation time 13240277988 ps
CPU time 505.17 seconds
Started Jul 14 05:14:17 PM PDT 24
Finished Jul 14 05:22:43 PM PDT 24
Peak memory 249268 kb
Host smart-cdad0dff-75e4-4eec-820b-ac2c96e74f5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299177362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2299177362
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.4254006298
Short name T369
Test name
Test status
Simulation time 2010425547 ps
CPU time 32.97 seconds
Started Jul 14 05:14:09 PM PDT 24
Finished Jul 14 05:14:42 PM PDT 24
Peak memory 256420 kb
Host smart-e9deaa6e-f6ca-438d-b00c-389670c1b088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42540
06298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.4254006298
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2275332852
Short name T70
Test name
Test status
Simulation time 379561191 ps
CPU time 20.03 seconds
Started Jul 14 05:14:09 PM PDT 24
Finished Jul 14 05:14:30 PM PDT 24
Peak memory 256664 kb
Host smart-1f5268fc-d5fa-41dd-a9ba-8a9db17538a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22753
32852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2275332852
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.974462017
Short name T243
Test name
Test status
Simulation time 1580514213 ps
CPU time 25.96 seconds
Started Jul 14 05:14:08 PM PDT 24
Finished Jul 14 05:14:34 PM PDT 24
Peak memory 249084 kb
Host smart-5e7469d8-4d1a-47a1-a3d2-4832722fd4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97446
2017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.974462017
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3933816756
Short name T441
Test name
Test status
Simulation time 248209027 ps
CPU time 17.15 seconds
Started Jul 14 05:14:02 PM PDT 24
Finished Jul 14 05:14:20 PM PDT 24
Peak memory 255380 kb
Host smart-480efd54-e900-46aa-bf52-3df9b5da99cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39338
16756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3933816756
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2413421568
Short name T624
Test name
Test status
Simulation time 49476279243 ps
CPU time 1427.39 seconds
Started Jul 14 05:14:12 PM PDT 24
Finished Jul 14 05:38:00 PM PDT 24
Peak memory 289920 kb
Host smart-359bdbd4-4a5b-4668-a5c7-7cd138fafa64
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413421568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2413421568
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1541802657
Short name T695
Test name
Test status
Simulation time 290419604732 ps
CPU time 2623.87 seconds
Started Jul 14 05:14:28 PM PDT 24
Finished Jul 14 05:58:12 PM PDT 24
Peak memory 282836 kb
Host smart-e1a9c7f5-c03a-4829-b472-1df621039551
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541802657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1541802657
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.535199067
Short name T465
Test name
Test status
Simulation time 2594074357 ps
CPU time 162.86 seconds
Started Jul 14 05:14:21 PM PDT 24
Finished Jul 14 05:17:04 PM PDT 24
Peak memory 257408 kb
Host smart-e958ee3b-c7fa-48f5-8f87-ce417bbf984e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53519
9067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.535199067
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.526359904
Short name T372
Test name
Test status
Simulation time 354058284 ps
CPU time 20.67 seconds
Started Jul 14 05:14:23 PM PDT 24
Finished Jul 14 05:14:44 PM PDT 24
Peak memory 249756 kb
Host smart-c0ea625e-a9b1-4aa2-aafe-e53f79324787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52635
9904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.526359904
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.286899271
Short name T330
Test name
Test status
Simulation time 39089642990 ps
CPU time 1687.36 seconds
Started Jul 14 05:14:27 PM PDT 24
Finished Jul 14 05:42:35 PM PDT 24
Peak memory 290196 kb
Host smart-327fb44d-231a-48f2-b99a-9b31cddef026
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286899271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.286899271
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2403047641
Short name T445
Test name
Test status
Simulation time 137419052937 ps
CPU time 1629.68 seconds
Started Jul 14 05:14:30 PM PDT 24
Finished Jul 14 05:41:40 PM PDT 24
Peak memory 265680 kb
Host smart-b2fad1f5-f2dd-4f88-8148-6b6017fb232d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403047641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2403047641
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2093855047
Short name T294
Test name
Test status
Simulation time 6271761197 ps
CPU time 236.82 seconds
Started Jul 14 05:14:28 PM PDT 24
Finished Jul 14 05:18:25 PM PDT 24
Peak memory 249320 kb
Host smart-4eea007a-c855-481e-adb0-850b7b430ff6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093855047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2093855047
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1894993545
Short name T418
Test name
Test status
Simulation time 6376855824 ps
CPU time 47.96 seconds
Started Jul 14 05:14:23 PM PDT 24
Finished Jul 14 05:15:11 PM PDT 24
Peak memory 256652 kb
Host smart-780a4104-be13-43b9-a1e4-13bbcb159fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18949
93545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1894993545
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.499329073
Short name T659
Test name
Test status
Simulation time 320616360 ps
CPU time 37.08 seconds
Started Jul 14 05:14:23 PM PDT 24
Finished Jul 14 05:15:00 PM PDT 24
Peak memory 249156 kb
Host smart-2a86b8b0-0ae5-4a6d-a068-d8e697c9002a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49932
9073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.499329073
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.16933535
Short name T358
Test name
Test status
Simulation time 173184432 ps
CPU time 17.05 seconds
Started Jul 14 05:14:21 PM PDT 24
Finished Jul 14 05:14:39 PM PDT 24
Peak memory 257340 kb
Host smart-bb1b79fd-38a2-4924-abde-b31cc04346f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16933
535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.16933535
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3476885591
Short name T105
Test name
Test status
Simulation time 71388649023 ps
CPU time 1921.6 seconds
Started Jul 14 05:14:27 PM PDT 24
Finished Jul 14 05:46:29 PM PDT 24
Peak memory 301356 kb
Host smart-39322d60-8fd9-4c15-a067-287d095f4ca5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476885591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3476885591
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3093782889
Short name T90
Test name
Test status
Simulation time 152845497929 ps
CPU time 2586.5 seconds
Started Jul 14 05:14:45 PM PDT 24
Finished Jul 14 05:57:53 PM PDT 24
Peak memory 282056 kb
Host smart-a388d8f8-3416-4918-b2b8-4072a1f9b19f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093782889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3093782889
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.4110990840
Short name T87
Test name
Test status
Simulation time 15613964372 ps
CPU time 209.64 seconds
Started Jul 14 05:14:44 PM PDT 24
Finished Jul 14 05:18:15 PM PDT 24
Peak memory 256772 kb
Host smart-4ac9bed5-d35f-49e4-861e-83afe0a2b2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41109
90840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4110990840
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.581933426
Short name T423
Test name
Test status
Simulation time 67526744 ps
CPU time 10.24 seconds
Started Jul 14 05:14:43 PM PDT 24
Finished Jul 14 05:14:53 PM PDT 24
Peak memory 249100 kb
Host smart-3824b58a-0a30-4310-9751-29395ced0996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58193
3426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.581933426
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3512943929
Short name T636
Test name
Test status
Simulation time 123263686172 ps
CPU time 1957.85 seconds
Started Jul 14 05:14:49 PM PDT 24
Finished Jul 14 05:47:28 PM PDT 24
Peak memory 273248 kb
Host smart-f9d6994d-20cf-4547-81c2-efe0e79cc036
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512943929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3512943929
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3521565491
Short name T187
Test name
Test status
Simulation time 22425066932 ps
CPU time 1396.82 seconds
Started Jul 14 05:14:47 PM PDT 24
Finished Jul 14 05:38:04 PM PDT 24
Peak memory 273188 kb
Host smart-7a712939-63a1-4bed-864b-0b259efb62b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521565491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3521565491
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.851045324
Short name T653
Test name
Test status
Simulation time 9831762107 ps
CPU time 197.11 seconds
Started Jul 14 05:14:45 PM PDT 24
Finished Jul 14 05:18:02 PM PDT 24
Peak memory 256876 kb
Host smart-a256dd07-c5e5-48a5-a644-6b9e1b5e8aa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851045324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.851045324
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3660508980
Short name T658
Test name
Test status
Simulation time 719169530 ps
CPU time 19.15 seconds
Started Jul 14 05:14:34 PM PDT 24
Finished Jul 14 05:14:54 PM PDT 24
Peak memory 249260 kb
Host smart-ffec7560-103a-49ed-a32c-7a94e01621e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36605
08980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3660508980
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.901888703
Short name T344
Test name
Test status
Simulation time 21238170 ps
CPU time 3.07 seconds
Started Jul 14 05:14:40 PM PDT 24
Finished Jul 14 05:14:44 PM PDT 24
Peak memory 240304 kb
Host smart-009b5b92-6c7d-4c60-92c0-ba5560f39384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90188
8703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.901888703
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.4034820547
Short name T438
Test name
Test status
Simulation time 2470597340 ps
CPU time 49.06 seconds
Started Jul 14 05:14:45 PM PDT 24
Finished Jul 14 05:15:35 PM PDT 24
Peak memory 248776 kb
Host smart-d5a5bacf-d842-4ba1-8e9c-e4d1b45211ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40348
20547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.4034820547
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2549112155
Short name T463
Test name
Test status
Simulation time 2930726299 ps
CPU time 45.83 seconds
Started Jul 14 05:14:37 PM PDT 24
Finished Jul 14 05:15:24 PM PDT 24
Peak memory 257420 kb
Host smart-1a282b37-c06f-421a-b3d6-ac7ec2c36d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25491
12155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2549112155
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3588209487
Short name T272
Test name
Test status
Simulation time 9882536540 ps
CPU time 1172.28 seconds
Started Jul 14 05:14:50 PM PDT 24
Finished Jul 14 05:34:23 PM PDT 24
Peak memory 290200 kb
Host smart-4345f17a-321f-4f91-b3cd-981189547e02
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588209487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3588209487
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.600197665
Short name T109
Test name
Test status
Simulation time 31250099956 ps
CPU time 1791.35 seconds
Started Jul 14 05:14:59 PM PDT 24
Finished Jul 14 05:44:51 PM PDT 24
Peak memory 283524 kb
Host smart-1a93fc92-8119-484d-a66a-f56af0c23815
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600197665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.600197665
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3916662488
Short name T404
Test name
Test status
Simulation time 2245460462 ps
CPU time 177.9 seconds
Started Jul 14 05:14:55 PM PDT 24
Finished Jul 14 05:17:54 PM PDT 24
Peak memory 256948 kb
Host smart-f1015cc1-498e-4b1e-b412-6c75f94e29e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39166
62488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3916662488
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2896472605
Short name T22
Test name
Test status
Simulation time 2176247574 ps
CPU time 35.42 seconds
Started Jul 14 05:14:54 PM PDT 24
Finished Jul 14 05:15:29 PM PDT 24
Peak memory 248892 kb
Host smart-ce5888be-c54f-4dd9-a2ea-58232b2bfae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28964
72605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2896472605
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3437618226
Short name T306
Test name
Test status
Simulation time 117026400922 ps
CPU time 1876.88 seconds
Started Jul 14 05:15:09 PM PDT 24
Finished Jul 14 05:46:26 PM PDT 24
Peak memory 273812 kb
Host smart-b8e620ce-f9b8-47ce-b034-ab4bb715125c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437618226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3437618226
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3398819049
Short name T677
Test name
Test status
Simulation time 48576708442 ps
CPU time 2767.31 seconds
Started Jul 14 05:15:07 PM PDT 24
Finished Jul 14 06:01:15 PM PDT 24
Peak memory 288920 kb
Host smart-806aa9e3-c804-4358-b35a-73bda91bb3f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398819049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3398819049
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2223289296
Short name T619
Test name
Test status
Simulation time 16068728769 ps
CPU time 186.2 seconds
Started Jul 14 05:14:54 PM PDT 24
Finished Jul 14 05:18:01 PM PDT 24
Peak memory 249124 kb
Host smart-9993e9d9-cb69-46d6-aadf-4c38885e5b21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223289296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2223289296
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.421903778
Short name T428
Test name
Test status
Simulation time 900920976 ps
CPU time 50.46 seconds
Started Jul 14 05:14:55 PM PDT 24
Finished Jul 14 05:15:46 PM PDT 24
Peak memory 256716 kb
Host smart-504ed8d2-b6e0-40ca-a14a-43889c737879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42190
3778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.421903778
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.4045390138
Short name T53
Test name
Test status
Simulation time 1354403451 ps
CPU time 83.39 seconds
Started Jul 14 05:14:58 PM PDT 24
Finished Jul 14 05:16:21 PM PDT 24
Peak memory 248812 kb
Host smart-9e067282-9152-40b4-aa00-f575cd75ea79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40453
90138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4045390138
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3680824897
Short name T213
Test name
Test status
Simulation time 1049115345 ps
CPU time 38.32 seconds
Started Jul 14 05:14:55 PM PDT 24
Finished Jul 14 05:15:34 PM PDT 24
Peak memory 256632 kb
Host smart-44ad0af3-d7f5-48e1-b07e-fc5198bbb270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36808
24897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3680824897
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1218885608
Short name T707
Test name
Test status
Simulation time 532086055 ps
CPU time 28.21 seconds
Started Jul 14 05:14:47 PM PDT 24
Finished Jul 14 05:15:16 PM PDT 24
Peak memory 256916 kb
Host smart-1b9414a9-4a7a-451b-85cf-d7c52e55f2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12188
85608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1218885608
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3060695062
Short name T77
Test name
Test status
Simulation time 131473948533 ps
CPU time 2252.48 seconds
Started Jul 14 05:15:07 PM PDT 24
Finished Jul 14 05:52:40 PM PDT 24
Peak memory 289296 kb
Host smart-364a2eee-769f-46c0-bc85-4a56a06ec8c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060695062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3060695062
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.3423913875
Short name T692
Test name
Test status
Simulation time 102831259397 ps
CPU time 4792.66 seconds
Started Jul 14 05:15:10 PM PDT 24
Finished Jul 14 06:35:04 PM PDT 24
Peak memory 336168 kb
Host smart-a447fc67-a6b3-4ffa-a465-eb81c9d65eb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423913875 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.3423913875
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.588565608
Short name T268
Test name
Test status
Simulation time 61555462976 ps
CPU time 1229.57 seconds
Started Jul 14 05:15:17 PM PDT 24
Finished Jul 14 05:35:47 PM PDT 24
Peak memory 286464 kb
Host smart-32c424a3-8f3b-4fe9-8818-b18fbd92b1ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588565608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.588565608
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2012587586
Short name T454
Test name
Test status
Simulation time 3243036994 ps
CPU time 224.3 seconds
Started Jul 14 05:15:15 PM PDT 24
Finished Jul 14 05:19:00 PM PDT 24
Peak memory 257476 kb
Host smart-b31eb286-28d9-4556-bb10-bbb3b7b5c9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20125
87586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2012587586
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2998969391
Short name T534
Test name
Test status
Simulation time 533649160 ps
CPU time 34.85 seconds
Started Jul 14 05:15:17 PM PDT 24
Finished Jul 14 05:15:52 PM PDT 24
Peak memory 255860 kb
Host smart-c5e34f53-d395-48a6-8761-699b00bd5128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29989
69391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2998969391
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.4273710733
Short name T192
Test name
Test status
Simulation time 42277637455 ps
CPU time 1411.63 seconds
Started Jul 14 05:15:16 PM PDT 24
Finished Jul 14 05:38:48 PM PDT 24
Peak memory 290172 kb
Host smart-5db52f12-57ca-4a22-b9d6-e70d10702a93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273710733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4273710733
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1814471165
Short name T462
Test name
Test status
Simulation time 106675291449 ps
CPU time 3360.41 seconds
Started Jul 14 05:15:23 PM PDT 24
Finished Jul 14 06:11:24 PM PDT 24
Peak memory 290172 kb
Host smart-42a03804-88bd-4090-852e-caca2039966e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814471165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1814471165
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.19300401
Short name T288
Test name
Test status
Simulation time 27604333724 ps
CPU time 351.86 seconds
Started Jul 14 05:15:16 PM PDT 24
Finished Jul 14 05:21:08 PM PDT 24
Peak memory 249288 kb
Host smart-7818520f-5c2b-4233-a88f-dab4c9b1a068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19300401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.19300401
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1127623245
Short name T411
Test name
Test status
Simulation time 281183801 ps
CPU time 32.61 seconds
Started Jul 14 05:15:10 PM PDT 24
Finished Jul 14 05:15:42 PM PDT 24
Peak memory 249280 kb
Host smart-7cfa444e-fb4e-4eae-a30a-890d4e8021d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11276
23245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1127623245
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1291741635
Short name T669
Test name
Test status
Simulation time 642563197 ps
CPU time 16.81 seconds
Started Jul 14 05:15:10 PM PDT 24
Finished Jul 14 05:15:28 PM PDT 24
Peak memory 248896 kb
Host smart-9dd5a737-1ac7-4708-9cd7-99629516c04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12917
41635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1291741635
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3624349801
Short name T597
Test name
Test status
Simulation time 6156438309 ps
CPU time 42.68 seconds
Started Jul 14 05:15:18 PM PDT 24
Finished Jul 14 05:16:01 PM PDT 24
Peak memory 249248 kb
Host smart-0eb1f034-2e72-49ce-864b-b2e9a4f3c1ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36243
49801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3624349801
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1804926092
Short name T263
Test name
Test status
Simulation time 367614629 ps
CPU time 21.08 seconds
Started Jul 14 05:15:10 PM PDT 24
Finished Jul 14 05:15:31 PM PDT 24
Peak memory 249236 kb
Host smart-5203895d-4120-4a61-bb3f-efb41df80914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18049
26092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1804926092
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2863265241
Short name T709
Test name
Test status
Simulation time 7027320443 ps
CPU time 485.58 seconds
Started Jul 14 05:15:22 PM PDT 24
Finished Jul 14 05:23:28 PM PDT 24
Peak memory 257560 kb
Host smart-6ffa9920-6f7e-4723-b016-cc7eab7826f6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863265241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2863265241
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.231772918
Short name T683
Test name
Test status
Simulation time 98148586214 ps
CPU time 2057.18 seconds
Started Jul 14 05:15:31 PM PDT 24
Finished Jul 14 05:49:48 PM PDT 24
Peak memory 273800 kb
Host smart-464299ff-a777-43cb-8f6b-15f4f00103d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231772918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.231772918
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.587317326
Short name T384
Test name
Test status
Simulation time 526673278 ps
CPU time 65.85 seconds
Started Jul 14 05:15:33 PM PDT 24
Finished Jul 14 05:16:39 PM PDT 24
Peak memory 256672 kb
Host smart-04fae133-2529-4d87-a52c-e653e66da8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58731
7326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.587317326
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2466866401
Short name T668
Test name
Test status
Simulation time 2546987360 ps
CPU time 49.77 seconds
Started Jul 14 05:15:32 PM PDT 24
Finished Jul 14 05:16:22 PM PDT 24
Peak memory 249292 kb
Host smart-b253827d-f44d-4805-a332-1786741d4c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24668
66401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2466866401
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.4256047592
Short name T324
Test name
Test status
Simulation time 16359754170 ps
CPU time 855.29 seconds
Started Jul 14 05:15:37 PM PDT 24
Finished Jul 14 05:29:53 PM PDT 24
Peak memory 273552 kb
Host smart-4a893483-f558-4834-867a-39068389d8d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256047592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.4256047592
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1609488435
Short name T107
Test name
Test status
Simulation time 42366030062 ps
CPU time 1288.79 seconds
Started Jul 14 05:15:36 PM PDT 24
Finished Jul 14 05:37:06 PM PDT 24
Peak memory 265664 kb
Host smart-259bddd3-ae56-4c60-82cc-60a4e3598e38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609488435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1609488435
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3865395741
Short name T717
Test name
Test status
Simulation time 57115183559 ps
CPU time 377.38 seconds
Started Jul 14 05:15:36 PM PDT 24
Finished Jul 14 05:21:54 PM PDT 24
Peak memory 256080 kb
Host smart-2f699b66-e260-4013-afb2-6389d87ce16b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865395741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3865395741
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3991043034
Short name T617
Test name
Test status
Simulation time 4270704972 ps
CPU time 59.37 seconds
Started Jul 14 05:15:25 PM PDT 24
Finished Jul 14 05:16:24 PM PDT 24
Peak memory 256632 kb
Host smart-bcc28b79-8ac1-4f8d-961d-b70bb58d36b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39910
43034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3991043034
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.133175525
Short name T654
Test name
Test status
Simulation time 682695392 ps
CPU time 14.57 seconds
Started Jul 14 05:15:25 PM PDT 24
Finished Jul 14 05:15:40 PM PDT 24
Peak memory 253764 kb
Host smart-bd6e0b99-68cc-46b2-b0f1-7362a9ee6ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13317
5525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.133175525
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2961269512
Short name T380
Test name
Test status
Simulation time 168686378 ps
CPU time 7.72 seconds
Started Jul 14 05:15:30 PM PDT 24
Finished Jul 14 05:15:38 PM PDT 24
Peak memory 254284 kb
Host smart-175c7f1d-4435-4542-acac-6231ea83f8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29612
69512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2961269512
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3961973724
Short name T713
Test name
Test status
Simulation time 1223186296 ps
CPU time 69.2 seconds
Started Jul 14 05:15:23 PM PDT 24
Finished Jul 14 05:16:33 PM PDT 24
Peak memory 256732 kb
Host smart-06642791-89c0-4ad3-a2d4-62dc5081edb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39619
73724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3961973724
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1097929814
Short name T66
Test name
Test status
Simulation time 9620226143 ps
CPU time 133.87 seconds
Started Jul 14 05:15:37 PM PDT 24
Finished Jul 14 05:17:51 PM PDT 24
Peak memory 257384 kb
Host smart-576c6931-fcda-42aa-8cdb-a8aa5cf0aed2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097929814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1097929814
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2348577134
Short name T69
Test name
Test status
Simulation time 345482976920 ps
CPU time 8664.31 seconds
Started Jul 14 05:15:37 PM PDT 24
Finished Jul 14 07:40:02 PM PDT 24
Peak memory 395656 kb
Host smart-594ea556-5c7c-4627-82cb-02bddf3bf5b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348577134 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2348577134
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.710193074
Short name T661
Test name
Test status
Simulation time 97902578168 ps
CPU time 2831.01 seconds
Started Jul 14 05:36:38 PM PDT 24
Finished Jul 14 06:23:50 PM PDT 24
Peak memory 289340 kb
Host smart-9048aa4c-8e47-4c16-bbe9-0820278af07e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710193074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.710193074
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1433096855
Short name T510
Test name
Test status
Simulation time 1226152500 ps
CPU time 9.43 seconds
Started Jul 14 05:15:43 PM PDT 24
Finished Jul 14 05:15:53 PM PDT 24
Peak memory 256684 kb
Host smart-17be936a-d499-41ef-b9b8-fae6900102b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14330
96855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1433096855
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.4179338389
Short name T671
Test name
Test status
Simulation time 4375264777 ps
CPU time 57.13 seconds
Started Jul 14 05:15:38 PM PDT 24
Finished Jul 14 05:16:36 PM PDT 24
Peak memory 256712 kb
Host smart-7459c1cc-e069-46d1-8dc9-e92f95e73395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41793
38389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4179338389
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.916323319
Short name T314
Test name
Test status
Simulation time 25352030969 ps
CPU time 1171.95 seconds
Started Jul 14 05:15:51 PM PDT 24
Finished Jul 14 05:35:23 PM PDT 24
Peak memory 284776 kb
Host smart-5f9376bf-1a91-438a-a66d-052e84ce54be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916323319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.916323319
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3454519813
Short name T584
Test name
Test status
Simulation time 112884423208 ps
CPU time 1515.86 seconds
Started Jul 14 05:15:50 PM PDT 24
Finished Jul 14 05:41:07 PM PDT 24
Peak memory 273696 kb
Host smart-fae69e39-7ea3-4194-ad52-92d14ed05ebd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454519813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3454519813
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3995960716
Short name T480
Test name
Test status
Simulation time 4444937145 ps
CPU time 200.6 seconds
Started Jul 14 05:15:48 PM PDT 24
Finished Jul 14 05:19:09 PM PDT 24
Peak memory 257304 kb
Host smart-6612c611-88fb-498b-b2c2-6c16e3ecfc7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995960716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3995960716
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3594533899
Short name T696
Test name
Test status
Simulation time 3560876863 ps
CPU time 64.38 seconds
Started Jul 14 05:15:36 PM PDT 24
Finished Jul 14 05:16:41 PM PDT 24
Peak memory 257232 kb
Host smart-eaf95eba-527e-42e8-94bf-7e2134daab36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35945
33899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3594533899
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3678284341
Short name T99
Test name
Test status
Simulation time 1235174319 ps
CPU time 87.65 seconds
Started Jul 14 05:15:36 PM PDT 24
Finished Jul 14 05:17:05 PM PDT 24
Peak memory 257236 kb
Host smart-2989d861-1059-4b45-bb31-71b69483e04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36782
84341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3678284341
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1550396248
Short name T405
Test name
Test status
Simulation time 3233110027 ps
CPU time 52.34 seconds
Started Jul 14 05:15:43 PM PDT 24
Finished Jul 14 05:16:36 PM PDT 24
Peak memory 256944 kb
Host smart-d6632c23-319e-42b2-af26-14c09319d1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15503
96248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1550396248
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1910842867
Short name T570
Test name
Test status
Simulation time 244267880 ps
CPU time 26.46 seconds
Started Jul 14 05:15:38 PM PDT 24
Finished Jul 14 05:16:04 PM PDT 24
Peak memory 257252 kb
Host smart-f77dda8c-8388-431d-84e6-257b6445c201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19108
42867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1910842867
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2193386737
Short name T511
Test name
Test status
Simulation time 31587868203 ps
CPU time 665.01 seconds
Started Jul 14 05:16:06 PM PDT 24
Finished Jul 14 05:27:12 PM PDT 24
Peak memory 272320 kb
Host smart-77964cc4-71be-498c-a2b7-a34cda97caea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193386737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2193386737
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2101980841
Short name T361
Test name
Test status
Simulation time 571473028 ps
CPU time 55.97 seconds
Started Jul 14 05:16:08 PM PDT 24
Finished Jul 14 05:17:04 PM PDT 24
Peak memory 256976 kb
Host smart-1c64318e-5733-493d-bcf2-9c6b00ed71ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21019
80841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2101980841
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.990927741
Short name T247
Test name
Test status
Simulation time 715986798 ps
CPU time 35.08 seconds
Started Jul 14 05:16:07 PM PDT 24
Finished Jul 14 05:16:42 PM PDT 24
Peak memory 248768 kb
Host smart-41551870-b491-494e-bd15-6f1f731e449e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99092
7741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.990927741
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2776609292
Short name T323
Test name
Test status
Simulation time 93737763477 ps
CPU time 1550.81 seconds
Started Jul 14 05:16:09 PM PDT 24
Finished Jul 14 05:42:00 PM PDT 24
Peak memory 273556 kb
Host smart-0e9c58e7-7254-42d7-a22e-93d89dc84e10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776609292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2776609292
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1009066022
Short name T394
Test name
Test status
Simulation time 8183681799 ps
CPU time 897.89 seconds
Started Jul 14 05:16:07 PM PDT 24
Finished Jul 14 05:31:05 PM PDT 24
Peak memory 268720 kb
Host smart-b7896fa3-7fc0-46da-a0ba-fee70b7eb43f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009066022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1009066022
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3182101128
Short name T364
Test name
Test status
Simulation time 415951034 ps
CPU time 35.13 seconds
Started Jul 14 05:15:56 PM PDT 24
Finished Jul 14 05:16:31 PM PDT 24
Peak memory 249140 kb
Host smart-5661dd9a-c72e-4f4d-8c22-237601524f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31821
01128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3182101128
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2657313307
Short name T100
Test name
Test status
Simulation time 732488415 ps
CPU time 39.55 seconds
Started Jul 14 05:15:53 PM PDT 24
Finished Jul 14 05:16:33 PM PDT 24
Peak memory 248932 kb
Host smart-49701ce7-f246-42b6-98c7-0a74ac3d47cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26573
13307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2657313307
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3851411737
Short name T228
Test name
Test status
Simulation time 314225597 ps
CPU time 26.58 seconds
Started Jul 14 05:16:05 PM PDT 24
Finished Jul 14 05:16:32 PM PDT 24
Peak memory 249180 kb
Host smart-1bcda418-3bef-4042-9da6-703e760ea8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38514
11737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3851411737
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.4279216539
Short name T393
Test name
Test status
Simulation time 122843572 ps
CPU time 4.75 seconds
Started Jul 14 05:15:58 PM PDT 24
Finished Jul 14 05:16:04 PM PDT 24
Peak memory 249140 kb
Host smart-d8268f9e-b534-4fed-9a74-9ea539c8216e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42792
16539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.4279216539
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2347508133
Short name T25
Test name
Test status
Simulation time 123025392606 ps
CPU time 2514.22 seconds
Started Jul 14 05:16:19 PM PDT 24
Finished Jul 14 05:58:13 PM PDT 24
Peak memory 299504 kb
Host smart-91646806-c6ca-4002-96cb-2d8a2a2d8f09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347508133 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2347508133
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.419902201
Short name T56
Test name
Test status
Simulation time 30923875225 ps
CPU time 1148.64 seconds
Started Jul 14 05:16:16 PM PDT 24
Finished Jul 14 05:35:25 PM PDT 24
Peak memory 281976 kb
Host smart-c5406134-8b34-4cc2-9557-8f5998e911dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419902201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.419902201
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3242380469
Short name T460
Test name
Test status
Simulation time 1083664505 ps
CPU time 105.15 seconds
Started Jul 14 05:16:15 PM PDT 24
Finished Jul 14 05:18:01 PM PDT 24
Peak memory 256620 kb
Host smart-520519ec-7cf0-4ee9-bf17-67b9384e652f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32423
80469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3242380469
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2795129897
Short name T347
Test name
Test status
Simulation time 374335441 ps
CPU time 22.41 seconds
Started Jul 14 05:16:15 PM PDT 24
Finished Jul 14 05:16:38 PM PDT 24
Peak memory 248572 kb
Host smart-b75e0e8f-08ea-4114-a2b2-15e64072b4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27951
29897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2795129897
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3180390217
Short name T284
Test name
Test status
Simulation time 28964577439 ps
CPU time 1260.4 seconds
Started Jul 14 05:16:16 PM PDT 24
Finished Jul 14 05:37:17 PM PDT 24
Peak memory 285756 kb
Host smart-6947905d-0dd5-43c4-a55a-5f338e5b404f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180390217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3180390217
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.763349866
Short name T452
Test name
Test status
Simulation time 31866736377 ps
CPU time 1841.3 seconds
Started Jul 14 05:16:22 PM PDT 24
Finished Jul 14 05:47:04 PM PDT 24
Peak memory 290016 kb
Host smart-b91a21de-1841-47e4-96a1-0bd73400feef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763349866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.763349866
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3925889115
Short name T309
Test name
Test status
Simulation time 18615411521 ps
CPU time 248.13 seconds
Started Jul 14 05:16:14 PM PDT 24
Finished Jul 14 05:20:22 PM PDT 24
Peak memory 248264 kb
Host smart-bc8a2967-dd56-449e-b47b-9b7104a6e766
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925889115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3925889115
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3376622563
Short name T390
Test name
Test status
Simulation time 47584033 ps
CPU time 3.92 seconds
Started Jul 14 05:16:13 PM PDT 24
Finished Jul 14 05:16:17 PM PDT 24
Peak memory 249160 kb
Host smart-7ac320b3-fa14-453b-86ec-e2bbf8545a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33766
22563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3376622563
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1313374574
Short name T684
Test name
Test status
Simulation time 1025530066 ps
CPU time 16.76 seconds
Started Jul 14 05:16:15 PM PDT 24
Finished Jul 14 05:16:32 PM PDT 24
Peak memory 255872 kb
Host smart-43207615-16d0-435b-83ee-a8c5aec1d7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13133
74574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1313374574
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1335887550
Short name T464
Test name
Test status
Simulation time 335005126 ps
CPU time 20.2 seconds
Started Jul 14 05:16:17 PM PDT 24
Finished Jul 14 05:16:37 PM PDT 24
Peak memory 256720 kb
Host smart-3711d66e-8dba-4b5b-9771-44ad7296c7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13358
87550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1335887550
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1611208194
Short name T386
Test name
Test status
Simulation time 201258888 ps
CPU time 21.19 seconds
Started Jul 14 05:16:15 PM PDT 24
Finished Jul 14 05:16:37 PM PDT 24
Peak memory 256792 kb
Host smart-0090219a-ee01-4e2b-93d1-bebc5b585a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16112
08194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1611208194
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2749733115
Short name T443
Test name
Test status
Simulation time 87569297571 ps
CPU time 2561.82 seconds
Started Jul 14 05:16:24 PM PDT 24
Finished Jul 14 05:59:07 PM PDT 24
Peak memory 290052 kb
Host smart-44004637-31bd-467d-8b20-e4a83fc6cebe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749733115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2749733115
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2771604393
Short name T600
Test name
Test status
Simulation time 98816642029 ps
CPU time 2851.14 seconds
Started Jul 14 05:16:29 PM PDT 24
Finished Jul 14 06:04:01 PM PDT 24
Peak memory 290196 kb
Host smart-ab4bccbb-d9fc-444d-bbd4-f630db573eed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771604393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2771604393
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2137983326
Short name T468
Test name
Test status
Simulation time 5523534531 ps
CPU time 278.88 seconds
Started Jul 14 05:16:29 PM PDT 24
Finished Jul 14 05:21:09 PM PDT 24
Peak memory 257560 kb
Host smart-9032ef35-6b64-4f67-95ca-00ee67615276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21379
83326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2137983326
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2618795698
Short name T622
Test name
Test status
Simulation time 222738499 ps
CPU time 7.71 seconds
Started Jul 14 05:16:31 PM PDT 24
Finished Jul 14 05:16:39 PM PDT 24
Peak memory 249532 kb
Host smart-8f5155ff-3730-43bc-a1da-392bfd20b0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26187
95698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2618795698
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3655176896
Short name T2
Test name
Test status
Simulation time 50022490219 ps
CPU time 1194.31 seconds
Started Jul 14 05:16:28 PM PDT 24
Finished Jul 14 05:36:22 PM PDT 24
Peak memory 273288 kb
Host smart-baf84692-d472-42ad-aa6d-7f3a7758ea24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655176896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3655176896
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2474381755
Short name T424
Test name
Test status
Simulation time 18130665417 ps
CPU time 1543.02 seconds
Started Jul 14 05:16:30 PM PDT 24
Finished Jul 14 05:42:13 PM PDT 24
Peak memory 289360 kb
Host smart-b9af06db-0932-4839-b916-1468531e485a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474381755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2474381755
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3543013076
Short name T290
Test name
Test status
Simulation time 17337472208 ps
CPU time 180.03 seconds
Started Jul 14 05:16:30 PM PDT 24
Finished Jul 14 05:19:31 PM PDT 24
Peak memory 248108 kb
Host smart-58f05956-1e73-41f6-9ca7-3bbb581ea5ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543013076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3543013076
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3925853685
Short name T224
Test name
Test status
Simulation time 2197145272 ps
CPU time 29.69 seconds
Started Jul 14 05:16:19 PM PDT 24
Finished Jul 14 05:16:49 PM PDT 24
Peak memory 255788 kb
Host smart-3883cc8c-da12-40e7-a3d6-1bd95267b117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39258
53685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3925853685
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1698943394
Short name T440
Test name
Test status
Simulation time 787257746 ps
CPU time 22.8 seconds
Started Jul 14 05:16:21 PM PDT 24
Finished Jul 14 05:16:44 PM PDT 24
Peak memory 248784 kb
Host smart-fb99e96e-0bb4-4bd9-aed2-350532401d94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16989
43394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1698943394
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3688428805
Short name T656
Test name
Test status
Simulation time 1662193378 ps
CPU time 27.6 seconds
Started Jul 14 05:16:27 PM PDT 24
Finished Jul 14 05:16:55 PM PDT 24
Peak memory 249156 kb
Host smart-6afc5227-530f-4c5c-afaf-458b3c447feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36884
28805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3688428805
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3300282126
Short name T80
Test name
Test status
Simulation time 1011266086 ps
CPU time 30.55 seconds
Started Jul 14 05:16:26 PM PDT 24
Finished Jul 14 05:16:56 PM PDT 24
Peak memory 256924 kb
Host smart-95fe46c2-b4bf-487f-8ad3-37329826117e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33002
82126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3300282126
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.4118833780
Short name T49
Test name
Test status
Simulation time 17833204480 ps
CPU time 417.48 seconds
Started Jul 14 05:16:31 PM PDT 24
Finished Jul 14 05:23:29 PM PDT 24
Peak memory 265716 kb
Host smart-9539d3dd-f38f-4b1b-a35e-6b7d3a43ef59
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118833780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.4118833780
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1984763975
Short name T197
Test name
Test status
Simulation time 23835334 ps
CPU time 2.71 seconds
Started Jul 14 05:07:00 PM PDT 24
Finished Jul 14 05:07:03 PM PDT 24
Peak memory 249412 kb
Host smart-f9a0cdc5-12c3-40e3-916a-7890935265dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1984763975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1984763975
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2573683750
Short name T506
Test name
Test status
Simulation time 19098330850 ps
CPU time 1038.26 seconds
Started Jul 14 05:07:01 PM PDT 24
Finished Jul 14 05:24:20 PM PDT 24
Peak memory 273312 kb
Host smart-1bf27009-4c82-4996-acaa-9029645345f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573683750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2573683750
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3613999852
Short name T355
Test name
Test status
Simulation time 1112784750 ps
CPU time 16.56 seconds
Started Jul 14 05:06:55 PM PDT 24
Finished Jul 14 05:07:12 PM PDT 24
Peak memory 249184 kb
Host smart-06adb423-18cf-42e3-b7de-097568ec118c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3613999852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3613999852
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3887785625
Short name T447
Test name
Test status
Simulation time 1980482907 ps
CPU time 99.35 seconds
Started Jul 14 05:06:53 PM PDT 24
Finished Jul 14 05:08:32 PM PDT 24
Peak memory 256932 kb
Host smart-43740ad0-840e-4105-9a0f-b37967fac94e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38877
85625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3887785625
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.8266961
Short name T382
Test name
Test status
Simulation time 781566987 ps
CPU time 23.84 seconds
Started Jul 14 05:06:54 PM PDT 24
Finished Jul 14 05:07:18 PM PDT 24
Peak memory 248788 kb
Host smart-c1aecd21-90fd-4e2f-bb40-a19af46da27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82669
61 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.8266961
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3864687244
Short name T672
Test name
Test status
Simulation time 79959909125 ps
CPU time 1321.18 seconds
Started Jul 14 05:07:01 PM PDT 24
Finished Jul 14 05:29:03 PM PDT 24
Peak memory 290232 kb
Host smart-bf5b0603-f3ac-478a-b232-90bb4586e3d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864687244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3864687244
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1252845468
Short name T513
Test name
Test status
Simulation time 7584959364 ps
CPU time 986.55 seconds
Started Jul 14 05:06:54 PM PDT 24
Finished Jul 14 05:23:22 PM PDT 24
Peak memory 289056 kb
Host smart-0732f2f1-e0a3-43de-b974-f42d055037b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252845468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1252845468
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2933030183
Short name T302
Test name
Test status
Simulation time 30021137956 ps
CPU time 315.18 seconds
Started Jul 14 05:07:01 PM PDT 24
Finished Jul 14 05:12:17 PM PDT 24
Peak memory 249260 kb
Host smart-ce92ac50-2e5a-4e13-b8d9-ee2256121993
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933030183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2933030183
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2284699487
Short name T608
Test name
Test status
Simulation time 970992170 ps
CPU time 45.7 seconds
Started Jul 14 05:06:55 PM PDT 24
Finished Jul 14 05:07:41 PM PDT 24
Peak memory 256396 kb
Host smart-b39f73f9-8fcb-4601-8793-240c46cc0678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22846
99487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2284699487
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3193809738
Short name T422
Test name
Test status
Simulation time 5414943260 ps
CPU time 39.46 seconds
Started Jul 14 05:07:01 PM PDT 24
Finished Jul 14 05:07:40 PM PDT 24
Peak memory 257404 kb
Host smart-850b949f-1802-449d-a1f2-7dff318cff88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31938
09738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3193809738
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1270174289
Short name T482
Test name
Test status
Simulation time 268702086 ps
CPU time 14.57 seconds
Started Jul 14 05:06:54 PM PDT 24
Finished Jul 14 05:07:09 PM PDT 24
Peak memory 254364 kb
Host smart-52aa189a-d96e-44b9-aa63-279c03783e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12701
74289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1270174289
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2502546209
Short name T530
Test name
Test status
Simulation time 51891807 ps
CPU time 4.1 seconds
Started Jul 14 05:06:56 PM PDT 24
Finished Jul 14 05:07:00 PM PDT 24
Peak memory 240868 kb
Host smart-22428282-cc5e-4856-9f71-28119c1c3aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25025
46209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2502546209
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.792049413
Short name T72
Test name
Test status
Simulation time 376722867103 ps
CPU time 2084.25 seconds
Started Jul 14 05:06:56 PM PDT 24
Finished Jul 14 05:41:41 PM PDT 24
Peak memory 285260 kb
Host smart-1e178c4a-e728-42c5-af55-91970f5dae11
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792049413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.792049413
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.4029863665
Short name T205
Test name
Test status
Simulation time 130759902 ps
CPU time 3.17 seconds
Started Jul 14 05:07:21 PM PDT 24
Finished Jul 14 05:07:25 PM PDT 24
Peak memory 249528 kb
Host smart-27600f54-ab39-4be5-9e78-163ce49167cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4029863665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.4029863665
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1260846510
Short name T523
Test name
Test status
Simulation time 28439731317 ps
CPU time 2235.41 seconds
Started Jul 14 05:07:13 PM PDT 24
Finished Jul 14 05:44:29 PM PDT 24
Peak memory 287128 kb
Host smart-f5f09084-8ad9-4159-a3bb-93be07c86f25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260846510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1260846510
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2359887052
Short name T509
Test name
Test status
Simulation time 263602414 ps
CPU time 12.07 seconds
Started Jul 14 05:07:21 PM PDT 24
Finished Jul 14 05:07:34 PM PDT 24
Peak memory 249152 kb
Host smart-0dfb6694-f4e6-4150-b144-05022a56cafe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2359887052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2359887052
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1269180720
Short name T102
Test name
Test status
Simulation time 4555630356 ps
CPU time 139.2 seconds
Started Jul 14 05:07:13 PM PDT 24
Finished Jul 14 05:09:33 PM PDT 24
Peak memory 256868 kb
Host smart-7ce53bcb-1f80-47a7-a535-28120f613a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12691
80720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1269180720
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3232272057
Short name T686
Test name
Test status
Simulation time 3006554576 ps
CPU time 33.41 seconds
Started Jul 14 05:07:06 PM PDT 24
Finished Jul 14 05:07:39 PM PDT 24
Peak memory 256044 kb
Host smart-61d06999-fa7d-4334-8038-09645d05d9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32322
72057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3232272057
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.923534857
Short name T621
Test name
Test status
Simulation time 51641670878 ps
CPU time 1369.65 seconds
Started Jul 14 05:07:19 PM PDT 24
Finished Jul 14 05:30:09 PM PDT 24
Peak memory 283884 kb
Host smart-c992c2d4-f1b7-42be-b371-8d6609cf1a77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923534857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.923534857
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3329351412
Short name T219
Test name
Test status
Simulation time 8572937511 ps
CPU time 348.22 seconds
Started Jul 14 05:07:13 PM PDT 24
Finished Jul 14 05:13:01 PM PDT 24
Peak memory 249360 kb
Host smart-c67ec7ed-3568-4bf3-92bc-987d3da35cd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329351412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3329351412
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2053746884
Short name T354
Test name
Test status
Simulation time 167782826 ps
CPU time 20.76 seconds
Started Jul 14 05:07:01 PM PDT 24
Finished Jul 14 05:07:22 PM PDT 24
Peak memory 249248 kb
Host smart-9e74f741-11d9-4ac6-8cc7-74383b4c206e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20537
46884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2053746884
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1493729547
Short name T279
Test name
Test status
Simulation time 394267889 ps
CPU time 24.51 seconds
Started Jul 14 05:07:07 PM PDT 24
Finished Jul 14 05:07:31 PM PDT 24
Peak memory 248748 kb
Host smart-268ba737-2d16-48dd-91eb-441f3b5e6128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14937
29547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1493729547
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3715925504
Short name T591
Test name
Test status
Simulation time 1828119110 ps
CPU time 62.28 seconds
Started Jul 14 05:07:01 PM PDT 24
Finished Jul 14 05:08:04 PM PDT 24
Peak memory 256388 kb
Host smart-f5b45a37-a166-479c-9d04-5c5f6e7d26bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37159
25504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3715925504
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2424086400
Short name T253
Test name
Test status
Simulation time 167662703302 ps
CPU time 5033.39 seconds
Started Jul 14 05:07:18 PM PDT 24
Finished Jul 14 06:31:12 PM PDT 24
Peak memory 306240 kb
Host smart-17c09bc0-1ed6-4fea-9fce-f68330192970
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424086400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2424086400
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1252216205
Short name T201
Test name
Test status
Simulation time 38121614 ps
CPU time 2.45 seconds
Started Jul 14 05:07:25 PM PDT 24
Finished Jul 14 05:07:28 PM PDT 24
Peak memory 249520 kb
Host smart-2cb528b4-6933-4a01-9a51-6ddae53f5803
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1252216205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1252216205
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1712276587
Short name T15
Test name
Test status
Simulation time 11159923491 ps
CPU time 1380.81 seconds
Started Jul 14 05:07:26 PM PDT 24
Finished Jul 14 05:30:27 PM PDT 24
Peak memory 290168 kb
Host smart-d683d3b6-b929-4d47-b571-ab5846f6bf35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712276587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1712276587
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3448244469
Short name T491
Test name
Test status
Simulation time 421382047 ps
CPU time 22.18 seconds
Started Jul 14 05:07:26 PM PDT 24
Finished Jul 14 05:07:48 PM PDT 24
Peak memory 249168 kb
Host smart-e421cc28-7126-4777-9ca4-e52bdabdd5e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3448244469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3448244469
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.264467273
Short name T562
Test name
Test status
Simulation time 1380399737 ps
CPU time 45.32 seconds
Started Jul 14 05:07:26 PM PDT 24
Finished Jul 14 05:08:11 PM PDT 24
Peak memory 256832 kb
Host smart-d4e0c06e-7431-4206-a284-f4dd9c05e3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26446
7273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.264467273
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3307921482
Short name T360
Test name
Test status
Simulation time 11277857801 ps
CPU time 74.31 seconds
Started Jul 14 05:07:21 PM PDT 24
Finished Jul 14 05:08:36 PM PDT 24
Peak memory 257416 kb
Host smart-995cd351-ca63-46b7-aacc-055c0e02219e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33079
21482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3307921482
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.453348711
Short name T331
Test name
Test status
Simulation time 63025078943 ps
CPU time 1573.7 seconds
Started Jul 14 05:07:26 PM PDT 24
Finished Jul 14 05:33:40 PM PDT 24
Peak memory 273416 kb
Host smart-72c90c1b-c44c-4120-b330-f1714f0f03ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453348711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.453348711
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1674152871
Short name T64
Test name
Test status
Simulation time 35269101123 ps
CPU time 2003.98 seconds
Started Jul 14 05:07:25 PM PDT 24
Finished Jul 14 05:40:50 PM PDT 24
Peak memory 273348 kb
Host smart-a5565e86-b7c3-4efe-8f15-85805b5bf704
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674152871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1674152871
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1343398890
Short name T301
Test name
Test status
Simulation time 22395708152 ps
CPU time 253.25 seconds
Started Jul 14 05:07:27 PM PDT 24
Finished Jul 14 05:11:41 PM PDT 24
Peak memory 255124 kb
Host smart-a3d44ba2-d339-4fff-ac50-422d4c058b1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343398890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1343398890
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3719370584
Short name T278
Test name
Test status
Simulation time 298618422 ps
CPU time 24.97 seconds
Started Jul 14 05:07:19 PM PDT 24
Finished Jul 14 05:07:44 PM PDT 24
Peak memory 256388 kb
Host smart-0abac9ef-af2b-4ec0-803a-288ddac7c93c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37193
70584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3719370584
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3023729974
Short name T95
Test name
Test status
Simulation time 213543551 ps
CPU time 13.98 seconds
Started Jul 14 05:07:19 PM PDT 24
Finished Jul 14 05:07:33 PM PDT 24
Peak memory 248764 kb
Host smart-f917f0aa-a1c8-409c-af8c-160bdd537021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30237
29974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3023729974
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.805217287
Short name T357
Test name
Test status
Simulation time 582751970 ps
CPU time 34.72 seconds
Started Jul 14 05:07:27 PM PDT 24
Finished Jul 14 05:08:02 PM PDT 24
Peak memory 248436 kb
Host smart-c686d45e-c9e4-4c1c-babf-23da1e27d675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80521
7287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.805217287
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2852061679
Short name T432
Test name
Test status
Simulation time 267764065 ps
CPU time 32.98 seconds
Started Jul 14 05:07:21 PM PDT 24
Finished Jul 14 05:07:55 PM PDT 24
Peak memory 249176 kb
Host smart-8589eae8-cf80-4f8b-b6a0-b6da4e878ab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28520
61679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2852061679
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.515669851
Short name T212
Test name
Test status
Simulation time 92706812 ps
CPU time 3.95 seconds
Started Jul 14 05:07:41 PM PDT 24
Finished Jul 14 05:07:46 PM PDT 24
Peak memory 249456 kb
Host smart-2320c708-ccfe-411f-aa2a-51987adfde14
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=515669851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.515669851
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1888171832
Short name T476
Test name
Test status
Simulation time 7911886540 ps
CPU time 934.79 seconds
Started Jul 14 05:07:33 PM PDT 24
Finished Jul 14 05:23:08 PM PDT 24
Peak memory 273900 kb
Host smart-7a6ded80-afb1-4614-a1dd-ffff52cef676
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888171832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1888171832
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2155689439
Short name T437
Test name
Test status
Simulation time 471914670 ps
CPU time 13.44 seconds
Started Jul 14 05:07:41 PM PDT 24
Finished Jul 14 05:07:55 PM PDT 24
Peak memory 249072 kb
Host smart-3cc9f541-3643-4e18-8305-fa1702bd7853
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2155689439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2155689439
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3550007063
Short name T632
Test name
Test status
Simulation time 2321175183 ps
CPU time 140.04 seconds
Started Jul 14 05:07:32 PM PDT 24
Finished Jul 14 05:09:53 PM PDT 24
Peak memory 257492 kb
Host smart-a85139a9-9605-4be3-8069-04cbd5b277bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35500
07063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3550007063
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.340294420
Short name T602
Test name
Test status
Simulation time 720870163 ps
CPU time 36.42 seconds
Started Jul 14 05:07:32 PM PDT 24
Finished Jul 14 05:08:09 PM PDT 24
Peak memory 256384 kb
Host smart-602c19e4-7c8b-4881-b8c4-3f539c265706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34029
4420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.340294420
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.4289382094
Short name T368
Test name
Test status
Simulation time 103266263930 ps
CPU time 2962.23 seconds
Started Jul 14 05:07:40 PM PDT 24
Finished Jul 14 05:57:03 PM PDT 24
Peak memory 289016 kb
Host smart-ab2e4ad6-d82e-4a70-9712-50495a421567
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289382094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.4289382094
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3032123640
Short name T648
Test name
Test status
Simulation time 52584183471 ps
CPU time 588.38 seconds
Started Jul 14 05:07:34 PM PDT 24
Finished Jul 14 05:17:23 PM PDT 24
Peak memory 249292 kb
Host smart-7aec8cf4-6045-43d0-bd90-f1fe4bd1244b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032123640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3032123640
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2533238471
Short name T92
Test name
Test status
Simulation time 426470046 ps
CPU time 30.46 seconds
Started Jul 14 05:07:34 PM PDT 24
Finished Jul 14 05:08:05 PM PDT 24
Peak memory 256792 kb
Host smart-5a974b40-2c67-4b92-8368-614b67b284e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25332
38471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2533238471
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1180576916
Short name T98
Test name
Test status
Simulation time 655611950 ps
CPU time 39.34 seconds
Started Jul 14 05:07:34 PM PDT 24
Finished Jul 14 05:08:14 PM PDT 24
Peak memory 248704 kb
Host smart-876f93bb-c67d-46cb-a90e-55b682b15530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11805
76916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1180576916
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1998507002
Short name T633
Test name
Test status
Simulation time 168049828 ps
CPU time 12.64 seconds
Started Jul 14 05:07:34 PM PDT 24
Finished Jul 14 05:07:47 PM PDT 24
Peak memory 248472 kb
Host smart-c8487292-1100-472a-ad83-d0b9d795dd9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19985
07002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1998507002
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2600046438
Short name T690
Test name
Test status
Simulation time 303448138 ps
CPU time 27.57 seconds
Started Jul 14 05:07:25 PM PDT 24
Finished Jul 14 05:07:53 PM PDT 24
Peak memory 249228 kb
Host smart-a6e8b7f2-4295-4213-8cee-73279ca8690e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26000
46438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2600046438
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.925559184
Short name T535
Test name
Test status
Simulation time 15806374250 ps
CPU time 1292.9 seconds
Started Jul 14 05:07:41 PM PDT 24
Finished Jul 14 05:29:15 PM PDT 24
Peak memory 289320 kb
Host smart-2ccdec08-9dbe-4a89-b0e6-369690a35970
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925559184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.925559184
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1621644000
Short name T37
Test name
Test status
Simulation time 310395916891 ps
CPU time 1492.14 seconds
Started Jul 14 05:07:42 PM PDT 24
Finished Jul 14 05:32:35 PM PDT 24
Peak memory 286976 kb
Host smart-1192a8b5-68c7-4cb2-95b3-3cfd1aee4ff0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621644000 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1621644000
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2498659061
Short name T202
Test name
Test status
Simulation time 140191204 ps
CPU time 3.28 seconds
Started Jul 14 05:07:47 PM PDT 24
Finished Jul 14 05:07:51 PM PDT 24
Peak memory 249472 kb
Host smart-72c9f56e-fd10-4068-bccd-83e9c30f6e9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2498659061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2498659061
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.884589995
Short name T485
Test name
Test status
Simulation time 11046321518 ps
CPU time 1150.6 seconds
Started Jul 14 05:07:47 PM PDT 24
Finished Jul 14 05:26:58 PM PDT 24
Peak memory 283960 kb
Host smart-87fc8336-80e5-4717-9813-962f606c9104
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884589995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.884589995
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.4094348060
Short name T497
Test name
Test status
Simulation time 887497518 ps
CPU time 11.98 seconds
Started Jul 14 05:07:46 PM PDT 24
Finished Jul 14 05:07:58 PM PDT 24
Peak memory 249048 kb
Host smart-2aac4df2-5dc2-415a-a6d5-10f1200b92f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4094348060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.4094348060
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1936626154
Short name T565
Test name
Test status
Simulation time 10309729469 ps
CPU time 52.3 seconds
Started Jul 14 05:07:48 PM PDT 24
Finished Jul 14 05:08:41 PM PDT 24
Peak memory 256872 kb
Host smart-f2cc55a0-4844-44d6-9033-a55c474f7a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19366
26154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1936626154
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2288815055
Short name T61
Test name
Test status
Simulation time 303230837 ps
CPU time 30.76 seconds
Started Jul 14 05:07:47 PM PDT 24
Finished Jul 14 05:08:18 PM PDT 24
Peak memory 249040 kb
Host smart-31448204-9376-43d9-843c-4084c0778e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22888
15055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2288815055
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1306999161
Short name T316
Test name
Test status
Simulation time 13690405198 ps
CPU time 1487.46 seconds
Started Jul 14 05:07:46 PM PDT 24
Finished Jul 14 05:32:34 PM PDT 24
Peak memory 289428 kb
Host smart-c363287d-d03e-41b6-b255-86e08d976b60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306999161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1306999161
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1221141570
Short name T543
Test name
Test status
Simulation time 252205720957 ps
CPU time 2187.34 seconds
Started Jul 14 05:07:46 PM PDT 24
Finished Jul 14 05:44:14 PM PDT 24
Peak memory 273600 kb
Host smart-3dbaecc6-404d-430c-a7c3-d375db94709d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221141570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1221141570
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.708085038
Short name T663
Test name
Test status
Simulation time 3991952756 ps
CPU time 157.88 seconds
Started Jul 14 05:07:47 PM PDT 24
Finished Jul 14 05:10:26 PM PDT 24
Peak memory 249236 kb
Host smart-7dd1cc72-5cf6-4765-a487-20f6d969460a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708085038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.708085038
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3961155899
Short name T346
Test name
Test status
Simulation time 258102250 ps
CPU time 9.57 seconds
Started Jul 14 05:07:39 PM PDT 24
Finished Jul 14 05:07:49 PM PDT 24
Peak memory 249256 kb
Host smart-350c1568-fd32-4500-ab98-01b95c6f93aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39611
55899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3961155899
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.874429286
Short name T499
Test name
Test status
Simulation time 2440825718 ps
CPU time 46.99 seconds
Started Jul 14 05:07:41 PM PDT 24
Finished Jul 14 05:08:28 PM PDT 24
Peak memory 248680 kb
Host smart-ccc59a5b-8e68-4102-863c-db91303f6219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87442
9286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.874429286
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.785933406
Short name T489
Test name
Test status
Simulation time 40141053 ps
CPU time 5.6 seconds
Started Jul 14 05:07:46 PM PDT 24
Finished Jul 14 05:07:52 PM PDT 24
Peak memory 254876 kb
Host smart-7034bb9a-eff5-46a3-964c-12363f9a24ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78593
3406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.785933406
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3306729376
Short name T708
Test name
Test status
Simulation time 3346183621 ps
CPU time 74.38 seconds
Started Jul 14 05:07:41 PM PDT 24
Finished Jul 14 05:08:56 PM PDT 24
Peak memory 256928 kb
Host smart-fc6e26d9-fbf7-4dd6-8e3f-176cda1d69ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33067
29376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3306729376
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2901574324
Short name T507
Test name
Test status
Simulation time 53792494883 ps
CPU time 3116.23 seconds
Started Jul 14 05:07:46 PM PDT 24
Finished Jul 14 05:59:43 PM PDT 24
Peak memory 290008 kb
Host smart-6c31f1e7-ecf7-49a1-94bf-bd690b37d719
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901574324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2901574324
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.665323829
Short name T81
Test name
Test status
Simulation time 48382685188 ps
CPU time 4788.03 seconds
Started Jul 14 05:07:51 PM PDT 24
Finished Jul 14 06:27:40 PM PDT 24
Peak memory 306088 kb
Host smart-99948d52-f199-48d9-981a-c7f8bd0f4019
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665323829 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.665323829
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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