Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	101990	1			T1	2		T17	6		T14	4
class_i[0x1]	66006	1			T3	20		T14	7		T9	11
class_i[0x2]	68742	1			T1	3399		T2	5		T8	5378
class_i[0x3]	41848	1			T3	1		T17	3		T14	99

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	71696	1			T1	811		T8	1316		T14	683
alert[0x1]	69584	1			T1	833		T3	11		T17	1
alert[0x2]	67927	1			T1	813		T3	6		T17	3
alert[0x3]	69379	1			T1	944		T2	5		T3	4

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

278297

1

T1

3401

T2

5

T3

14

esc_ping_fail

289

1

T3

7

T9

3

T10

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	71615	1			T1	811		T8	1316		T14	683
esc_integrity_fail	alert[0x1]	69510	1			T1	833		T3	7		T17	1
esc_integrity_fail	alert[0x2]	67857	1			T1	813		T3	4		T17	3
esc_integrity_fail	alert[0x3]	69315	1			T1	944		T2	5		T3	3
esc_ping_fail	alert[0x0]	81	1			T9	1		T217	2		T62	1
esc_ping_fail	alert[0x1]	74	1			T3	4		T10	1		T217	1
esc_ping_fail	alert[0x2]	70	1			T3	2		T9	2		T10	1
esc_ping_fail	alert[0x3]	64	1			T3	1		T10	1		T217	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	101891	1			T1	2		T17	6		T14	4
esc_integrity_fail	class_i[0x1]	65900	1			T3	13		T14	7		T9	10
esc_integrity_fail	class_i[0x2]	68707	1			T1	3399		T2	5		T8	5378
esc_integrity_fail	class_i[0x3]	41799	1			T3	1		T17	3		T14	99
esc_ping_fail	class_i[0x0]	99	1			T9	1		T62	4		T283	9
esc_ping_fail	class_i[0x1]	106	1			T3	7		T9	1		T10	3
esc_ping_fail	class_i[0x2]	35	1			T9	1		T290	3		T291	2
esc_ping_fail	class_i[0x3]	49	1			T217	8		T292	4		T103	7