Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	708898917	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	708898917	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	708898917	708751681	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	708898917	708751681	0	0
tb.dut.EdnKnownO_A	0	0	708898917	708751681	0	0
tb.dut.EscPKnownO_A	0	0	708898917	708751681	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	708898917	60	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	708898917	60	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	708898917	60	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	708898917	60	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	708898917	60	0	0
tb.dut.IrqAKnownO_A	0	0	708898917	708751681	0	0
tb.dut.IrqBKnownO_A	0	0	708898917	708751681	0	0
tb.dut.IrqCKnownO_A	0	0	708898917	708751681	0	0
tb.dut.IrqDKnownO_A	0	0	708898917	708751681	0	0
tb.dut.TlAReadyKnownO_A	0	0	708898917	708751681	0	0
tb.dut.TlDValidKnownO_A	0	0	708898917	708751681	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	736798952	3167067	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	736798952	14312	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	736798952	13026	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	736798952	14630	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	736798952	13808	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	736798952	13030	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	736798952	13992	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	736798952	13304	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	736798952	13596	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	736798952	13161	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	736798952	13617	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	736798952	12902	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	736798952	15036	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	736798952	13322	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	736798952	12967	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	736798952	13240	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	736798952	13236	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	736798952	13152	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	736798952	13019	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	736798952	13144	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	736798952	15521	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	736798952	15007	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	736798952	12845	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	736798952	13164	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	736798952	14064	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	736798952	13793	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	736798952	14036	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	736798952	13970	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	736798952	14412	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	736798952	13246	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	736798952	13742	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	736798952	13917	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	736798952	13767	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	736798952	14346	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	736798952	15208	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	736798952	13754	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	736798952	13805	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	736798952	13664	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	736798952	13719	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	736798952	14181	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	736798952	13596	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	736798952	14019	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	736798952	12974	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	736798952	13979	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	736798952	13840	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	736798952	14388	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	736798952	14837	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	736798952	12785	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	736798952	14173	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	736798952	13150	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	736798952	13364	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	736798952	13516	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	736798952	14756	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	736798952	12709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	736798952	13844	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	736798952	13721	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	736798952	13745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	736798952	13362	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	736798952	14492	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	736798952	13234	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	736798952	14533	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	736798952	13113	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	736798952	13231	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	736798952	14210	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	736798952	13760	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	736798952	14586	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	736798952	14803	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	736798952	14068	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	736798952	14955	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	736798952	13793	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	736798952	24153	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	736798952	13234	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	736798952	14173	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	736798952	13081	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	736798952	12980	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	736798952	14161	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	736798952	13535	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	736798952	15381	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	736798952	13865	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	708898917	3822	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	708898917	246248	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	708898917	362939089	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	708898917	209	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	708898917	810	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	708898917	58	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	708898917	388	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	708710723	277185889	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	708898917	899	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	708898917	875	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	708898917	863	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	708898917	848	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	708898917	1071	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	708898917	112394	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	708898917	956	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	708898917	56	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	708898917	1092	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	708898917	912	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	708709218	708639442	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	708898917	708751681	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	708898917	3720	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	708898917	197897	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	708898917	420750837	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	708898917	209	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	708898917	545	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	708898917	26	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	708898917	256	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	708710723	299475005	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	708898917	621	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	708898917	612	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	708898917	602	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	708898917	600	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	708898917	937	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	708898917	107602	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	708898917	850	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	708898917	61	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	708898917	1121	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	708898917	941	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	708709218	708639442	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	708898917	708751681	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	708898917	1976	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	708898917	168874	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	708898917	432082755	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	708898917	172	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	708898917	492	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	708898917	20	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	708898917	224	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	708710723	333543184	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	708898917	566	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	708898917	556	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	708898917	546	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	708898917	539	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	708898917	1074	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	708898917	117727	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	708898917	988	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	708898917	65	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	708898917	1085	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	708898917	905	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	708709218	708639442	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	708898917	708751681	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	708898917	60	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	708898917	2550	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	708898917	193611	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	708898917	399046104	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	708898917	199	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	708898917	550	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	708898917	17	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	708898917	261	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	708710723	319415523	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	708898917	607	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	708898917	597	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	708898917	589	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	708898917	576	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	708898917	1051	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	708898917	105288	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	708898917	978	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	708898917	52	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	708898917	1069	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	708898917	889	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	708709218	708639442	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	708898917	708751681	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	736798952	138642247	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	736798952	736129017	0	0
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