Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	56	1			T14	1		T20	1		T45	1
class_index[0x1]	61	1			T64	1		T66	1		T24	1
class_index[0x2]	65	1			T17	1		T14	2		T41	1
class_index[0x3]	52	1			T5	3		T14	3		T41	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	72	1			T14	1		T20	1		T49	1
intr_timeout_cnt[1]	61	1			T5	3		T14	2		T41	1
intr_timeout_cnt[2]	18	1			T66	1		T68	1		T75	1
intr_timeout_cnt[3]	9	1			T76	1		T254	1		T255	1
intr_timeout_cnt[4]	25	1			T14	2		T26	1		T51	1
intr_timeout_cnt[5]	8	1			T74	1		T53	1		T256	1
intr_timeout_cnt[6]	18	1			T17	1		T73	1		T53	1
intr_timeout_cnt[7]	6	1			T14	1		T64	1		T255	1
intr_timeout_cnt[8]	8	1			T41	1		T74	1		T254	1
intr_timeout_cnt[9]	9	1			T51	1		T74	1		T75	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[3]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	14	1			T14	1		T20	1		T57	1
class_index[0x0]	intr_timeout_cnt[1]	13	1			T45	1		T26	3		T79	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T68	1		T75	1		T257	3
class_index[0x0]	intr_timeout_cnt[3]	3	1			T76	1		T255	1		T258	1
class_index[0x0]	intr_timeout_cnt[4]	11	1			T51	1		T73	1		T259	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T260	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	6	1			T78	1		T80	1		T261	3
class_index[0x0]	intr_timeout_cnt[8]	1	1			T254	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T51	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	19	1			T24	1		T77	1		T254	1
class_index[0x1]	intr_timeout_cnt[1]	16	1			T79	1		T80	1		T174	3
class_index[0x1]	intr_timeout_cnt[2]	8	1			T66	1		T81	1		T174	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T254	1		T219	2		T262	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T73	1		T189	1		T263	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T74	1		T264	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T53	1		T256	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	4	1			T64	1		T265	1		T266	2
class_index[0x1]	intr_timeout_cnt[8]	2	1			T219	1		T228	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T267	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	21	1			T31	1		T74	3		T75	2
class_index[0x2]	intr_timeout_cnt[1]	13	1			T70	1		T26	1		T98	1
class_index[0x2]	intr_timeout_cnt[2]	2	1			T77	1		T78	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	8	1			T14	1		T74	1		T268	2
class_index[0x2]	intr_timeout_cnt[5]	3	1			T53	1		T256	1		T269	1
class_index[0x2]	intr_timeout_cnt[6]	9	1			T17	1		T77	1		T219	4
class_index[0x2]	intr_timeout_cnt[7]	2	1			T14	1		T255	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	4	1			T41	1		T74	1		T270	2
class_index[0x2]	intr_timeout_cnt[9]	3	1			T254	1		T230	1		T271	1
class_index[0x3]	intr_timeout_cnt[0]	18	1			T49	1		T37	1		T74	1
class_index[0x3]	intr_timeout_cnt[1]	19	1			T5	3		T14	2		T41	1
class_index[0x3]	intr_timeout_cnt[2]	2	1			T254	1		T269	1		-	-
class_index[0x3]	intr_timeout_cnt[3]	2	1			T272	1		T228	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	3	1			T14	1		T26	1		T273	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T267	1		T274	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T73	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T230	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	4	1			T74	1		T75	1		T229	1