Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	363776	1			T1	1291		T2	11		T3	47
all_values[1]	363776	1			T1	1291		T2	11		T3	47
all_values[2]	363776	1			T1	1291		T2	11		T3	47
all_values[3]	363776	1			T1	1291		T2	11		T3	47

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

723206

1

T1

2605

T2

24

T5

56

auto[1]

731898

1

T1

2559

T2

20

T3

188

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

864701

1

T1

2610

T2

26

T3

164

auto[1]

590403

1

T1

2554

T2

18

T3

24

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	104377	1			T1	320		T2	5		T5	5
all_values[0]	auto[0]	auto[1]	76357	1			T1	309		T2	4		T5	5
all_values[0]	auto[1]	auto[0]	106043	1			T1	332		T2	1		T3	44
all_values[0]	auto[1]	auto[1]	76999	1			T1	330		T2	1		T3	3
all_values[1]	auto[0]	auto[0]	107909	1			T1	337		T2	2		T5	10
all_values[1]	auto[0]	auto[1]	73794	1			T1	325		T2	2		T5	9
all_values[1]	auto[1]	auto[0]	108341	1			T1	327		T2	5		T3	40
all_values[1]	auto[1]	auto[1]	73732	1			T1	302		T2	2		T3	7
all_values[2]	auto[0]	auto[0]	109913	1			T1	339		T2	3		T5	6
all_values[2]	auto[0]	auto[1]	70626	1			T1	337		T2	2		T5	6
all_values[2]	auto[1]	auto[0]	112164	1			T1	308		T2	4		T3	47
all_values[2]	auto[1]	auto[1]	71073	1			T1	307		T2	2		T5	9
all_values[3]	auto[0]	auto[0]	106827	1			T1	319		T2	3		T5	8
all_values[3]	auto[0]	auto[1]	73403	1			T1	319		T2	3		T5	7
all_values[3]	auto[1]	auto[0]	109127	1			T1	328		T2	3		T3	33
all_values[3]	auto[1]	auto[1]	74419	1			T1	325		T2	2		T3	14