Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	363776	1			T1	1291		T2	11		T3	47
all_pins[1]	363776	1			T1	1291		T2	11		T3	47
all_pins[2]	363776	1			T1	1291		T2	11		T3	47
all_pins[3]	363776	1			T1	1291		T2	11		T3	47

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1158881	1			T1	3900		T2	37		T3	164
values[0x1]	296223	1			T1	1264		T2	7		T3	24
transitions[0x0=>0x1]	196220	1			T1	807		T2	5		T3	23
transitions[0x1=>0x0]	196477	1			T1	808		T2	5		T3	24

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	286777	1			T1	961		T2	10		T3	44
all_pins[0]	values[0x1]	76999	1			T1	330		T2	1		T3	3
all_pins[0]	transitions[0x0=>0x1]	76264	1			T1	329		T2	1		T3	2
all_pins[0]	transitions[0x1=>0x0]	73941	1			T1	325		T2	2		T3	14
all_pins[1]	values[0x0]	290044	1			T1	989		T2	9		T3	40
all_pins[1]	values[0x1]	73732	1			T1	302		T2	2		T3	7
all_pins[1]	transitions[0x0=>0x1]	39938	1			T1	148		T2	1		T3	7
all_pins[1]	transitions[0x1=>0x0]	43205	1			T1	176		T3	3		T5	4
all_pins[2]	values[0x0]	292703	1			T1	984		T2	9		T3	47
all_pins[2]	values[0x1]	71073	1			T1	307		T2	2		T5	9
all_pins[2]	transitions[0x0=>0x1]	38473	1			T1	157		T2	1		T5	5
all_pins[2]	transitions[0x1=>0x0]	41132	1			T1	152		T2	1		T3	7
all_pins[3]	values[0x0]	289357	1			T1	966		T2	9		T3	33
all_pins[3]	values[0x1]	74419	1			T1	325		T2	2		T3	14
all_pins[3]	transitions[0x0=>0x1]	41545	1			T1	173		T2	2		T3	14
all_pins[3]	transitions[0x1=>0x0]	38199	1			T1	155		T2	2		T5	5