Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287	1			T149	7		T150	7		T216	4
all_values[1]	287	1			T149	7		T150	7		T216	4
all_values[2]	287	1			T149	7		T150	7		T216	4
all_values[3]	287	1			T149	7		T150	7		T216	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

605

1

T149

6

T150

11

T216

12

auto[1]

543

1

T149

22

T150

17

T216

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

457

1

T149

6

T150

7

T216

7

auto[1]

691

1

T149

22

T150

21

T216

9

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

682

1

T149

14

T150

17

T216

11

auto[1]

466

1

T149

14

T150

11

T216

5

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

60

1

T149

1

T216

2

T335

1

all_values[0]

auto[0]

auto[0]

auto[1]

21

1

T150

1

T336

2

T337

1

all_values[0]

auto[0]

auto[1]

auto[0]

51

1

T150

1

T335

1

T338

2

all_values[0]

auto[0]

auto[1]

auto[1]

33

1

T149

4

T150

1

T216

1

all_values[0]

auto[1]

auto[0]

auto[1]

63

1

T150

1

T216

1

T335

2

all_values[0]

auto[1]

auto[1]

auto[1]

59

1

T149

2

T150

3

T335

2

all_values[1]

auto[0]

auto[0]

auto[0]

54

1

T149

1

T150

2

T216

2

all_values[1]

auto[0]

auto[0]

auto[1]

36

1

T150

1

T216

1

T335

2

all_values[1]

auto[0]

auto[1]

auto[0]

44

1

T149

3

T150

1

T339

2

all_values[1]

auto[0]

auto[1]

auto[1]

30

1

T150

2

T338

1

T340

1

all_values[1]

auto[1]

auto[0]

auto[1]

72

1

T149

1

T216

1

T335

2

all_values[1]

auto[1]

auto[1]

auto[1]

51

1

T149

2

T150

1

T338

1

all_values[2]

auto[0]

auto[0]

auto[0]

80

1

T216

1

T335

2

T338

4

all_values[2]

auto[0]

auto[0]

auto[1]

18

1

T216

1

T338

2

T340

1

all_values[2]

auto[0]

auto[1]

auto[0]

57

1

T216

1

T335

1

T340

2

all_values[2]

auto[0]

auto[1]

auto[1]

27

1

T149

3

T150

3

T335

1

all_values[2]

auto[1]

auto[0]

auto[1]

49

1

T149

2

T150

2

T338

1

all_values[2]

auto[1]

auto[1]

auto[1]

56

1

T149

2

T150

2

T216

1

all_values[3]

auto[0]

auto[0]

auto[0]

67

1

T150

2

T216

1

T335

1

all_values[3]

auto[0]

auto[0]

auto[1]

29

1

T150

1

T335

1

T339

2

all_values[3]

auto[0]

auto[1]

auto[0]

44

1

T149

1

T150

1

T340

1

all_values[3]

auto[0]

auto[1]

auto[1]

31

1

T149

1

T150

1

T216

1

all_values[3]

auto[1]

auto[0]

auto[1]

56

1

T149

1

T150

1

T216

2

all_values[3]

auto[1]

auto[1]

auto[1]

60

1

T149

4

T150

1

T335

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal