Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	90333	1			T1	1020		T4	445		T8	652
accum_cnt_1000	212387	1			T1	1675		T4	402		T8	574
accum_cnt_100	26114	1			T1	105		T4	28		T8	27
accum_cnt_50	66866	1			T1	81		T3	9		T4	1980
accum_cnt_10	214696	1			T1	27		T2	20		T3	24
accum_cnt_0	417942	1			T1	992		T2	20		T3	111

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	268999	1			T1	975		T2	10		T3	36
class_index[0x1]	268999	1			T1	975		T2	10		T3	36
class_index[0x2]	268999	1			T1	975		T2	10		T3	36
class_index[0x3]	268999	1			T1	975		T2	10		T3	36

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	24670	1			T1	419		T20	607		T26	276
class_index[0x0]	accum_cnt_1000	57895	1			T1	484		T14	563		T20	568
class_index[0x0]	accum_cnt_100	6967	1			T1	35		T14	42		T20	55
class_index[0x0]	accum_cnt_50	19823	1			T1	23		T4	981		T17	6
class_index[0x0]	accum_cnt_10	48046	1			T1	10		T2	8		T5	5
class_index[0x0]	accum_cnt_0	96523	1			T1	4		T2	2		T3	36
class_index[0x1]	accum_cnt_2000	19212	1			T1	167		T8	497		T20	393
class_index[0x1]	accum_cnt_1000	52953	1			T1	724		T8	469		T20	851
class_index[0x1]	accum_cnt_100	7496	1			T1	40		T8	22		T14	17
class_index[0x1]	accum_cnt_50	18171	1			T1	35		T3	9		T17	5
class_index[0x1]	accum_cnt_10	56286	1			T1	3		T2	5		T3	24
class_index[0x1]	accum_cnt_0	102132	1			T1	6		T2	5		T3	3
class_index[0x2]	accum_cnt_2000	20234	1			T14	217		T20	629		T48	212
class_index[0x2]	accum_cnt_1000	47348	1			T14	223		T20	616		T7	751
class_index[0x2]	accum_cnt_100	5595	1			T14	25		T20	71		T7	53
class_index[0x2]	accum_cnt_50	13928	1			T4	981		T14	63		T20	60
class_index[0x2]	accum_cnt_10	56630	1			T5	3		T4	10		T17	7
class_index[0x2]	accum_cnt_0	115571	1			T1	975		T2	10		T3	36
class_index[0x3]	accum_cnt_2000	26217	1			T1	434		T4	445		T8	155
class_index[0x3]	accum_cnt_1000	54191	1			T1	467		T4	402		T8	105
class_index[0x3]	accum_cnt_100	6056	1			T1	30		T4	28		T8	5
class_index[0x3]	accum_cnt_50	14944	1			T1	23		T4	18		T8	10
class_index[0x3]	accum_cnt_10	53734	1			T1	14		T2	7		T5	23
class_index[0x3]	accum_cnt_0	103716	1			T1	7		T2	3		T3	36