Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2374	1			T10	2		T21	46		T48	129
alert[0x1]	3369	1			T8	172		T69	10		T21	34
alert[0x2]	6077	1			T26	2		T24	1		T281	2
alert[0x3]	13574	1			T14	5		T9	1		T10	2
alert[0x4]	11074	1			T69	22		T45	8		T47	28
alert[0x5]	5495	1			T14	15		T20	73		T69	33
alert[0x6]	2851	1			T20	2		T217	2		T45	5
alert[0x7]	3147	1			T14	6		T20	40		T9	1
alert[0x8]	3343	1			T20	1		T9	1		T48	588
alert[0x9]	18580	1			T69	1466		T48	152		T275	1
alert[0xa]	4423	1			T3	1		T8	202		T20	3
alert[0xb]	5184	1			T8	27		T10	1		T21	267
alert[0xc]	10766	1			T8	709		T20	2		T21	15
alert[0xd]	6526	1			T3	1		T8	745		T14	4
alert[0xe]	3304	1			T3	2		T20	3		T68	25
alert[0xf]	7078	1			T8	13		T14	9		T9	1
alert[0x10]	8755	1			T8	116		T10	1		T47	6
alert[0x11]	11374	1			T8	7		T69	1		T47	37
alert[0x12]	10212	1			T8	16		T14	3		T9	1
alert[0x13]	4181	1			T3	1		T20	1		T9	1
alert[0x14]	1025	1			T8	3		T10	1		T45	2
alert[0x15]	6580	1			T20	3		T66	2		T89	10
alert[0x16]	8432	1			T3	1		T8	942		T69	174
alert[0x17]	3389	1			T9	1		T49	436		T68	181
alert[0x18]	13399	1			T8	93		T69	35		T51	284
alert[0x19]	6088	1			T8	29		T10	2		T69	618
alert[0x1a]	7300	1			T69	5		T47	5		T49	39
alert[0x1b]	11422	1			T8	76		T68	32		T89	43
alert[0x1c]	8125	1			T8	117		T14	3		T217	1
alert[0x1d]	5890	1			T3	1		T14	9		T20	2
alert[0x1e]	3317	1			T217	3		T21	6		T48	657
alert[0x1f]	9651	1			T20	1		T69	76		T217	1
alert[0x20]	9027	1			T14	9		T47	237		T68	70
alert[0x21]	14725	1			T69	22		T282	1		T89	7
alert[0x22]	6624	1			T14	30		T20	1		T60	1
alert[0x23]	7594	1			T8	298		T14	2		T69	2
alert[0x24]	5469	1			T8	133		T14	1		T42	3
alert[0x25]	5480	1			T3	1		T8	115		T21	45
alert[0x26]	3636	1			T8	527		T20	179		T69	54
alert[0x27]	2180	1			T14	5		T9	1		T69	63
alert[0x28]	6783	1			T8	253		T69	11		T49	140
alert[0x29]	3551	1			T9	1		T69	35		T42	2
alert[0x2a]	5545	1			T8	3379		T49	2		T62	1
alert[0x2b]	4341	1			T20	1		T21	1		T47	17
alert[0x2c]	5648	1			T21	8		T47	164		T68	653
alert[0x2d]	4632	1			T17	27		T8	128		T69	52
alert[0x2e]	11536	1			T8	38		T10	1		T48	48
alert[0x2f]	5850	1			T3	1		T49	468		T24	1
alert[0x30]	9391	1			T8	24		T20	5		T10	1
alert[0x31]	5316	1			T3	1		T8	22		T14	1
alert[0x32]	8148	1			T3	1		T20	5		T21	9
alert[0x33]	6048	1			T20	7		T69	102		T217	2
alert[0x34]	7225	1			T69	210		T217	1		T48	44
alert[0x35]	11329	1			T3	2		T69	73		T217	1
alert[0x36]	5700	1			T8	457		T14	1		T69	338
alert[0x37]	6009	1			T3	2		T14	1		T69	19
alert[0x38]	6379	1			T9	1		T69	189		T217	1
alert[0x39]	12961	1			T8	2138		T10	1		T217	1
alert[0x3a]	2806	1			T8	27		T14	1		T9	1
alert[0x3b]	5514	1			T8	30		T21	60		T47	74
alert[0x3c]	7838	1			T3	1		T8	17		T21	163
alert[0x3d]	3124	1			T17	3		T14	1		T69	11
alert[0x3e]	5314	1			T69	14		T45	13		T25	7
alert[0x3f]	3725	1			T8	821		T47	48		T48	90
alert[0x40]	12975	1			T8	24		T20	12		T45	4

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	104985	1			T3	3		T8	4		T14	49
class_i[0x1]	143905	1			T17	27		T14	44		T20	241
class_i[0x2]	99921	1			T17	3		T14	2		T20	70
class_i[0x3]	99917	1			T3	13		T8	11694		T14	11

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

448054

1

T17

30

T8

11698

T14

106

alert_ping_fail

674

1

T3

16

T9

12

T10

12

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2360	1			T21	46		T48	129		T68	7
alert_integrity_fail	alert[0x1]	3355	1			T8	172		T69	10		T21	34
alert_integrity_fail	alert[0x2]	6072	1			T26	2		T24	1		T281	2
alert_integrity_fail	alert[0x3]	13556	1			T14	5		T47	18		T49	24
alert_integrity_fail	alert[0x4]	11066	1			T69	22		T45	8		T47	28
alert_integrity_fail	alert[0x5]	5479	1			T14	15		T20	73		T69	33
alert_integrity_fail	alert[0x6]	2830	1			T20	2		T45	5		T48	322
alert_integrity_fail	alert[0x7]	3133	1			T14	6		T20	40		T69	57
alert_integrity_fail	alert[0x8]	3326	1			T20	1		T48	588		T24	2
alert_integrity_fail	alert[0x9]	18568	1			T69	1466		T48	152		T76	32
alert_integrity_fail	alert[0xa]	4414	1			T8	202		T20	3		T69	333
alert_integrity_fail	alert[0xb]	5173	1			T8	27		T21	267		T45	2
alert_integrity_fail	alert[0xc]	10755	1			T8	709		T20	2		T21	15
alert_integrity_fail	alert[0xd]	6519	1			T8	745		T14	4		T48	4
alert_integrity_fail	alert[0xe]	3295	1			T20	3		T68	25		T51	107
alert_integrity_fail	alert[0xf]	7070	1			T8	13		T14	9		T21	3
alert_integrity_fail	alert[0x10]	8744	1			T8	116		T47	6		T48	1997
alert_integrity_fail	alert[0x11]	11368	1			T8	7		T69	1		T47	37
alert_integrity_fail	alert[0x12]	10207	1			T8	16		T14	3		T48	2947
alert_integrity_fail	alert[0x13]	4168	1			T20	1		T69	176		T21	8
alert_integrity_fail	alert[0x14]	1013	1			T8	3		T45	2		T49	55
alert_integrity_fail	alert[0x15]	6567	1			T20	3		T66	2		T89	10
alert_integrity_fail	alert[0x16]	8423	1			T8	942		T69	174		T42	5
alert_integrity_fail	alert[0x17]	3377	1			T49	436		T68	181		T89	3
alert_integrity_fail	alert[0x18]	13392	1			T8	93		T69	35		T51	284
alert_integrity_fail	alert[0x19]	6074	1			T8	29		T69	618		T49	499
alert_integrity_fail	alert[0x1a]	7290	1			T69	5		T47	5		T49	39
alert_integrity_fail	alert[0x1b]	11412	1			T8	76		T68	32		T89	43
alert_integrity_fail	alert[0x1c]	8113	1			T8	117		T14	3		T48	9
alert_integrity_fail	alert[0x1d]	5875	1			T14	9		T20	2		T69	396
alert_integrity_fail	alert[0x1e]	3308	1			T21	6		T48	657		T49	73
alert_integrity_fail	alert[0x1f]	9640	1			T20	1		T69	76		T49	84
alert_integrity_fail	alert[0x20]	9018	1			T14	9		T47	237		T68	70
alert_integrity_fail	alert[0x21]	14715	1			T69	22		T89	7		T51	10
alert_integrity_fail	alert[0x22]	6612	1			T14	30		T20	1		T48	955
alert_integrity_fail	alert[0x23]	7590	1			T8	298		T14	2		T69	2
alert_integrity_fail	alert[0x24]	5464	1			T8	133		T14	1		T42	3
alert_integrity_fail	alert[0x25]	5470	1			T8	115		T21	45		T89	6
alert_integrity_fail	alert[0x26]	3628	1			T8	527		T20	179		T69	54
alert_integrity_fail	alert[0x27]	2175	1			T14	5		T69	63		T49	491
alert_integrity_fail	alert[0x28]	6764	1			T8	253		T69	11		T49	140
alert_integrity_fail	alert[0x29]	3536	1			T69	35		T42	2		T49	76
alert_integrity_fail	alert[0x2a]	5537	1			T8	3379		T49	2		T68	22
alert_integrity_fail	alert[0x2b]	4331	1			T20	1		T21	1		T47	17
alert_integrity_fail	alert[0x2c]	5637	1			T21	8		T47	164		T68	653
alert_integrity_fail	alert[0x2d]	4624	1			T17	27		T8	128		T69	52
alert_integrity_fail	alert[0x2e]	11524	1			T8	38		T48	48		T68	3328
alert_integrity_fail	alert[0x2f]	5837	1			T49	468		T24	1		T89	14
alert_integrity_fail	alert[0x30]	9385	1			T8	24		T20	5		T42	6
alert_integrity_fail	alert[0x31]	5301	1			T8	22		T14	1		T69	39
alert_integrity_fail	alert[0x32]	8133	1			T20	5		T21	9		T47	19
alert_integrity_fail	alert[0x33]	6042	1			T20	7		T69	102		T45	46
alert_integrity_fail	alert[0x34]	7217	1			T69	210		T48	44		T24	4
alert_integrity_fail	alert[0x35]	11314	1			T69	73		T45	5		T48	35
alert_integrity_fail	alert[0x36]	5692	1			T8	457		T14	1		T69	338
alert_integrity_fail	alert[0x37]	5994	1			T14	1		T69	19		T21	7
alert_integrity_fail	alert[0x38]	6369	1			T69	189		T45	9		T47	150
alert_integrity_fail	alert[0x39]	12952	1			T8	2138		T48	1		T24	8
alert_integrity_fail	alert[0x3a]	2800	1			T8	27		T14	1		T69	22
alert_integrity_fail	alert[0x3b]	5508	1			T8	30		T21	60		T47	74
alert_integrity_fail	alert[0x3c]	7828	1			T8	17		T21	163		T45	32
alert_integrity_fail	alert[0x3d]	3117	1			T17	3		T14	1		T69	11
alert_integrity_fail	alert[0x3e]	5305	1			T69	14		T45	13		T25	7
alert_integrity_fail	alert[0x3f]	3721	1			T8	821		T47	48		T48	90
alert_integrity_fail	alert[0x40]	12972	1			T8	24		T20	12		T45	4
alert_ping_fail	alert[0x0]	14	1			T10	2		T275	1		T283	1
alert_ping_fail	alert[0x1]	14	1			T62	1		T282	1		T275	1
alert_ping_fail	alert[0x2]	5	1			T284	1		T285	1		T286	1
alert_ping_fail	alert[0x3]	18	1			T9	1		T10	2		T287	1
alert_ping_fail	alert[0x4]	8	1			T103	1		T288	1		T289	1
alert_ping_fail	alert[0x5]	16	1			T283	1		T287	2		T288	1
alert_ping_fail	alert[0x6]	21	1			T217	2		T290	1		T277	1
alert_ping_fail	alert[0x7]	14	1			T9	1		T283	2		T286	1
alert_ping_fail	alert[0x8]	17	1			T9	1		T62	1		T283	1
alert_ping_fail	alert[0x9]	12	1			T275	1		T283	1		T287	1
alert_ping_fail	alert[0xa]	9	1			T3	1		T9	1		T291	1
alert_ping_fail	alert[0xb]	11	1			T10	1		T103	1		T288	1
alert_ping_fail	alert[0xc]	11	1			T62	1		T290	1		T287	1
alert_ping_fail	alert[0xd]	7	1			T3	1		T292	1		T291	1
alert_ping_fail	alert[0xe]	9	1			T3	2		T292	1		T293	1
alert_ping_fail	alert[0xf]	8	1			T9	1		T292	1		T103	1
alert_ping_fail	alert[0x10]	11	1			T10	1		T287	1		T284	1
alert_ping_fail	alert[0x11]	6	1			T292	1		T103	1		T291	1
alert_ping_fail	alert[0x12]	5	1			T9	1		T294	1		T285	1
alert_ping_fail	alert[0x13]	13	1			T3	1		T9	1		T62	1
alert_ping_fail	alert[0x14]	12	1			T10	1		T282	2		T288	1
alert_ping_fail	alert[0x15]	13	1			T295	1		T178	1		T296	1
alert_ping_fail	alert[0x16]	9	1			T3	1		T62	1		T297	1
alert_ping_fail	alert[0x17]	12	1			T9	1		T282	1		T283	1
alert_ping_fail	alert[0x18]	7	1			T287	1		T286	1		T298	1
alert_ping_fail	alert[0x19]	14	1			T10	2		T282	1		T291	2
alert_ping_fail	alert[0x1a]	10	1			T103	1		T287	1		T288	1
alert_ping_fail	alert[0x1b]	10	1			T291	2		T299	1		T300	1
alert_ping_fail	alert[0x1c]	12	1			T217	1		T275	1		T36	2
alert_ping_fail	alert[0x1d]	15	1			T3	1		T276	1		T291	1
alert_ping_fail	alert[0x1e]	9	1			T217	3		T301	1		T302	1
alert_ping_fail	alert[0x1f]	11	1			T217	1		T280	1		T288	1
alert_ping_fail	alert[0x20]	9	1			T103	1		T287	1		T288	1
alert_ping_fail	alert[0x21]	10	1			T282	1		T287	2		T288	1
alert_ping_fail	alert[0x22]	12	1			T60	1		T282	1		T288	1
alert_ping_fail	alert[0x23]	4	1			T303	1		T304	1		T305	1
alert_ping_fail	alert[0x24]	5	1			T217	1		T282	1		T103	1
alert_ping_fail	alert[0x25]	10	1			T3	1		T62	1		T306	1
alert_ping_fail	alert[0x26]	8	1			T217	1		T283	1		T307	1
alert_ping_fail	alert[0x27]	5	1			T9	1		T292	1		T288	1
alert_ping_fail	alert[0x28]	19	1			T292	1		T283	1		T287	1
alert_ping_fail	alert[0x29]	15	1			T9	1		T283	3		T288	1
alert_ping_fail	alert[0x2a]	8	1			T62	1		T279	1		T287	1
alert_ping_fail	alert[0x2b]	10	1			T294	1		T286	1		T302	2
alert_ping_fail	alert[0x2c]	11	1			T103	1		T284	1		T308	1
alert_ping_fail	alert[0x2d]	8	1			T291	1		T287	1		T293	1
alert_ping_fail	alert[0x2e]	12	1			T10	1		T282	1		T287	1
alert_ping_fail	alert[0x2f]	13	1			T3	1		T36	1		T292	1
alert_ping_fail	alert[0x30]	6	1			T10	1		T290	1		T309	1
alert_ping_fail	alert[0x31]	15	1			T3	1		T283	2		T301	1
alert_ping_fail	alert[0x32]	15	1			T3	1		T62	1		T289	1
alert_ping_fail	alert[0x33]	6	1			T217	2		T294	1		T214	1
alert_ping_fail	alert[0x34]	8	1			T217	1		T62	1		T293	1
alert_ping_fail	alert[0x35]	15	1			T3	2		T217	1		T103	1
alert_ping_fail	alert[0x36]	8	1			T62	1		T103	1		T294	1
alert_ping_fail	alert[0x37]	15	1			T3	2		T282	1		T283	1
alert_ping_fail	alert[0x38]	10	1			T9	1		T217	1		T287	1
alert_ping_fail	alert[0x39]	9	1			T10	1		T217	1		T62	1
alert_ping_fail	alert[0x3a]	6	1			T9	1		T292	1		T287	1
alert_ping_fail	alert[0x3b]	6	1			T284	1		T178	1		T310	2
alert_ping_fail	alert[0x3c]	10	1			T3	1		T285	1		T311	1
alert_ping_fail	alert[0x3d]	7	1			T217	1		T103	1		T303	1
alert_ping_fail	alert[0x3e]	9	1			T291	1		T284	1		T308	1
alert_ping_fail	alert[0x3f]	4	1			T297	1		T312	2		T302	1
alert_ping_fail	alert[0x40]	3	1			T62	1		T313	1		T314	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	104805	1			T8	4		T14	49		T20	28
alert_integrity_fail	class_i[0x1]	143804	1			T17	27		T14	44		T20	241
alert_integrity_fail	class_i[0x2]	99765	1			T17	3		T14	2		T20	70
alert_integrity_fail	class_i[0x3]	99680	1			T8	11694		T14	11		T20	2
alert_ping_fail	class_i[0x0]	180	1			T3	3		T10	1		T217	15
alert_ping_fail	class_i[0x1]	101	1			T10	1		T60	1		T217	1
alert_ping_fail	class_i[0x2]	156	1			T10	10		T36	3		T292	10
alert_ping_fail	class_i[0x3]	237	1			T3	13		T9	12		T62	1