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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.71 100.00 100.00 100.00 99.38 99.52


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T768 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2187419275 Jul 15 07:18:38 PM PDT 24 Jul 15 07:20:16 PM PDT 24 252583474 ps
T769 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3292107737 Jul 15 07:18:40 PM PDT 24 Jul 15 07:20:15 PM PDT 24 93824361 ps
T770 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3324666038 Jul 15 07:19:00 PM PDT 24 Jul 15 07:20:16 PM PDT 24 10536443 ps
T771 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2023535984 Jul 15 07:18:20 PM PDT 24 Jul 15 07:20:20 PM PDT 24 703476742 ps
T772 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2743928452 Jul 15 07:18:49 PM PDT 24 Jul 15 07:20:13 PM PDT 24 8578330 ps
T773 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4014809007 Jul 15 07:18:37 PM PDT 24 Jul 15 07:20:09 PM PDT 24 19116886 ps
T774 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1917185461 Jul 15 07:17:58 PM PDT 24 Jul 15 07:19:55 PM PDT 24 130083064 ps
T775 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1073760684 Jul 15 07:18:48 PM PDT 24 Jul 15 07:20:13 PM PDT 24 7434022 ps
T142 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2573685557 Jul 15 07:17:47 PM PDT 24 Jul 15 07:37:29 PM PDT 24 30135035919 ps
T776 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2773745529 Jul 15 07:17:58 PM PDT 24 Jul 15 07:19:45 PM PDT 24 64550932 ps
T161 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1708323018 Jul 15 07:17:41 PM PDT 24 Jul 15 07:19:52 PM PDT 24 51119158 ps
T140 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4024749536 Jul 15 07:17:42 PM PDT 24 Jul 15 07:38:10 PM PDT 24 24808220290 ps
T777 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3860898065 Jul 15 07:17:55 PM PDT 24 Jul 15 07:20:05 PM PDT 24 250671662 ps
T778 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.554081075 Jul 15 07:18:40 PM PDT 24 Jul 15 07:20:08 PM PDT 24 8152398 ps
T779 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2697754414 Jul 15 07:18:11 PM PDT 24 Jul 15 07:20:13 PM PDT 24 4718328809 ps
T153 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1534308803 Jul 15 07:18:20 PM PDT 24 Jul 15 07:20:28 PM PDT 24 464843143 ps
T780 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2372762772 Jul 15 07:17:45 PM PDT 24 Jul 15 07:26:55 PM PDT 24 17793422677 ps
T134 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2462938637 Jul 15 07:18:00 PM PDT 24 Jul 15 07:30:30 PM PDT 24 8838066178 ps
T781 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3605925566 Jul 15 07:18:03 PM PDT 24 Jul 15 07:19:52 PM PDT 24 103969342 ps
T132 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2715433208 Jul 15 07:18:36 PM PDT 24 Jul 15 07:25:46 PM PDT 24 10017709698 ps
T782 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.884754487 Jul 15 07:18:43 PM PDT 24 Jul 15 07:20:12 PM PDT 24 36725842 ps
T783 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3673898295 Jul 15 07:18:31 PM PDT 24 Jul 15 07:20:13 PM PDT 24 132408062 ps
T784 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4192943616 Jul 15 07:17:44 PM PDT 24 Jul 15 07:19:38 PM PDT 24 942727972 ps
T785 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3498093562 Jul 15 07:17:39 PM PDT 24 Jul 15 07:19:56 PM PDT 24 384962064 ps
T158 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3086321388 Jul 15 07:18:14 PM PDT 24 Jul 15 07:19:59 PM PDT 24 61608680 ps
T786 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2961438855 Jul 15 07:18:44 PM PDT 24 Jul 15 07:20:14 PM PDT 24 108987721 ps
T787 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3364343619 Jul 15 07:18:21 PM PDT 24 Jul 15 07:20:12 PM PDT 24 661438393 ps
T788 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1335235549 Jul 15 07:17:42 PM PDT 24 Jul 15 07:20:31 PM PDT 24 3485617220 ps
T789 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1699019588 Jul 15 07:18:48 PM PDT 24 Jul 15 07:20:11 PM PDT 24 14673314 ps
T790 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1509119338 Jul 15 07:18:44 PM PDT 24 Jul 15 07:21:43 PM PDT 24 942987060 ps
T791 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2749800355 Jul 15 07:18:19 PM PDT 24 Jul 15 07:20:00 PM PDT 24 9996376 ps
T792 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.698177078 Jul 15 07:18:55 PM PDT 24 Jul 15 07:20:22 PM PDT 24 15532197 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.574319315 Jul 15 07:17:55 PM PDT 24 Jul 15 07:20:12 PM PDT 24 200004173 ps
T794 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1057184718 Jul 15 07:17:52 PM PDT 24 Jul 15 07:19:48 PM PDT 24 211726439 ps
T795 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1343192860 Jul 15 07:18:38 PM PDT 24 Jul 15 07:20:11 PM PDT 24 67210874 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1086881690 Jul 15 07:17:41 PM PDT 24 Jul 15 07:24:12 PM PDT 24 4033393280 ps
T797 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2930893707 Jul 15 07:18:14 PM PDT 24 Jul 15 07:20:01 PM PDT 24 363504335 ps
T798 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1851468478 Jul 15 07:18:10 PM PDT 24 Jul 15 07:20:00 PM PDT 24 10984980 ps
T799 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1331536707 Jul 15 07:18:49 PM PDT 24 Jul 15 07:20:14 PM PDT 24 13244680 ps
T800 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.261096429 Jul 15 07:17:58 PM PDT 24 Jul 15 07:19:57 PM PDT 24 1020270466 ps
T801 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2306638005 Jul 15 07:18:48 PM PDT 24 Jul 15 07:20:18 PM PDT 24 98430399 ps
T802 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4087627599 Jul 15 07:18:41 PM PDT 24 Jul 15 07:20:10 PM PDT 24 14040423 ps
T803 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2434096882 Jul 15 07:18:29 PM PDT 24 Jul 15 07:20:10 PM PDT 24 145034577 ps
T804 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3955070678 Jul 15 07:17:42 PM PDT 24 Jul 15 07:20:11 PM PDT 24 57376317 ps
T805 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3692987348 Jul 15 07:17:48 PM PDT 24 Jul 15 07:19:57 PM PDT 24 14955463 ps
T806 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3828633282 Jul 15 07:18:18 PM PDT 24 Jul 15 07:20:34 PM PDT 24 503463348 ps
T807 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.586072235 Jul 15 07:18:31 PM PDT 24 Jul 15 07:20:12 PM PDT 24 267173688 ps
T141 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.766903550 Jul 15 07:18:49 PM PDT 24 Jul 15 07:40:39 PM PDT 24 19278490052 ps
T808 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1281907635 Jul 15 07:18:12 PM PDT 24 Jul 15 07:20:15 PM PDT 24 2791770954 ps
T809 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1123667547 Jul 15 07:17:41 PM PDT 24 Jul 15 07:20:00 PM PDT 24 25109504 ps
T810 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1629357577 Jul 15 07:17:42 PM PDT 24 Jul 15 07:22:08 PM PDT 24 8027134962 ps
T811 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3036198507 Jul 15 07:19:01 PM PDT 24 Jul 15 07:20:16 PM PDT 24 19927782 ps
T812 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3984723090 Jul 15 07:17:53 PM PDT 24 Jul 15 07:19:46 PM PDT 24 136457018 ps
T813 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.158280932 Jul 15 07:17:53 PM PDT 24 Jul 15 07:19:52 PM PDT 24 242301347 ps
T814 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3324791315 Jul 15 07:18:49 PM PDT 24 Jul 15 07:20:14 PM PDT 24 10784703 ps
T815 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2473232938 Jul 15 07:18:54 PM PDT 24 Jul 15 07:20:21 PM PDT 24 9897051 ps
T816 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1541169577 Jul 15 07:17:57 PM PDT 24 Jul 15 07:27:23 PM PDT 24 10235442854 ps
T139 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.791037470 Jul 15 07:18:30 PM PDT 24 Jul 15 07:34:31 PM PDT 24 51180034271 ps
T154 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3417912165 Jul 15 07:18:02 PM PDT 24 Jul 15 07:20:56 PM PDT 24 1052132670 ps
T159 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3013648944 Jul 15 07:18:35 PM PDT 24 Jul 15 07:20:14 PM PDT 24 195376482 ps
T817 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1537094907 Jul 15 07:18:54 PM PDT 24 Jul 15 07:20:14 PM PDT 24 14882201 ps
T143 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.521601218 Jul 15 07:18:03 PM PDT 24 Jul 15 07:24:22 PM PDT 24 2320299414 ps
T818 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2242493814 Jul 15 07:19:02 PM PDT 24 Jul 15 07:20:17 PM PDT 24 10258999 ps
T819 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4276976933 Jul 15 07:18:09 PM PDT 24 Jul 15 07:20:13 PM PDT 24 123569013 ps
T144 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3039741323 Jul 15 07:18:20 PM PDT 24 Jul 15 07:24:22 PM PDT 24 8025198673 ps
T820 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3864130503 Jul 15 07:17:54 PM PDT 24 Jul 15 07:20:09 PM PDT 24 1542341909 ps
T821 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3925771987 Jul 15 07:17:46 PM PDT 24 Jul 15 07:19:34 PM PDT 24 81538640 ps
T163 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.812439779 Jul 15 07:17:47 PM PDT 24 Jul 15 07:20:15 PM PDT 24 1166697169 ps
T822 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1530020003 Jul 15 07:18:16 PM PDT 24 Jul 15 07:20:02 PM PDT 24 32676826 ps
T152 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3814968821 Jul 15 07:18:41 PM PDT 24 Jul 15 07:20:12 PM PDT 24 205981854 ps
T823 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3115026066 Jul 15 07:18:10 PM PDT 24 Jul 15 07:20:00 PM PDT 24 598266526 ps
T824 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.117120718 Jul 15 07:17:42 PM PDT 24 Jul 15 07:19:55 PM PDT 24 77834845 ps
T825 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1949902922 Jul 15 07:18:53 PM PDT 24 Jul 15 07:20:14 PM PDT 24 12272356 ps
T137 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3337752295 Jul 15 07:17:54 PM PDT 24 Jul 15 07:22:20 PM PDT 24 9252231926 ps
T826 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3543973388 Jul 15 07:18:03 PM PDT 24 Jul 15 07:19:54 PM PDT 24 98130128 ps
T827 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3754054559 Jul 15 07:18:21 PM PDT 24 Jul 15 07:20:13 PM PDT 24 85340564 ps
T828 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3527315305 Jul 15 07:18:46 PM PDT 24 Jul 15 07:20:21 PM PDT 24 386602898 ps
T160 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2586095095 Jul 15 07:18:23 PM PDT 24 Jul 15 07:20:05 PM PDT 24 59881270 ps
T829 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1538802056 Jul 15 07:18:43 PM PDT 24 Jul 15 07:20:10 PM PDT 24 10731789 ps
T830 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.377637074 Jul 15 07:18:47 PM PDT 24 Jul 15 07:25:17 PM PDT 24 30634701226 ps
T831 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.869738292 Jul 15 07:18:54 PM PDT 24 Jul 15 07:20:22 PM PDT 24 10426520 ps

Test location /workspace/coverage/default/33.alert_handler_stress_all.3204302964
Short name T14
Test name
Test status
Simulation time 107837618749 ps
CPU time 1876.9 seconds
Started Jul 15 05:16:15 PM PDT 24
Finished Jul 15 05:47:32 PM PDT 24
Peak memory 282064 kb
Host smart-816c063d-aca2-481e-b775-f8b4c935c673
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204302964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3204302964
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1647909058
Short name T21
Test name
Test status
Simulation time 76591672064 ps
CPU time 4985.46 seconds
Started Jul 15 05:12:24 PM PDT 24
Finished Jul 15 06:35:31 PM PDT 24
Peak memory 290328 kb
Host smart-332e39fe-0979-43ac-bc2d-d9a14bd7b50e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647909058 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1647909058
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3957185291
Short name T12
Test name
Test status
Simulation time 1318530099 ps
CPU time 21.26 seconds
Started Jul 15 05:11:38 PM PDT 24
Finished Jul 15 05:12:00 PM PDT 24
Peak memory 267596 kb
Host smart-428ff88d-f529-4573-bcbc-ff9c5d60e831
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3957185291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3957185291
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1984727670
Short name T1
Test name
Test status
Simulation time 55248058421 ps
CPU time 1731.01 seconds
Started Jul 15 05:14:28 PM PDT 24
Finished Jul 15 05:43:20 PM PDT 24
Peak memory 282936 kb
Host smart-6cb9c876-2ebf-4fbf-96dd-e1260d6b4b43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984727670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1984727670
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.24621144
Short name T145
Test name
Test status
Simulation time 3958976613 ps
CPU time 39.79 seconds
Started Jul 15 07:18:19 PM PDT 24
Finished Jul 15 07:20:39 PM PDT 24
Peak memory 240516 kb
Host smart-226c2277-30c9-4216-8650-323e58bc35f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=24621144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.24621144
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3107037251
Short name T68
Test name
Test status
Simulation time 42036251273 ps
CPU time 2595 seconds
Started Jul 15 05:11:23 PM PDT 24
Finished Jul 15 05:54:42 PM PDT 24
Peak memory 287364 kb
Host smart-acae7e37-a1eb-401e-99b5-c1db1808c118
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107037251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3107037251
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2798474196
Short name T125
Test name
Test status
Simulation time 1854317975 ps
CPU time 230.74 seconds
Started Jul 15 07:18:03 PM PDT 24
Finished Jul 15 07:23:49 PM PDT 24
Peak memory 272864 kb
Host smart-37e7285c-05ef-48a4-824a-f066ecdfcca8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2798474196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2798474196
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3820414543
Short name T188
Test name
Test status
Simulation time 47485229068 ps
CPU time 5067.49 seconds
Started Jul 15 05:14:59 PM PDT 24
Finished Jul 15 06:39:28 PM PDT 24
Peak memory 338312 kb
Host smart-e6738e9d-2be0-4fd9-bbfb-9742e7560f99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820414543 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3820414543
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1062206016
Short name T248
Test name
Test status
Simulation time 910242612903 ps
CPU time 5920.44 seconds
Started Jul 15 05:18:19 PM PDT 24
Finished Jul 15 06:57:01 PM PDT 24
Peak memory 372108 kb
Host smart-e6caa480-3710-44f4-ad4c-b7db02149b44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062206016 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1062206016
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1962704337
Short name T60
Test name
Test status
Simulation time 57775546713 ps
CPU time 2400.67 seconds
Started Jul 15 05:15:47 PM PDT 24
Finished Jul 15 05:55:48 PM PDT 24
Peak memory 289688 kb
Host smart-33686753-eb12-4eea-84ba-631a89b79c63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962704337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1962704337
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2927935742
Short name T131
Test name
Test status
Simulation time 15769055273 ps
CPU time 1029.95 seconds
Started Jul 15 07:19:15 PM PDT 24
Finished Jul 15 07:37:31 PM PDT 24
Peak memory 265528 kb
Host smart-6e2461f6-caa0-457f-8c40-9b09d1a5f4b0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927935742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2927935742
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2981767811
Short name T76
Test name
Test status
Simulation time 70932233121 ps
CPU time 7882.25 seconds
Started Jul 15 05:16:49 PM PDT 24
Finished Jul 15 07:28:12 PM PDT 24
Peak memory 371200 kb
Host smart-0079272d-9ba1-4f25-a7ba-51c93be9729d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981767811 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2981767811
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.433636409
Short name T103
Test name
Test status
Simulation time 40877120368 ps
CPU time 430.01 seconds
Started Jul 15 05:16:32 PM PDT 24
Finished Jul 15 05:23:43 PM PDT 24
Peak memory 255600 kb
Host smart-af6d1a8b-cad0-4287-afca-d654116c60aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433636409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.433636409
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3274585479
Short name T112
Test name
Test status
Simulation time 8428810777 ps
CPU time 295.44 seconds
Started Jul 15 07:17:48 PM PDT 24
Finished Jul 15 07:24:54 PM PDT 24
Peak memory 266428 kb
Host smart-dfefa50e-70d8-467a-95eb-c811efac86e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3274585479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3274585479
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.848594521
Short name T119
Test name
Test status
Simulation time 132872208127 ps
CPU time 922.59 seconds
Started Jul 15 07:18:19 PM PDT 24
Finished Jul 15 07:35:22 PM PDT 24
Peak memory 273524 kb
Host smart-f36ff296-0b68-48dd-8d87-e449fd47d157
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848594521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.848594521
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3953159823
Short name T101
Test name
Test status
Simulation time 3158156502 ps
CPU time 49.44 seconds
Started Jul 15 05:10:49 PM PDT 24
Finished Jul 15 05:11:45 PM PDT 24
Peak memory 249408 kb
Host smart-64ee9a22-7fdf-4f05-8289-87ecc346843c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39531
59823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3953159823
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3740876045
Short name T279
Test name
Test status
Simulation time 44863300973 ps
CPU time 2695.16 seconds
Started Jul 15 05:16:51 PM PDT 24
Finished Jul 15 06:01:47 PM PDT 24
Peak memory 285836 kb
Host smart-a023d80f-85c3-49f7-b316-320688085732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740876045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3740876045
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.284050693
Short name T361
Test name
Test status
Simulation time 1297850356 ps
CPU time 16.85 seconds
Started Jul 15 05:11:09 PM PDT 24
Finished Jul 15 05:11:27 PM PDT 24
Peak memory 249168 kb
Host smart-2e9b7223-1e16-4897-8f4a-a65c59844691
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=284050693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.284050693
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1798538902
Short name T150
Test name
Test status
Simulation time 9526491 ps
CPU time 1.54 seconds
Started Jul 15 07:19:00 PM PDT 24
Finished Jul 15 07:20:17 PM PDT 24
Peak memory 236676 kb
Host smart-a3c1c154-2fdb-4d0b-bd85-a819f0de5b56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1798538902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1798538902
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.4261060463
Short name T114
Test name
Test status
Simulation time 12940586727 ps
CPU time 952.44 seconds
Started Jul 15 07:17:52 PM PDT 24
Finished Jul 15 07:35:37 PM PDT 24
Peak memory 272800 kb
Host smart-4bc8fd18-48c9-4707-98cd-580af7c90b9d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261060463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.4261060463
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1077327616
Short name T74
Test name
Test status
Simulation time 192073237937 ps
CPU time 3200.74 seconds
Started Jul 15 05:19:21 PM PDT 24
Finished Jul 15 06:12:43 PM PDT 24
Peak memory 306016 kb
Host smart-b311e7b6-b80c-431a-aaf2-bfd8782f8951
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077327616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1077327616
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2338984881
Short name T3
Test name
Test status
Simulation time 80570682728 ps
CPU time 594.65 seconds
Started Jul 15 05:15:47 PM PDT 24
Finished Jul 15 05:25:42 PM PDT 24
Peak memory 249316 kb
Host smart-1456f5cf-0271-403c-951e-2603d9a13c40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338984881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2338984881
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2157342732
Short name T323
Test name
Test status
Simulation time 187472984658 ps
CPU time 2764.49 seconds
Started Jul 15 05:11:29 PM PDT 24
Finished Jul 15 05:57:35 PM PDT 24
Peak memory 281992 kb
Host smart-698c8a76-502a-48e6-8505-b053ec1d229e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157342732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2157342732
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.66973870
Short name T116
Test name
Test status
Simulation time 17218938018 ps
CPU time 357.62 seconds
Started Jul 15 07:18:40 PM PDT 24
Finished Jul 15 07:26:05 PM PDT 24
Peak memory 265428 kb
Host smart-145c9fd8-ba08-4f4e-8a79-24f2ff2037d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=66973870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_error
s.66973870
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.743504019
Short name T286
Test name
Test status
Simulation time 16117963498 ps
CPU time 518.85 seconds
Started Jul 15 05:18:54 PM PDT 24
Finished Jul 15 05:27:33 PM PDT 24
Peak memory 256308 kb
Host smart-524bcd5c-5934-4873-b6f3-82775060f9ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743504019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.743504019
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3479168332
Short name T113
Test name
Test status
Simulation time 5332881587 ps
CPU time 567.47 seconds
Started Jul 15 07:18:46 PM PDT 24
Finished Jul 15 07:29:37 PM PDT 24
Peak memory 265384 kb
Host smart-0dc02f23-2336-43e2-8b46-c67dafa4944a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479168332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3479168332
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1508508452
Short name T320
Test name
Test status
Simulation time 472327969567 ps
CPU time 2069.48 seconds
Started Jul 15 05:15:33 PM PDT 24
Finished Jul 15 05:50:03 PM PDT 24
Peak memory 273872 kb
Host smart-08d6c726-a03b-4d49-9247-83659732088d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508508452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1508508452
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.4134508772
Short name T217
Test name
Test status
Simulation time 12436644144 ps
CPU time 460.46 seconds
Started Jul 15 05:14:59 PM PDT 24
Finished Jul 15 05:22:40 PM PDT 24
Peak memory 249364 kb
Host smart-9226e206-1b64-4851-93c1-310b9809e0db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134508772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.4134508772
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1105696198
Short name T51
Test name
Test status
Simulation time 69373197942 ps
CPU time 1622.54 seconds
Started Jul 15 05:12:42 PM PDT 24
Finished Jul 15 05:39:46 PM PDT 24
Peak memory 290224 kb
Host smart-c97bb882-b63a-473c-adf4-12bcff92afdd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105696198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1105696198
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.4010632333
Short name T77
Test name
Test status
Simulation time 29694040545 ps
CPU time 3072.98 seconds
Started Jul 15 05:16:31 PM PDT 24
Finished Jul 15 06:07:45 PM PDT 24
Peak memory 338996 kb
Host smart-103247b4-e9a8-4f3e-ab33-a53aca89b335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010632333 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.4010632333
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1968374671
Short name T122
Test name
Test status
Simulation time 17813017053 ps
CPU time 342.84 seconds
Started Jul 15 07:19:10 PM PDT 24
Finished Jul 15 07:26:02 PM PDT 24
Peak memory 271824 kb
Host smart-4a8c0343-a6f5-426f-b6d9-f3ef48b9b041
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1968374671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1968374671
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.791037470
Short name T139
Test name
Test status
Simulation time 51180034271 ps
CPU time 867.4 seconds
Started Jul 15 07:18:30 PM PDT 24
Finished Jul 15 07:34:31 PM PDT 24
Peak memory 265364 kb
Host smart-c918200a-39f4-4c80-a7f7-d0fa8c4ba481
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791037470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.791037470
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1289344208
Short name T280
Test name
Test status
Simulation time 88651453352 ps
CPU time 1634.79 seconds
Started Jul 15 05:10:59 PM PDT 24
Finished Jul 15 05:38:14 PM PDT 24
Peak memory 289396 kb
Host smart-3652acbd-29b0-4c69-847b-acc64f35c4aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289344208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1289344208
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3107061989
Short name T299
Test name
Test status
Simulation time 44314809592 ps
CPU time 376.78 seconds
Started Jul 15 05:11:11 PM PDT 24
Finished Jul 15 05:17:29 PM PDT 24
Peak memory 249276 kb
Host smart-53404261-8e13-4720-ae38-88eb54247272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107061989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3107061989
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2916933332
Short name T31
Test name
Test status
Simulation time 334493177842 ps
CPU time 5591.98 seconds
Started Jul 15 05:17:03 PM PDT 24
Finished Jul 15 06:50:16 PM PDT 24
Peak memory 322556 kb
Host smart-19398453-c426-489b-8177-5a7aec9a17d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916933332 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2916933332
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1941044552
Short name T26
Test name
Test status
Simulation time 61453325713 ps
CPU time 3560.36 seconds
Started Jul 15 05:18:35 PM PDT 24
Finished Jul 15 06:17:56 PM PDT 24
Peak memory 289636 kb
Host smart-9dbf148e-4d20-4290-b8e2-f26f9726e478
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941044552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1941044552
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1016153609
Short name T216
Test name
Test status
Simulation time 7366656 ps
CPU time 1.51 seconds
Started Jul 15 07:18:20 PM PDT 24
Finished Jul 15 07:20:05 PM PDT 24
Peak memory 237560 kb
Host smart-11535fad-3e46-472e-b119-189581a56755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1016153609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1016153609
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.408871646
Short name T234
Test name
Test status
Simulation time 32000428777 ps
CPU time 945.87 seconds
Started Jul 15 05:11:24 PM PDT 24
Finished Jul 15 05:27:13 PM PDT 24
Peak memory 273868 kb
Host smart-8df66fff-92e1-4f5c-a2a5-1dea2eec8a65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408871646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.408871646
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2165575071
Short name T333
Test name
Test status
Simulation time 139118869778 ps
CPU time 2499.94 seconds
Started Jul 15 05:14:21 PM PDT 24
Finished Jul 15 05:56:02 PM PDT 24
Peak memory 289472 kb
Host smart-3faf4d9b-cd7d-49d9-938e-c4beaaa6054e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165575071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2165575071
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3519223473
Short name T291
Test name
Test status
Simulation time 7614971100 ps
CPU time 316.61 seconds
Started Jul 15 05:16:07 PM PDT 24
Finished Jul 15 05:21:24 PM PDT 24
Peak memory 257356 kb
Host smart-f2d018c0-9e81-43e9-ac82-2c74624c26e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519223473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3519223473
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3646090704
Short name T254
Test name
Test status
Simulation time 197818668219 ps
CPU time 5319.96 seconds
Started Jul 15 05:13:56 PM PDT 24
Finished Jul 15 06:42:37 PM PDT 24
Peak memory 299924 kb
Host smart-9c0f4049-3a4b-4786-915c-1b0188910424
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646090704 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3646090704
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3086321388
Short name T158
Test name
Test status
Simulation time 61608680 ps
CPU time 3.1 seconds
Started Jul 15 07:18:14 PM PDT 24
Finished Jul 15 07:19:59 PM PDT 24
Peak memory 237572 kb
Host smart-7c18e647-7875-4232-bf29-07064ffcc1be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3086321388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3086321388
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2194435055
Short name T120
Test name
Test status
Simulation time 60299376487 ps
CPU time 1022.74 seconds
Started Jul 15 07:18:18 PM PDT 24
Finished Jul 15 07:37:02 PM PDT 24
Peak memory 272888 kb
Host smart-b5ba9082-9343-4c36-b2a6-f6212b191447
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194435055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2194435055
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.168265625
Short name T83
Test name
Test status
Simulation time 26759004381 ps
CPU time 1211.92 seconds
Started Jul 15 05:16:22 PM PDT 24
Finished Jul 15 05:36:35 PM PDT 24
Peak memory 273160 kb
Host smart-99816804-2ae7-4811-9543-6125cde04cba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168265625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.168265625
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2094431527
Short name T312
Test name
Test status
Simulation time 36153938601 ps
CPU time 444.32 seconds
Started Jul 15 05:17:39 PM PDT 24
Finished Jul 15 05:25:03 PM PDT 24
Peak memory 249256 kb
Host smart-ac8c5c17-bb95-454d-8bcb-b7b72fc150c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094431527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2094431527
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.791766582
Short name T194
Test name
Test status
Simulation time 55069812 ps
CPU time 4.07 seconds
Started Jul 15 05:10:59 PM PDT 24
Finished Jul 15 05:11:03 PM PDT 24
Peak memory 249504 kb
Host smart-b9de3985-1d61-45f4-b3bb-9e7055a525a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=791766582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.791766582
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3441255483
Short name T199
Test name
Test status
Simulation time 20665641 ps
CPU time 2.29 seconds
Started Jul 15 05:11:07 PM PDT 24
Finished Jul 15 05:11:11 PM PDT 24
Peak memory 249420 kb
Host smart-0560aeb4-fa1e-40db-8d5d-78fd66c776de
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3441255483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3441255483
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1653747653
Short name T196
Test name
Test status
Simulation time 46393441 ps
CPU time 2.61 seconds
Started Jul 15 05:13:02 PM PDT 24
Finished Jul 15 05:13:05 PM PDT 24
Peak memory 249408 kb
Host smart-74fad5cd-2a93-45c3-8a3f-924e62dc6637
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1653747653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1653747653
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.324681540
Short name T193
Test name
Test status
Simulation time 38669335 ps
CPU time 3.25 seconds
Started Jul 15 05:13:12 PM PDT 24
Finished Jul 15 05:13:16 PM PDT 24
Peak memory 249484 kb
Host smart-86356584-7b16-4aa4-9c8f-d5ddcae416a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=324681540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.324681540
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3876127839
Short name T305
Test name
Test status
Simulation time 22503695469 ps
CPU time 454.44 seconds
Started Jul 15 05:11:02 PM PDT 24
Finished Jul 15 05:18:37 PM PDT 24
Peak memory 249260 kb
Host smart-d5b28a83-9fa5-4dc8-84ff-5b4fbfa1b52c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876127839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3876127839
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2943986672
Short name T53
Test name
Test status
Simulation time 97467695427 ps
CPU time 2228.45 seconds
Started Jul 15 05:10:59 PM PDT 24
Finished Jul 15 05:48:08 PM PDT 24
Peak memory 314820 kb
Host smart-06d5455c-515b-408d-8747-d660197ce662
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943986672 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2943986672
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.276491998
Short name T274
Test name
Test status
Simulation time 96815350866 ps
CPU time 2958.36 seconds
Started Jul 15 05:12:57 PM PDT 24
Finished Jul 15 06:02:16 PM PDT 24
Peak memory 290124 kb
Host smart-6e150d30-d90d-46a1-a576-300f40ad21af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276491998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.276491998
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3103155036
Short name T81
Test name
Test status
Simulation time 927367744 ps
CPU time 63.36 seconds
Started Jul 15 05:13:43 PM PDT 24
Finished Jul 15 05:14:47 PM PDT 24
Peak memory 257400 kb
Host smart-a2b39a49-73b9-487a-9922-bcb60a130894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31031
55036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3103155036
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.854041746
Short name T177
Test name
Test status
Simulation time 77159162535 ps
CPU time 4197.92 seconds
Started Jul 15 05:14:59 PM PDT 24
Finished Jul 15 06:24:58 PM PDT 24
Peak memory 306656 kb
Host smart-2e315f2e-099a-456b-9fe1-6cfb111cde25
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854041746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.854041746
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3502530372
Short name T73
Test name
Test status
Simulation time 2745789195 ps
CPU time 93.52 seconds
Started Jul 15 05:15:17 PM PDT 24
Finished Jul 15 05:16:52 PM PDT 24
Peak memory 257528 kb
Host smart-e93ef559-f5e8-4ddb-9165-ecf8a423b27e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502530372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3502530372
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.938407968
Short name T228
Test name
Test status
Simulation time 56214723564 ps
CPU time 3324.35 seconds
Started Jul 15 05:11:37 PM PDT 24
Finished Jul 15 06:07:03 PM PDT 24
Peak memory 318152 kb
Host smart-cf930aab-be1c-44fc-ba90-7ee6c94e9b09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938407968 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.938407968
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.1456617529
Short name T9
Test name
Test status
Simulation time 39111563452 ps
CPU time 338.72 seconds
Started Jul 15 05:16:46 PM PDT 24
Finished Jul 15 05:22:25 PM PDT 24
Peak memory 249324 kb
Host smart-7463409c-fe01-42f4-8f2c-06097fc95295
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456617529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1456617529
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.198030012
Short name T276
Test name
Test status
Simulation time 231397956012 ps
CPU time 3358.53 seconds
Started Jul 15 05:18:54 PM PDT 24
Finished Jul 15 06:14:54 PM PDT 24
Peak memory 289968 kb
Host smart-4b686d11-9fea-4218-89d5-9811fbbbce3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198030012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.198030012
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2793238296
Short name T233
Test name
Test status
Simulation time 76428232229 ps
CPU time 1320.03 seconds
Started Jul 15 05:19:43 PM PDT 24
Finished Jul 15 05:41:44 PM PDT 24
Peak memory 289880 kb
Host smart-20ca6b5a-19fe-4de6-adbd-7cdd8eee3144
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793238296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2793238296
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.270420769
Short name T121
Test name
Test status
Simulation time 7378619059 ps
CPU time 103.62 seconds
Started Jul 15 07:18:29 PM PDT 24
Finished Jul 15 07:21:47 PM PDT 24
Peak memory 269452 kb
Host smart-5fae64ca-ed9b-41f5-a316-d531d6780605
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=270420769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.270420769
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2462938637
Short name T134
Test name
Test status
Simulation time 8838066178 ps
CPU time 649.03 seconds
Started Jul 15 07:18:00 PM PDT 24
Finished Jul 15 07:30:30 PM PDT 24
Peak memory 273572 kb
Host smart-1c89d25e-7563-4b25-b114-72a301c180f7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462938637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2462938637
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1950795308
Short name T245
Test name
Test status
Simulation time 6225516151 ps
CPU time 158.79 seconds
Started Jul 15 05:10:59 PM PDT 24
Finished Jul 15 05:13:39 PM PDT 24
Peak memory 257472 kb
Host smart-da0f93a9-d189-4d14-bd58-9cf45be813bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950795308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1950795308
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1273418430
Short name T486
Test name
Test status
Simulation time 469749512 ps
CPU time 28.57 seconds
Started Jul 15 05:12:57 PM PDT 24
Finished Jul 15 05:13:26 PM PDT 24
Peak memory 249164 kb
Host smart-c7dc7023-2dbf-493a-a16f-9ae0ec3257b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12734
18430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1273418430
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3875609693
Short name T62
Test name
Test status
Simulation time 33845046592 ps
CPU time 341.88 seconds
Started Jul 15 05:14:47 PM PDT 24
Finished Jul 15 05:20:30 PM PDT 24
Peak memory 249340 kb
Host smart-26235d2b-dbda-4eaa-bbb6-c8d211e831d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875609693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3875609693
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.3781909532
Short name T64
Test name
Test status
Simulation time 628480363 ps
CPU time 36.78 seconds
Started Jul 15 05:13:31 PM PDT 24
Finished Jul 15 05:14:09 PM PDT 24
Peak memory 248696 kb
Host smart-e34dae7c-14f7-427d-9b46-6969db5f17e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37819
09532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3781909532
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3382645882
Short name T239
Test name
Test status
Simulation time 205060560028 ps
CPU time 3133.77 seconds
Started Jul 15 05:14:13 PM PDT 24
Finished Jul 15 06:06:28 PM PDT 24
Peak memory 298484 kb
Host smart-5dada3a9-7625-4e6c-8140-930311d0b7a8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382645882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3382645882
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1929446567
Short name T58
Test name
Test status
Simulation time 37139032714 ps
CPU time 2313.03 seconds
Started Jul 15 05:14:33 PM PDT 24
Finished Jul 15 05:53:07 PM PDT 24
Peak memory 289004 kb
Host smart-84a381a2-61a1-4e87-8518-2ff1f79b7180
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929446567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1929446567
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.442053840
Short name T270
Test name
Test status
Simulation time 2078113018 ps
CPU time 29.59 seconds
Started Jul 15 05:15:17 PM PDT 24
Finished Jul 15 05:15:47 PM PDT 24
Peak memory 257444 kb
Host smart-1baadf4a-fe40-409c-9559-109b61c931ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44205
3840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.442053840
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.932641459
Short name T260
Test name
Test status
Simulation time 862176445 ps
CPU time 54.35 seconds
Started Jul 15 05:17:14 PM PDT 24
Finished Jul 15 05:18:09 PM PDT 24
Peak memory 249224 kb
Host smart-69fe107e-eac3-4102-b63d-b7b1e8c18935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93264
1459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.932641459
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.720505013
Short name T267
Test name
Test status
Simulation time 198753019814 ps
CPU time 3250.95 seconds
Started Jul 15 05:18:04 PM PDT 24
Finished Jul 15 06:12:16 PM PDT 24
Peak memory 289712 kb
Host smart-e8d8523c-75b5-4597-a975-8312d198523c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720505013 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.720505013
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1498725702
Short name T253
Test name
Test status
Simulation time 10589458959 ps
CPU time 1266.18 seconds
Started Jul 15 05:19:15 PM PDT 24
Finished Jul 15 05:40:22 PM PDT 24
Peak memory 289832 kb
Host smart-cf9a10cd-0902-46f6-a6b1-9f77fa2db3fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498725702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1498725702
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1697352650
Short name T230
Test name
Test status
Simulation time 81241979712 ps
CPU time 2214.18 seconds
Started Jul 15 05:19:41 PM PDT 24
Finished Jul 15 05:56:36 PM PDT 24
Peak memory 298536 kb
Host smart-ac50341c-ca45-41f0-9377-b72e226f6408
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697352650 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1697352650
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3883116523
Short name T108
Test name
Test status
Simulation time 2985788613 ps
CPU time 243.99 seconds
Started Jul 15 07:18:19 PM PDT 24
Finished Jul 15 07:24:03 PM PDT 24
Peak memory 265404 kb
Host smart-a1b6ef76-8590-4108-bdea-45a218a7ecca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3883116523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3883116523
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.599541247
Short name T129
Test name
Test status
Simulation time 3898905304 ps
CPU time 113.61 seconds
Started Jul 15 07:18:31 PM PDT 24
Finished Jul 15 07:21:58 PM PDT 24
Peak memory 265408 kb
Host smart-97a480ec-4cd9-4314-b814-64e876ea4441
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=599541247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.599541247
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3739295975
Short name T151
Test name
Test status
Simulation time 38984933 ps
CPU time 3.17 seconds
Started Jul 15 07:18:23 PM PDT 24
Finished Jul 15 07:20:06 PM PDT 24
Peak memory 237636 kb
Host smart-726e00a5-3110-460c-9966-0b4e7e018ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3739295975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3739295975
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2138967105
Short name T133
Test name
Test status
Simulation time 5183380108 ps
CPU time 632.87 seconds
Started Jul 15 07:18:33 PM PDT 24
Finished Jul 15 07:30:40 PM PDT 24
Peak memory 265368 kb
Host smart-7613140b-2e36-4a38-8d7b-84db6f00922c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138967105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2138967105
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2586095095
Short name T160
Test name
Test status
Simulation time 59881270 ps
CPU time 2.3 seconds
Started Jul 15 07:18:23 PM PDT 24
Finished Jul 15 07:20:05 PM PDT 24
Peak memory 238616 kb
Host smart-d20178b5-6ee2-4c55-9088-bbde878fc537
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2586095095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2586095095
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1532192711
Short name T156
Test name
Test status
Simulation time 4818681171 ps
CPU time 86.76 seconds
Started Jul 15 07:18:48 PM PDT 24
Finished Jul 15 07:21:38 PM PDT 24
Peak memory 237988 kb
Host smart-ded0b573-abaf-4a71-9aef-f395f11a66c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1532192711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1532192711
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.4106549613
Short name T162
Test name
Test status
Simulation time 166491909 ps
CPU time 21.55 seconds
Started Jul 15 07:17:53 PM PDT 24
Finished Jul 15 07:19:58 PM PDT 24
Peak memory 237644 kb
Host smart-ff5d6939-7377-4034-ab66-596a47313840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4106549613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.4106549613
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3337752295
Short name T137
Test name
Test status
Simulation time 9252231926 ps
CPU time 163.65 seconds
Started Jul 15 07:17:54 PM PDT 24
Finished Jul 15 07:22:20 PM PDT 24
Peak memory 265392 kb
Host smart-71cb1cdd-2d69-47c4-a2c0-edfbaded2ffc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3337752295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3337752295
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.114996456
Short name T147
Test name
Test status
Simulation time 146121866 ps
CPU time 4.33 seconds
Started Jul 15 07:18:37 PM PDT 24
Finished Jul 15 07:20:12 PM PDT 24
Peak memory 238544 kb
Host smart-8e2e7afc-70b6-4a3d-96cb-b42e4e4a2b0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=114996456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.114996456
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1106230539
Short name T166
Test name
Test status
Simulation time 61018862 ps
CPU time 2.06 seconds
Started Jul 15 07:18:43 PM PDT 24
Finished Jul 15 07:20:11 PM PDT 24
Peak memory 236556 kb
Host smart-20422ce3-bc51-4fb3-86e7-d8f818b9ab3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1106230539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1106230539
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.812439779
Short name T163
Test name
Test status
Simulation time 1166697169 ps
CPU time 34.55 seconds
Started Jul 15 07:17:47 PM PDT 24
Finished Jul 15 07:20:15 PM PDT 24
Peak memory 240448 kb
Host smart-2505078d-560e-4d10-b97c-10501dfa194b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=812439779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.812439779
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3417912165
Short name T154
Test name
Test status
Simulation time 1052132670 ps
CPU time 67.57 seconds
Started Jul 15 07:18:02 PM PDT 24
Finished Jul 15 07:20:56 PM PDT 24
Peak memory 240492 kb
Host smart-637afbe9-fa54-42e8-a7cb-d90a0aabbf3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3417912165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3417912165
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1708323018
Short name T161
Test name
Test status
Simulation time 51119158 ps
CPU time 3.11 seconds
Started Jul 15 07:17:41 PM PDT 24
Finished Jul 15 07:19:52 PM PDT 24
Peak memory 237820 kb
Host smart-047d8651-1b78-43e4-acc2-e979ff40381b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1708323018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1708323018
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3013648944
Short name T159
Test name
Test status
Simulation time 195376482 ps
CPU time 7.66 seconds
Started Jul 15 07:18:35 PM PDT 24
Finished Jul 15 07:20:14 PM PDT 24
Peak memory 237524 kb
Host smart-f34b495b-e8d6-4d9b-9a61-2798cf3c5757
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3013648944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3013648944
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3362090422
Short name T146
Test name
Test status
Simulation time 113174626 ps
CPU time 2.59 seconds
Started Jul 15 07:18:11 PM PDT 24
Finished Jul 15 07:20:01 PM PDT 24
Peak memory 237540 kb
Host smart-61918900-0242-414f-9d70-5474604b819f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3362090422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3362090422
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1534308803
Short name T153
Test name
Test status
Simulation time 464843143 ps
CPU time 29.38 seconds
Started Jul 15 07:18:20 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 240504 kb
Host smart-aadf8397-5587-40b3-870d-3c0b949da944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1534308803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1534308803
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.159474929
Short name T155
Test name
Test status
Simulation time 4034693965 ps
CPU time 33.51 seconds
Started Jul 15 07:17:58 PM PDT 24
Finished Jul 15 07:20:32 PM PDT 24
Peak memory 240536 kb
Host smart-ac03b548-3689-449c-a918-21266567fd23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=159474929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.159474929
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1896715570
Short name T22
Test name
Test status
Simulation time 48083471107 ps
CPU time 2802.41 seconds
Started Jul 15 05:14:20 PM PDT 24
Finished Jul 15 06:01:03 PM PDT 24
Peak memory 288420 kb
Host smart-3607a1ba-5095-43f9-81ea-39b362d62dd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896715570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1896715570
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1192809156
Short name T19
Test name
Test status
Simulation time 2086252005 ps
CPU time 36.35 seconds
Started Jul 15 05:19:23 PM PDT 24
Finished Jul 15 05:19:59 PM PDT 24
Peak memory 248752 kb
Host smart-ee235af1-daa9-49eb-acc1-aa7cc15970c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11928
09156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1192809156
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1629357577
Short name T810
Test name
Test status
Simulation time 8027134962 ps
CPU time 124.89 seconds
Started Jul 15 07:17:42 PM PDT 24
Finished Jul 15 07:22:08 PM PDT 24
Peak memory 240608 kb
Host smart-e4026637-f813-415f-9ce1-9e93bb78f418
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1629357577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1629357577
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2034441254
Short name T764
Test name
Test status
Simulation time 8982124936 ps
CPU time 471.36 seconds
Started Jul 15 07:17:42 PM PDT 24
Finished Jul 15 07:27:36 PM PDT 24
Peak memory 237624 kb
Host smart-640b10d2-11b1-4e6b-ba3c-498f797bf75a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2034441254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2034441254
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3498093562
Short name T785
Test name
Test status
Simulation time 384962064 ps
CPU time 7.54 seconds
Started Jul 15 07:17:39 PM PDT 24
Finished Jul 15 07:19:56 PM PDT 24
Peak memory 249012 kb
Host smart-a5e13301-321a-4798-b181-9ad4dfc72d11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3498093562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3498093562
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.4192943616
Short name T784
Test name
Test status
Simulation time 942727972 ps
CPU time 8.92 seconds
Started Jul 15 07:17:44 PM PDT 24
Finished Jul 15 07:19:38 PM PDT 24
Peak memory 240564 kb
Host smart-fa048d64-e74f-495f-af1e-eeeda71013ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192943616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.4192943616
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.728595791
Short name T731
Test name
Test status
Simulation time 59102113 ps
CPU time 5.39 seconds
Started Jul 15 07:17:40 PM PDT 24
Finished Jul 15 07:20:04 PM PDT 24
Peak memory 240520 kb
Host smart-f68072be-0adc-4923-87e5-95003519494d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=728595791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.728595791
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3692987348
Short name T805
Test name
Test status
Simulation time 14955463 ps
CPU time 1.25 seconds
Started Jul 15 07:17:48 PM PDT 24
Finished Jul 15 07:19:57 PM PDT 24
Peak memory 236648 kb
Host smart-be14620b-9019-4c17-8727-8b626f95699d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3692987348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3692987348
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.687157004
Short name T755
Test name
Test status
Simulation time 1589581885 ps
CPU time 10.69 seconds
Started Jul 15 07:17:41 PM PDT 24
Finished Jul 15 07:19:59 PM PDT 24
Peak memory 245616 kb
Host smart-5eac56df-c503-44ec-9a43-9ee46c59a085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=687157004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.687157004
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3746867791
Short name T138
Test name
Test status
Simulation time 8646104379 ps
CPU time 148.54 seconds
Started Jul 15 07:17:42 PM PDT 24
Finished Jul 15 07:22:17 PM PDT 24
Peak memory 265432 kb
Host smart-b116515e-817d-4663-9cad-fe3d8c8221aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3746867791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3746867791
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2668597734
Short name T117
Test name
Test status
Simulation time 4440434557 ps
CPU time 613.02 seconds
Started Jul 15 07:17:43 PM PDT 24
Finished Jul 15 07:29:53 PM PDT 24
Peak memory 265412 kb
Host smart-e83771ed-b31e-4dfc-be4e-8e334544090d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668597734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2668597734
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3955070678
Short name T804
Test name
Test status
Simulation time 57376317 ps
CPU time 7.98 seconds
Started Jul 15 07:17:42 PM PDT 24
Finished Jul 15 07:20:11 PM PDT 24
Peak memory 247956 kb
Host smart-01b140dc-2d1b-4c32-8683-edc48b49878e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3955070678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3955070678
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1086881690
Short name T796
Test name
Test status
Simulation time 4033393280 ps
CPU time 262.14 seconds
Started Jul 15 07:17:41 PM PDT 24
Finished Jul 15 07:24:12 PM PDT 24
Peak memory 240660 kb
Host smart-ed197fe6-f7fb-428a-9944-263ccafab8fd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1086881690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1086881690
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1887153305
Short name T182
Test name
Test status
Simulation time 5943199641 ps
CPU time 186.01 seconds
Started Jul 15 07:17:40 PM PDT 24
Finished Jul 15 07:22:54 PM PDT 24
Peak memory 237584 kb
Host smart-5f2a66a5-5920-421b-851c-cc88da6c9ae4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1887153305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1887153305
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2218103235
Short name T725
Test name
Test status
Simulation time 134055388 ps
CPU time 6.2 seconds
Started Jul 15 07:17:39 PM PDT 24
Finished Jul 15 07:19:30 PM PDT 24
Peak memory 248720 kb
Host smart-c77b7850-1e89-43b9-a73c-397ff7a1a574
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2218103235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2218103235
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.117120718
Short name T824
Test name
Test status
Simulation time 77834845 ps
CPU time 6.07 seconds
Started Jul 15 07:17:42 PM PDT 24
Finished Jul 15 07:19:55 PM PDT 24
Peak memory 239896 kb
Host smart-6afee110-fdc0-4037-ac5d-62ed01aea4bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117120718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.117120718
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2248522440
Short name T718
Test name
Test status
Simulation time 132991367 ps
CPU time 5.62 seconds
Started Jul 15 07:17:48 PM PDT 24
Finished Jul 15 07:20:04 PM PDT 24
Peak memory 237560 kb
Host smart-8dd3ab72-179b-4b75-8f9a-5ecf99a49686
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2248522440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2248522440
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1123667547
Short name T809
Test name
Test status
Simulation time 25109504 ps
CPU time 1.52 seconds
Started Jul 15 07:17:41 PM PDT 24
Finished Jul 15 07:20:00 PM PDT 24
Peak memory 236576 kb
Host smart-e0c051ff-6f73-4ca0-9ab1-e2aa5f7f4dc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1123667547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1123667547
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1335235549
Short name T788
Test name
Test status
Simulation time 3485617220 ps
CPU time 32.38 seconds
Started Jul 15 07:17:42 PM PDT 24
Finished Jul 15 07:20:31 PM PDT 24
Peak memory 244860 kb
Host smart-507dab92-ba73-4482-b6cd-17056a71c28d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1335235549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1335235549
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.609983388
Short name T109
Test name
Test status
Simulation time 2735772065 ps
CPU time 109.17 seconds
Started Jul 15 07:17:41 PM PDT 24
Finished Jul 15 07:21:52 PM PDT 24
Peak memory 266440 kb
Host smart-63c559ff-882a-4522-b4e0-611e758350a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=609983388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.609983388
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4024749536
Short name T140
Test name
Test status
Simulation time 24808220290 ps
CPU time 1105.39 seconds
Started Jul 15 07:17:42 PM PDT 24
Finished Jul 15 07:38:10 PM PDT 24
Peak memory 273516 kb
Host smart-0910cfeb-e5d6-43d0-b368-8ef95727a7e8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024749536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4024749536
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1542975839
Short name T710
Test name
Test status
Simulation time 220143241 ps
CPU time 11.24 seconds
Started Jul 15 07:17:42 PM PDT 24
Finished Jul 15 07:20:14 PM PDT 24
Peak memory 248780 kb
Host smart-e12882da-febc-4784-948b-a95f35de2bdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1542975839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1542975839
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.4209110994
Short name T231
Test name
Test status
Simulation time 1127640532 ps
CPU time 34.18 seconds
Started Jul 15 07:17:41 PM PDT 24
Finished Jul 15 07:20:37 PM PDT 24
Peak memory 240540 kb
Host smart-69011fe2-7f46-405b-9903-0f2223a129ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4209110994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.4209110994
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3121812229
Short name T341
Test name
Test status
Simulation time 106868827 ps
CPU time 4.73 seconds
Started Jul 15 07:18:20 PM PDT 24
Finished Jul 15 07:20:04 PM PDT 24
Peak memory 240560 kb
Host smart-3f8902c8-5f59-4a3d-8fbc-d06e81224e2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121812229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3121812229
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.4212356286
Short name T756
Test name
Test status
Simulation time 70070282 ps
CPU time 5.08 seconds
Started Jul 15 07:18:21 PM PDT 24
Finished Jul 15 07:20:09 PM PDT 24
Peak memory 237564 kb
Host smart-2da95f7c-60e8-428c-869f-02b43c827ad3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4212356286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.4212356286
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1161379723
Short name T336
Test name
Test status
Simulation time 26057503 ps
CPU time 1.32 seconds
Started Jul 15 07:18:20 PM PDT 24
Finished Jul 15 07:20:05 PM PDT 24
Peak memory 237552 kb
Host smart-b10a61ce-ecc7-4745-835f-32682f858066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1161379723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1161379723
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4179352092
Short name T726
Test name
Test status
Simulation time 1002239988 ps
CPU time 38.1 seconds
Started Jul 15 07:18:16 PM PDT 24
Finished Jul 15 07:20:41 PM PDT 24
Peak memory 248704 kb
Host smart-f950105b-5922-4e28-b8e5-916f3bfc1a3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4179352092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.4179352092
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.599763685
Short name T720
Test name
Test status
Simulation time 87353214 ps
CPU time 11.13 seconds
Started Jul 15 07:18:21 PM PDT 24
Finished Jul 15 07:20:15 PM PDT 24
Peak memory 248812 kb
Host smart-9da72cfe-5804-4d62-af12-5650c8e81f31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=599763685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.599763685
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3364343619
Short name T787
Test name
Test status
Simulation time 661438393 ps
CPU time 7.79 seconds
Started Jul 15 07:18:21 PM PDT 24
Finished Jul 15 07:20:12 PM PDT 24
Peak memory 239496 kb
Host smart-84be6a7a-8095-49af-a864-c114ae0b70c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364343619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3364343619
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1949748973
Short name T727
Test name
Test status
Simulation time 192784951 ps
CPU time 5.06 seconds
Started Jul 15 07:18:22 PM PDT 24
Finished Jul 15 07:20:11 PM PDT 24
Peak memory 237580 kb
Host smart-ce61ea17-6ec3-4190-b38d-60574a608c90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1949748973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1949748973
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3828633282
Short name T806
Test name
Test status
Simulation time 503463348 ps
CPU time 35.28 seconds
Started Jul 15 07:18:18 PM PDT 24
Finished Jul 15 07:20:34 PM PDT 24
Peak memory 245748 kb
Host smart-174ccaaa-3ef8-4047-af9a-7b826f1e772b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3828633282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3828633282
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1250370619
Short name T128
Test name
Test status
Simulation time 5025155594 ps
CPU time 365.01 seconds
Started Jul 15 07:18:20 PM PDT 24
Finished Jul 15 07:26:04 PM PDT 24
Peak memory 265532 kb
Host smart-b26dee4c-ffcc-4aa7-8f7c-e9e29a563c7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1250370619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1250370619
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4016980401
Short name T126
Test name
Test status
Simulation time 6288911252 ps
CPU time 472.41 seconds
Started Jul 15 07:18:34 PM PDT 24
Finished Jul 15 07:27:58 PM PDT 24
Peak memory 265400 kb
Host smart-4fd76d2c-390f-42ac-a931-c66bb30eb2bf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016980401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.4016980401
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3754054559
Short name T827
Test name
Test status
Simulation time 85340564 ps
CPU time 9.26 seconds
Started Jul 15 07:18:21 PM PDT 24
Finished Jul 15 07:20:13 PM PDT 24
Peak memory 248896 kb
Host smart-4f114bf2-3e69-49fb-976d-ebe6f485d315
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3754054559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3754054559
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.249916140
Short name T744
Test name
Test status
Simulation time 183619067 ps
CPU time 6.75 seconds
Started Jul 15 07:18:20 PM PDT 24
Finished Jul 15 07:20:06 PM PDT 24
Peak memory 241056 kb
Host smart-5db891a5-0857-4136-9428-78240e95c446
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249916140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.249916140
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3115155023
Short name T762
Test name
Test status
Simulation time 346762050 ps
CPU time 7.96 seconds
Started Jul 15 07:18:21 PM PDT 24
Finished Jul 15 07:20:12 PM PDT 24
Peak memory 240444 kb
Host smart-5af109b2-b100-4da3-9cc5-da868c218493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3115155023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3115155023
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2749800355
Short name T791
Test name
Test status
Simulation time 9996376 ps
CPU time 1.31 seconds
Started Jul 15 07:18:19 PM PDT 24
Finished Jul 15 07:20:00 PM PDT 24
Peak memory 237564 kb
Host smart-c1e12177-aef9-47e4-b60c-e80d495cd6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2749800355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2749800355
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.116683600
Short name T760
Test name
Test status
Simulation time 1022152093 ps
CPU time 34 seconds
Started Jul 15 07:18:20 PM PDT 24
Finished Jul 15 07:20:38 PM PDT 24
Peak memory 244808 kb
Host smart-44be3bcb-3a7b-498b-8b5a-a11c518761ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=116683600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.116683600
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3977524950
Short name T115
Test name
Test status
Simulation time 10441867472 ps
CPU time 139.3 seconds
Started Jul 15 07:18:20 PM PDT 24
Finished Jul 15 07:22:18 PM PDT 24
Peak memory 265572 kb
Host smart-ea6ab530-7d16-4d65-b9ab-999cef4647c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3977524950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3977524950
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3673898295
Short name T783
Test name
Test status
Simulation time 132408062 ps
CPU time 8.61 seconds
Started Jul 15 07:18:31 PM PDT 24
Finished Jul 15 07:20:13 PM PDT 24
Peak memory 253064 kb
Host smart-be1829f9-c654-44ce-9d5a-143dbab83dfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3673898295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3673898295
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2434096882
Short name T803
Test name
Test status
Simulation time 145034577 ps
CPU time 6.7 seconds
Started Jul 15 07:18:29 PM PDT 24
Finished Jul 15 07:20:10 PM PDT 24
Peak memory 241132 kb
Host smart-65c642fc-81a7-459f-bef1-2a83f0469eff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434096882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2434096882
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2743131458
Short name T753
Test name
Test status
Simulation time 191889217 ps
CPU time 4.3 seconds
Started Jul 15 07:18:19 PM PDT 24
Finished Jul 15 07:20:03 PM PDT 24
Peak memory 237548 kb
Host smart-f15a4a3a-f4fe-4b47-ab1a-0b5d3f2b1afb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2743131458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2743131458
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1198243144
Short name T739
Test name
Test status
Simulation time 11296981 ps
CPU time 1.56 seconds
Started Jul 15 07:18:25 PM PDT 24
Finished Jul 15 07:20:05 PM PDT 24
Peak memory 237604 kb
Host smart-3e298430-ca91-49b8-b167-3df499a657a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1198243144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1198243144
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3956900930
Short name T745
Test name
Test status
Simulation time 278267742 ps
CPU time 19.81 seconds
Started Jul 15 07:18:23 PM PDT 24
Finished Jul 15 07:20:22 PM PDT 24
Peak memory 248712 kb
Host smart-526e4aee-73cd-4036-bcbe-1c949861f235
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3956900930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3956900930
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3039741323
Short name T144
Test name
Test status
Simulation time 8025198673 ps
CPU time 263.41 seconds
Started Jul 15 07:18:20 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 265356 kb
Host smart-c96e6899-011c-4299-9e60-0973f319732c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3039741323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3039741323
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2023535984
Short name T771
Test name
Test status
Simulation time 703476742 ps
CPU time 20.94 seconds
Started Jul 15 07:18:20 PM PDT 24
Finished Jul 15 07:20:20 PM PDT 24
Peak memory 255368 kb
Host smart-77710035-7539-4eb3-b3cb-fc8b6475bba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2023535984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2023535984
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.512157506
Short name T715
Test name
Test status
Simulation time 298881101 ps
CPU time 7.18 seconds
Started Jul 15 07:18:32 PM PDT 24
Finished Jul 15 07:20:13 PM PDT 24
Peak memory 241228 kb
Host smart-0238dbcc-5aae-4004-a5aa-7b5027be558f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512157506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.512157506
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.526776306
Short name T738
Test name
Test status
Simulation time 118269552 ps
CPU time 4.58 seconds
Started Jul 15 07:18:26 PM PDT 24
Finished Jul 15 07:20:08 PM PDT 24
Peak memory 240528 kb
Host smart-be6f61b6-ed46-4c52-8a13-d64672ce6f50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=526776306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.526776306
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.194501911
Short name T339
Test name
Test status
Simulation time 6704252 ps
CPU time 1.41 seconds
Started Jul 15 07:18:25 PM PDT 24
Finished Jul 15 07:20:05 PM PDT 24
Peak memory 236648 kb
Host smart-2502e8b7-25c3-4551-9331-72f1ca572b5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=194501911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.194501911
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2754221533
Short name T164
Test name
Test status
Simulation time 90073446 ps
CPU time 12.47 seconds
Started Jul 15 07:18:30 PM PDT 24
Finished Jul 15 07:20:16 PM PDT 24
Peak memory 248692 kb
Host smart-43de599f-0267-4b98-8650-fbdb68a2ff69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2754221533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2754221533
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3270286374
Short name T110
Test name
Test status
Simulation time 34758213546 ps
CPU time 1058.34 seconds
Started Jul 15 07:18:25 PM PDT 24
Finished Jul 15 07:37:42 PM PDT 24
Peak memory 265420 kb
Host smart-f1188131-ea78-444a-b293-aad48dcffd30
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270286374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3270286374
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2631862859
Short name T711
Test name
Test status
Simulation time 30381654 ps
CPU time 3 seconds
Started Jul 15 07:18:29 PM PDT 24
Finished Jul 15 07:20:07 PM PDT 24
Peak memory 248864 kb
Host smart-6349bfd6-884b-49d2-afad-877eb6972821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2631862859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2631862859
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2187419275
Short name T768
Test name
Test status
Simulation time 252583474 ps
CPU time 8.21 seconds
Started Jul 15 07:18:38 PM PDT 24
Finished Jul 15 07:20:16 PM PDT 24
Peak memory 254036 kb
Host smart-e854e091-334f-47a0-ba7c-40b3554ae206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187419275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2187419275
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1343192860
Short name T795
Test name
Test status
Simulation time 67210874 ps
CPU time 3.55 seconds
Started Jul 15 07:18:38 PM PDT 24
Finished Jul 15 07:20:11 PM PDT 24
Peak memory 237608 kb
Host smart-4804f179-e762-4e68-99f2-5a4287ef21c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1343192860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1343192860
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.4014809007
Short name T773
Test name
Test status
Simulation time 19116886 ps
CPU time 1.37 seconds
Started Jul 15 07:18:37 PM PDT 24
Finished Jul 15 07:20:09 PM PDT 24
Peak memory 236624 kb
Host smart-b24da0d2-763f-4941-8ec3-c5294ffeedc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4014809007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.4014809007
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2111053788
Short name T736
Test name
Test status
Simulation time 1060821531 ps
CPU time 20.61 seconds
Started Jul 15 07:18:38 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 248836 kb
Host smart-828859ba-848b-49b2-a7c9-8c10e6fa9e77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2111053788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2111053788
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.586072235
Short name T807
Test name
Test status
Simulation time 267173688 ps
CPU time 8 seconds
Started Jul 15 07:18:31 PM PDT 24
Finished Jul 15 07:20:12 PM PDT 24
Peak memory 248436 kb
Host smart-47b04451-9f6c-4258-8a74-c8b1bde0da10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=586072235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.586072235
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2961438855
Short name T786
Test name
Test status
Simulation time 108987721 ps
CPU time 5.24 seconds
Started Jul 15 07:18:44 PM PDT 24
Finished Jul 15 07:20:14 PM PDT 24
Peak memory 248792 kb
Host smart-ea51ccee-ef95-4e5f-84a1-6686b30daf20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961438855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2961438855
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.227676699
Short name T343
Test name
Test status
Simulation time 483865404 ps
CPU time 9.67 seconds
Started Jul 15 07:18:42 PM PDT 24
Finished Jul 15 07:20:19 PM PDT 24
Peak memory 237520 kb
Host smart-77b5c0b2-47a5-4ecd-8f8d-4c10a050180c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=227676699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.227676699
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4087627599
Short name T802
Test name
Test status
Simulation time 14040423 ps
CPU time 1.28 seconds
Started Jul 15 07:18:41 PM PDT 24
Finished Jul 15 07:20:10 PM PDT 24
Peak memory 237592 kb
Host smart-61e7a627-dcb3-41c2-a23c-f78beee934c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4087627599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.4087627599
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.749500139
Short name T165
Test name
Test status
Simulation time 3861864901 ps
CPU time 40.95 seconds
Started Jul 15 07:18:48 PM PDT 24
Finished Jul 15 07:20:53 PM PDT 24
Peak memory 244840 kb
Host smart-f7380a58-3ef2-4371-b2ce-3cef82ff1fff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=749500139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.749500139
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1572499177
Short name T130
Test name
Test status
Simulation time 1102248215 ps
CPU time 102.3 seconds
Started Jul 15 07:18:35 PM PDT 24
Finished Jul 15 07:21:49 PM PDT 24
Peak memory 265416 kb
Host smart-a7c9e5b2-b237-4588-a64b-a726c164e781
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1572499177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1572499177
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2715433208
Short name T132
Test name
Test status
Simulation time 10017709698 ps
CPU time 339.83 seconds
Started Jul 15 07:18:36 PM PDT 24
Finished Jul 15 07:25:46 PM PDT 24
Peak memory 269668 kb
Host smart-ce20623c-b2db-48f2-9216-eb2662bfcb4c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715433208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2715433208
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2342526128
Short name T225
Test name
Test status
Simulation time 182882377 ps
CPU time 13.19 seconds
Started Jul 15 07:18:37 PM PDT 24
Finished Jul 15 07:20:21 PM PDT 24
Peak memory 248736 kb
Host smart-8dedbb43-5e30-4333-9ed0-29b63c332847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2342526128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2342526128
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2568571597
Short name T157
Test name
Test status
Simulation time 180046818 ps
CPU time 3.22 seconds
Started Jul 15 07:18:36 PM PDT 24
Finished Jul 15 07:20:10 PM PDT 24
Peak memory 238616 kb
Host smart-692ac602-74c6-4c0f-912f-a5132c92342d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2568571597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2568571597
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2737953682
Short name T190
Test name
Test status
Simulation time 321132113 ps
CPU time 8.01 seconds
Started Jul 15 07:18:46 PM PDT 24
Finished Jul 15 07:20:17 PM PDT 24
Peak memory 256792 kb
Host smart-aa63f38e-1d9f-4bed-8c34-db2d42a23fcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737953682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2737953682
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.884754487
Short name T782
Test name
Test status
Simulation time 36725842 ps
CPU time 3.38 seconds
Started Jul 15 07:18:43 PM PDT 24
Finished Jul 15 07:20:12 PM PDT 24
Peak memory 237688 kb
Host smart-c6a3a7e0-49e3-4e5c-8c73-bcf7be66c096
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=884754487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.884754487
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1538802056
Short name T829
Test name
Test status
Simulation time 10731789 ps
CPU time 1.47 seconds
Started Jul 15 07:18:43 PM PDT 24
Finished Jul 15 07:20:10 PM PDT 24
Peak memory 236660 kb
Host smart-726ab0b2-d0b8-4ae7-a2e0-8c8a55871673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1538802056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1538802056
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1120502243
Short name T746
Test name
Test status
Simulation time 331482422 ps
CPU time 18.73 seconds
Started Jul 15 07:18:46 PM PDT 24
Finished Jul 15 07:20:28 PM PDT 24
Peak memory 244836 kb
Host smart-793840d2-d3af-4364-b5b2-152cc406ebba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1120502243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1120502243
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2406217653
Short name T713
Test name
Test status
Simulation time 406681991 ps
CPU time 5.14 seconds
Started Jul 15 07:18:47 PM PDT 24
Finished Jul 15 07:20:14 PM PDT 24
Peak memory 248800 kb
Host smart-2a9c1fbd-7c8e-42f1-b58b-36a9f12360a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2406217653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2406217653
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3814968821
Short name T152
Test name
Test status
Simulation time 205981854 ps
CPU time 3.47 seconds
Started Jul 15 07:18:41 PM PDT 24
Finished Jul 15 07:20:12 PM PDT 24
Peak memory 237560 kb
Host smart-21312685-6b92-4fec-bc06-2bf06e525111
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3814968821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3814968821
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.472709437
Short name T719
Test name
Test status
Simulation time 81065979 ps
CPU time 7.46 seconds
Started Jul 15 07:18:48 PM PDT 24
Finished Jul 15 07:20:19 PM PDT 24
Peak memory 241056 kb
Host smart-69d9236f-d553-41ac-afd2-2e99ca0ccce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472709437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.472709437
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1223763214
Short name T342
Test name
Test status
Simulation time 246585298 ps
CPU time 9.08 seconds
Started Jul 15 07:18:47 PM PDT 24
Finished Jul 15 07:20:18 PM PDT 24
Peak memory 237596 kb
Host smart-76d17e60-fc7d-44b8-b125-fa784ec80d12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1223763214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1223763214
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.554081075
Short name T778
Test name
Test status
Simulation time 8152398 ps
CPU time 1.43 seconds
Started Jul 15 07:18:40 PM PDT 24
Finished Jul 15 07:20:08 PM PDT 24
Peak memory 237576 kb
Host smart-f3c0d3b2-5768-4aca-a7b4-20afb0480772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=554081075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.554081075
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3527315305
Short name T828
Test name
Test status
Simulation time 386602898 ps
CPU time 11.57 seconds
Started Jul 15 07:18:46 PM PDT 24
Finished Jul 15 07:20:21 PM PDT 24
Peak memory 248676 kb
Host smart-af684343-7a63-4e94-a5c9-35450a201f3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3527315305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3527315305
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1509119338
Short name T790
Test name
Test status
Simulation time 942987060 ps
CPU time 93.58 seconds
Started Jul 15 07:18:44 PM PDT 24
Finished Jul 15 07:21:43 PM PDT 24
Peak memory 257128 kb
Host smart-693ea1f8-f1ce-4142-9ef8-a77759835a6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1509119338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1509119338
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.377637074
Short name T830
Test name
Test status
Simulation time 30634701226 ps
CPU time 308.01 seconds
Started Jul 15 07:18:47 PM PDT 24
Finished Jul 15 07:25:17 PM PDT 24
Peak memory 265404 kb
Host smart-84ff1740-1e8e-4cfd-af96-9392f8a2c26e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377637074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.377637074
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3292107737
Short name T769
Test name
Test status
Simulation time 93824361 ps
CPU time 6.89 seconds
Started Jul 15 07:18:40 PM PDT 24
Finished Jul 15 07:20:15 PM PDT 24
Peak memory 247544 kb
Host smart-0467b380-3ea0-43dc-9c8a-40d5eefb692d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3292107737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3292107737
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3857770371
Short name T721
Test name
Test status
Simulation time 257704234 ps
CPU time 5.75 seconds
Started Jul 15 07:18:48 PM PDT 24
Finished Jul 15 07:20:17 PM PDT 24
Peak memory 256892 kb
Host smart-d957f17d-19a2-43ec-a2bc-bc849497e183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857770371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3857770371
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2306638005
Short name T801
Test name
Test status
Simulation time 98430399 ps
CPU time 8.38 seconds
Started Jul 15 07:18:48 PM PDT 24
Finished Jul 15 07:20:18 PM PDT 24
Peak memory 237572 kb
Host smart-bcc97ae8-1bf0-4376-b5a8-5fc6d35aed25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2306638005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2306638005
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3707729954
Short name T717
Test name
Test status
Simulation time 8764026 ps
CPU time 1.49 seconds
Started Jul 15 07:18:48 PM PDT 24
Finished Jul 15 07:20:13 PM PDT 24
Peak memory 237604 kb
Host smart-a4cca2df-77b3-4d86-ab65-552905e9a385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3707729954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3707729954
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4179006533
Short name T186
Test name
Test status
Simulation time 2587411078 ps
CPU time 37.15 seconds
Started Jul 15 07:18:48 PM PDT 24
Finished Jul 15 07:20:47 PM PDT 24
Peak memory 248772 kb
Host smart-6a5308f9-b7ca-4ab3-a0da-4dd4ae33c9a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4179006533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.4179006533
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1541929619
Short name T136
Test name
Test status
Simulation time 16804593832 ps
CPU time 313.77 seconds
Started Jul 15 07:18:44 PM PDT 24
Finished Jul 15 07:25:23 PM PDT 24
Peak memory 265440 kb
Host smart-2a50ea4a-3869-4027-9e34-2485b3c43933
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1541929619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1541929619
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.766903550
Short name T141
Test name
Test status
Simulation time 19278490052 ps
CPU time 1223.74 seconds
Started Jul 15 07:18:49 PM PDT 24
Finished Jul 15 07:40:39 PM PDT 24
Peak memory 273508 kb
Host smart-8dc9b82f-09c8-43ab-a648-eb10d3b35830
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766903550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.766903550
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.423940067
Short name T757
Test name
Test status
Simulation time 81810910 ps
CPU time 6.25 seconds
Started Jul 15 07:18:47 PM PDT 24
Finished Jul 15 07:20:15 PM PDT 24
Peak memory 248728 kb
Host smart-0880f340-49cc-4f7f-a154-5aa85bedcfec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=423940067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.423940067
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4054272902
Short name T724
Test name
Test status
Simulation time 2443048048 ps
CPU time 141.98 seconds
Started Jul 15 07:17:54 PM PDT 24
Finished Jul 15 07:21:58 PM PDT 24
Peak memory 237588 kb
Host smart-c54d613b-5a04-459d-bbf2-d44282442b3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4054272902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4054272902
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1006418787
Short name T728
Test name
Test status
Simulation time 3405835659 ps
CPU time 83.24 seconds
Started Jul 15 07:17:51 PM PDT 24
Finished Jul 15 07:21:22 PM PDT 24
Peak memory 236676 kb
Host smart-915026c7-7865-45c9-8df7-8d5a10bf981a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1006418787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1006418787
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3419531646
Short name T148
Test name
Test status
Simulation time 951835399 ps
CPU time 4.92 seconds
Started Jul 15 07:17:53 PM PDT 24
Finished Jul 15 07:19:41 PM PDT 24
Peak memory 248720 kb
Host smart-92fcba5a-d1dd-43c4-a4c8-7091c02a4afb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3419531646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3419531646
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3925771987
Short name T821
Test name
Test status
Simulation time 81538640 ps
CPU time 4.83 seconds
Started Jul 15 07:17:46 PM PDT 24
Finished Jul 15 07:19:34 PM PDT 24
Peak memory 240324 kb
Host smart-ace5c251-cac8-4d42-b1e4-dc69b4c625bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925771987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3925771987
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1917185461
Short name T774
Test name
Test status
Simulation time 130083064 ps
CPU time 5.09 seconds
Started Jul 15 07:17:58 PM PDT 24
Finished Jul 15 07:19:55 PM PDT 24
Peak memory 237460 kb
Host smart-bd314aa1-c71e-4eb6-9e38-d3de4a6a6f69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1917185461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1917185461
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4007559427
Short name T337
Test name
Test status
Simulation time 23882391 ps
CPU time 1.52 seconds
Started Jul 15 07:17:58 PM PDT 24
Finished Jul 15 07:20:00 PM PDT 24
Peak memory 236596 kb
Host smart-e90f5843-3f83-48c1-ae9f-3b94429e63dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4007559427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4007559427
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.535285925
Short name T733
Test name
Test status
Simulation time 318065061 ps
CPU time 21.89 seconds
Started Jul 15 07:17:58 PM PDT 24
Finished Jul 15 07:20:21 PM PDT 24
Peak memory 244776 kb
Host smart-2e97adc8-90a8-4a94-bcb6-b4e1c5bc1538
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=535285925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.535285925
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2573685557
Short name T142
Test name
Test status
Simulation time 30135035919 ps
CPU time 1059.79 seconds
Started Jul 15 07:17:47 PM PDT 24
Finished Jul 15 07:37:29 PM PDT 24
Peak memory 265392 kb
Host smart-c6849052-543b-4275-9391-29e0c1c87edc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573685557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2573685557
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4122199921
Short name T224
Test name
Test status
Simulation time 144522631 ps
CPU time 9.44 seconds
Started Jul 15 07:17:45 PM PDT 24
Finished Jul 15 07:19:39 PM PDT 24
Peak memory 256000 kb
Host smart-56d00093-6b6f-4465-b6b1-78691e1901db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4122199921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.4122199921
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1699019588
Short name T789
Test name
Test status
Simulation time 14673314 ps
CPU time 1.35 seconds
Started Jul 15 07:18:48 PM PDT 24
Finished Jul 15 07:20:11 PM PDT 24
Peak memory 236604 kb
Host smart-bb7806f3-9183-43c9-b3ed-e4917279d5ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1699019588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1699019588
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1073760684
Short name T775
Test name
Test status
Simulation time 7434022 ps
CPU time 1.42 seconds
Started Jul 15 07:18:48 PM PDT 24
Finished Jul 15 07:20:13 PM PDT 24
Peak memory 235600 kb
Host smart-203edfb9-f590-41d5-a028-f79a49a2e055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1073760684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1073760684
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.381265283
Short name T761
Test name
Test status
Simulation time 9712503 ps
CPU time 1.33 seconds
Started Jul 15 07:18:50 PM PDT 24
Finished Jul 15 07:20:13 PM PDT 24
Peak memory 235644 kb
Host smart-4bbb2e1d-3ba2-4e49-8c5e-177a5829c288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=381265283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.381265283
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2458873130
Short name T734
Test name
Test status
Simulation time 7105961 ps
CPU time 1.38 seconds
Started Jul 15 07:18:47 PM PDT 24
Finished Jul 15 07:20:10 PM PDT 24
Peak memory 237556 kb
Host smart-bce76d0d-3c41-4a4b-83f4-8e70d07be8d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2458873130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2458873130
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1331536707
Short name T799
Test name
Test status
Simulation time 13244680 ps
CPU time 1.42 seconds
Started Jul 15 07:18:49 PM PDT 24
Finished Jul 15 07:20:14 PM PDT 24
Peak memory 236664 kb
Host smart-20374c9b-2e37-4a69-a9cf-94e2cc89e42a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1331536707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1331536707
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3122156265
Short name T743
Test name
Test status
Simulation time 12399604 ps
CPU time 1.44 seconds
Started Jul 15 07:18:47 PM PDT 24
Finished Jul 15 07:20:11 PM PDT 24
Peak memory 237576 kb
Host smart-4d58ea1d-dd98-4594-ad7d-b82047797b33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3122156265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3122156265
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1620721998
Short name T716
Test name
Test status
Simulation time 10826966 ps
CPU time 1.28 seconds
Started Jul 15 07:18:50 PM PDT 24
Finished Jul 15 07:20:13 PM PDT 24
Peak memory 237528 kb
Host smart-11c3c0f9-5932-4f7d-82fc-5c049c04ecd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1620721998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1620721998
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1979103602
Short name T714
Test name
Test status
Simulation time 14877843 ps
CPU time 1.46 seconds
Started Jul 15 07:18:50 PM PDT 24
Finished Jul 15 07:20:14 PM PDT 24
Peak memory 236596 kb
Host smart-89832024-cd96-4310-8026-d57dbf3b1ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1979103602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1979103602
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2743928452
Short name T772
Test name
Test status
Simulation time 8578330 ps
CPU time 1.53 seconds
Started Jul 15 07:18:49 PM PDT 24
Finished Jul 15 07:20:13 PM PDT 24
Peak memory 236620 kb
Host smart-4656232d-8695-4106-a761-9c7aeabb9054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2743928452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2743928452
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3324791315
Short name T814
Test name
Test status
Simulation time 10784703 ps
CPU time 1.28 seconds
Started Jul 15 07:18:49 PM PDT 24
Finished Jul 15 07:20:14 PM PDT 24
Peak memory 236628 kb
Host smart-0b41d39d-414c-4d80-9646-df85f246057e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3324791315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3324791315
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.474333146
Short name T183
Test name
Test status
Simulation time 2244619754 ps
CPU time 143.43 seconds
Started Jul 15 07:17:58 PM PDT 24
Finished Jul 15 07:22:13 PM PDT 24
Peak memory 239220 kb
Host smart-7cc9d572-fa46-452c-b148-f3f29efad157
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=474333146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.474333146
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2372762772
Short name T780
Test name
Test status
Simulation time 17793422677 ps
CPU time 445.95 seconds
Started Jul 15 07:17:45 PM PDT 24
Finished Jul 15 07:26:55 PM PDT 24
Peak memory 237628 kb
Host smart-a65e6e19-5043-4889-a78d-c3c2ffa0c6de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2372762772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2372762772
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3018685922
Short name T709
Test name
Test status
Simulation time 57400137 ps
CPU time 5.16 seconds
Started Jul 15 07:17:53 PM PDT 24
Finished Jul 15 07:19:41 PM PDT 24
Peak memory 248676 kb
Host smart-ae8f0888-0bcb-4596-8ec4-90a86d2c5bcb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3018685922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3018685922
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3579481957
Short name T344
Test name
Test status
Simulation time 117127864 ps
CPU time 9.36 seconds
Started Jul 15 07:17:48 PM PDT 24
Finished Jul 15 07:19:39 PM PDT 24
Peak memory 256864 kb
Host smart-6f75328f-7553-4845-b7d0-30d7f7d3acb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579481957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3579481957
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.461951637
Short name T730
Test name
Test status
Simulation time 51502523 ps
CPU time 4.49 seconds
Started Jul 15 07:17:47 PM PDT 24
Finished Jul 15 07:19:53 PM PDT 24
Peak memory 237688 kb
Host smart-ec1c6915-8a93-43c1-836e-bd86f1d88d8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=461951637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.461951637
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.492744993
Short name T723
Test name
Test status
Simulation time 21602415 ps
CPU time 1.34 seconds
Started Jul 15 07:17:58 PM PDT 24
Finished Jul 15 07:19:38 PM PDT 24
Peak memory 236596 kb
Host smart-9158893c-ac18-4123-b3f5-3b1655d9ed8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=492744993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.492744993
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2044883464
Short name T766
Test name
Test status
Simulation time 240677083 ps
CPU time 17.3 seconds
Started Jul 15 07:17:47 PM PDT 24
Finished Jul 15 07:19:59 PM PDT 24
Peak memory 245732 kb
Host smart-3ea53b1c-9d6d-4eab-868c-e01105a02ccd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2044883464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2044883464
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1106997001
Short name T111
Test name
Test status
Simulation time 8588968968 ps
CPU time 155.74 seconds
Started Jul 15 07:17:46 PM PDT 24
Finished Jul 15 07:22:05 PM PDT 24
Peak memory 265460 kb
Host smart-3b0cff08-4517-4b9f-a11e-6d2f7669e7ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1106997001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1106997001
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.158280932
Short name T813
Test name
Test status
Simulation time 242301347 ps
CPU time 15.39 seconds
Started Jul 15 07:17:53 PM PDT 24
Finished Jul 15 07:19:52 PM PDT 24
Peak memory 255480 kb
Host smart-80f140c8-7ea4-4f12-8687-0f26a87e9b5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=158280932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.158280932
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2674629459
Short name T759
Test name
Test status
Simulation time 10808289 ps
CPU time 1.26 seconds
Started Jul 15 07:18:49 PM PDT 24
Finished Jul 15 07:20:16 PM PDT 24
Peak memory 237600 kb
Host smart-3e8d0d68-f64d-4607-a66c-311d68905c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2674629459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2674629459
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3010469206
Short name T732
Test name
Test status
Simulation time 6716870 ps
CPU time 1.41 seconds
Started Jul 15 07:18:52 PM PDT 24
Finished Jul 15 07:20:14 PM PDT 24
Peak memory 237540 kb
Host smart-9555240c-a06c-4e30-ad98-442e675cd835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3010469206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3010469206
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3384651934
Short name T338
Test name
Test status
Simulation time 11236917 ps
CPU time 1.54 seconds
Started Jul 15 07:18:52 PM PDT 24
Finished Jul 15 07:20:13 PM PDT 24
Peak memory 237572 kb
Host smart-847f927c-da93-4b8f-bb08-e39d05269600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3384651934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3384651934
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1537094907
Short name T817
Test name
Test status
Simulation time 14882201 ps
CPU time 1.62 seconds
Started Jul 15 07:18:54 PM PDT 24
Finished Jul 15 07:20:14 PM PDT 24
Peak memory 236596 kb
Host smart-a9a23343-a0f8-4b7b-b68f-d45dc13aadd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1537094907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1537094907
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1218929571
Short name T742
Test name
Test status
Simulation time 12922874 ps
CPU time 1.36 seconds
Started Jul 15 07:18:55 PM PDT 24
Finished Jul 15 07:20:22 PM PDT 24
Peak memory 235684 kb
Host smart-0feaa161-9d18-4694-b239-3bb879d55ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1218929571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1218929571
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.475598085
Short name T729
Test name
Test status
Simulation time 11654124 ps
CPU time 1.4 seconds
Started Jul 15 07:18:54 PM PDT 24
Finished Jul 15 07:20:14 PM PDT 24
Peak memory 236648 kb
Host smart-880be90e-7f73-40ec-b7a1-6fcdfe922b0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=475598085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.475598085
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2473232938
Short name T815
Test name
Test status
Simulation time 9897051 ps
CPU time 1.25 seconds
Started Jul 15 07:18:54 PM PDT 24
Finished Jul 15 07:20:21 PM PDT 24
Peak memory 235572 kb
Host smart-c5471151-4996-4de8-b236-66a176a376f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2473232938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2473232938
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1949902922
Short name T825
Test name
Test status
Simulation time 12272356 ps
CPU time 1.75 seconds
Started Jul 15 07:18:53 PM PDT 24
Finished Jul 15 07:20:14 PM PDT 24
Peak memory 236636 kb
Host smart-dd407d7a-ec6f-4db8-914b-bce1ae657970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1949902922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1949902922
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.698177078
Short name T792
Test name
Test status
Simulation time 15532197 ps
CPU time 1.54 seconds
Started Jul 15 07:18:55 PM PDT 24
Finished Jul 15 07:20:22 PM PDT 24
Peak memory 236632 kb
Host smart-1c1b5240-35ab-4af8-b95a-ab1e0effba0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=698177078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.698177078
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2956348404
Short name T740
Test name
Test status
Simulation time 14191787 ps
CPU time 1.29 seconds
Started Jul 15 07:18:53 PM PDT 24
Finished Jul 15 07:20:12 PM PDT 24
Peak memory 236632 kb
Host smart-33e5eeb1-bb27-4b8e-b919-187f6a3dbddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2956348404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2956348404
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3685638927
Short name T187
Test name
Test status
Simulation time 1142710321 ps
CPU time 164.37 seconds
Started Jul 15 07:18:02 PM PDT 24
Finished Jul 15 07:22:29 PM PDT 24
Peak memory 238780 kb
Host smart-61b3fafb-e76e-4824-9656-23035f1aca61
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3685638927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3685638927
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3125284790
Short name T763
Test name
Test status
Simulation time 5829932492 ps
CPU time 193.49 seconds
Started Jul 15 07:17:49 PM PDT 24
Finished Jul 15 07:22:43 PM PDT 24
Peak memory 240544 kb
Host smart-6abc1d28-68ad-459f-a753-3cef1394eb7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3125284790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3125284790
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.61806139
Short name T749
Test name
Test status
Simulation time 1883349027 ps
CPU time 9.46 seconds
Started Jul 15 07:17:54 PM PDT 24
Finished Jul 15 07:20:08 PM PDT 24
Peak memory 249048 kb
Host smart-6392f923-06f0-41ea-9985-5473e3a18b8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=61806139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.61806139
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.574319315
Short name T793
Test name
Test status
Simulation time 200004173 ps
CPU time 8.51 seconds
Started Jul 15 07:17:55 PM PDT 24
Finished Jul 15 07:20:12 PM PDT 24
Peak memory 256320 kb
Host smart-2e3d00ba-73db-4d3f-b293-e5c32ce6e54b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574319315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.574319315
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3984723090
Short name T812
Test name
Test status
Simulation time 136457018 ps
CPU time 9.62 seconds
Started Jul 15 07:17:53 PM PDT 24
Finished Jul 15 07:19:46 PM PDT 24
Peak memory 237564 kb
Host smart-acd339a2-1503-4560-97c7-7c4fe2c67f60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3984723090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3984723090
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1318117796
Short name T737
Test name
Test status
Simulation time 10357284 ps
CPU time 1.32 seconds
Started Jul 15 07:17:53 PM PDT 24
Finished Jul 15 07:19:43 PM PDT 24
Peak memory 236600 kb
Host smart-3fb77dc0-053c-41c8-8ba4-0aea37080ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1318117796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1318117796
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.750696470
Short name T185
Test name
Test status
Simulation time 748804309 ps
CPU time 23.67 seconds
Started Jul 15 07:17:52 PM PDT 24
Finished Jul 15 07:20:08 PM PDT 24
Peak memory 248736 kb
Host smart-c03d1fc5-7bb4-4e9c-b339-77d1f15b1ff0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=750696470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.750696470
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3760536387
Short name T135
Test name
Test status
Simulation time 48508846122 ps
CPU time 909.69 seconds
Started Jul 15 07:17:53 PM PDT 24
Finished Jul 15 07:34:54 PM PDT 24
Peak memory 265372 kb
Host smart-9faf97c5-e41a-4812-9533-696f7029d5ba
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760536387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3760536387
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.787060085
Short name T223
Test name
Test status
Simulation time 322394805 ps
CPU time 11.05 seconds
Started Jul 15 07:17:55 PM PDT 24
Finished Jul 15 07:19:56 PM PDT 24
Peak memory 248532 kb
Host smart-b8f0604a-1959-4810-b275-e13fe5c30e47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=787060085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.787060085
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1057184718
Short name T794
Test name
Test status
Simulation time 211726439 ps
CPU time 4.03 seconds
Started Jul 15 07:17:52 PM PDT 24
Finished Jul 15 07:19:48 PM PDT 24
Peak memory 236604 kb
Host smart-f3878afa-7a0e-4f0e-b8cc-2cd550f46df7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1057184718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1057184718
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3617029149
Short name T748
Test name
Test status
Simulation time 18228203 ps
CPU time 1.38 seconds
Started Jul 15 07:18:54 PM PDT 24
Finished Jul 15 07:20:22 PM PDT 24
Peak memory 237360 kb
Host smart-d6e616ae-31a9-4871-8b44-8fc8865b5c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3617029149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3617029149
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.869738292
Short name T831
Test name
Test status
Simulation time 10426520 ps
CPU time 1.36 seconds
Started Jul 15 07:18:54 PM PDT 24
Finished Jul 15 07:20:22 PM PDT 24
Peak memory 236648 kb
Host smart-be586929-a84a-489c-accd-a93ae71cd75a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=869738292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.869738292
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3219511624
Short name T335
Test name
Test status
Simulation time 12444434 ps
CPU time 1.66 seconds
Started Jul 15 07:18:54 PM PDT 24
Finished Jul 15 07:20:15 PM PDT 24
Peak memory 236684 kb
Host smart-1e8cdfc1-e1c2-4b64-849a-1ff7c660287a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3219511624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3219511624
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3036198507
Short name T811
Test name
Test status
Simulation time 19927782 ps
CPU time 1.39 seconds
Started Jul 15 07:19:01 PM PDT 24
Finished Jul 15 07:20:16 PM PDT 24
Peak memory 236984 kb
Host smart-1de621ad-b521-4247-bd7d-5055ab3c9989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3036198507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3036198507
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4039149438
Short name T754
Test name
Test status
Simulation time 10304434 ps
CPU time 1.34 seconds
Started Jul 15 07:19:02 PM PDT 24
Finished Jul 15 07:20:22 PM PDT 24
Peak memory 236608 kb
Host smart-1cc0358d-0189-480e-b95e-33c63c947cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4039149438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4039149438
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3324666038
Short name T770
Test name
Test status
Simulation time 10536443 ps
CPU time 1.44 seconds
Started Jul 15 07:19:00 PM PDT 24
Finished Jul 15 07:20:16 PM PDT 24
Peak memory 235588 kb
Host smart-23e25967-61a0-4c57-b1c8-2633b3020edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3324666038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3324666038
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2484404482
Short name T752
Test name
Test status
Simulation time 8300626 ps
CPU time 1.49 seconds
Started Jul 15 07:19:04 PM PDT 24
Finished Jul 15 07:20:22 PM PDT 24
Peak memory 237496 kb
Host smart-db62d710-b36c-42f9-9839-4a1d87d0a43e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2484404482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2484404482
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2171231772
Short name T722
Test name
Test status
Simulation time 8352707 ps
CPU time 1.35 seconds
Started Jul 15 07:19:01 PM PDT 24
Finished Jul 15 07:20:16 PM PDT 24
Peak memory 237036 kb
Host smart-dbb11433-1da1-416e-bf6a-56d57944851c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2171231772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2171231772
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2242493814
Short name T818
Test name
Test status
Simulation time 10258999 ps
CPU time 1.61 seconds
Started Jul 15 07:19:02 PM PDT 24
Finished Jul 15 07:20:17 PM PDT 24
Peak memory 236628 kb
Host smart-18b065b4-c16c-4b3d-96e2-941a345d7d63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2242493814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2242493814
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3864130503
Short name T820
Test name
Test status
Simulation time 1542341909 ps
CPU time 10.71 seconds
Started Jul 15 07:17:54 PM PDT 24
Finished Jul 15 07:20:09 PM PDT 24
Peak memory 251068 kb
Host smart-3454bf04-3a73-4381-9a58-a09f603b1e7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864130503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3864130503
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3543973388
Short name T826
Test name
Test status
Simulation time 98130128 ps
CPU time 4.76 seconds
Started Jul 15 07:18:03 PM PDT 24
Finished Jul 15 07:19:54 PM PDT 24
Peak memory 237560 kb
Host smart-e73cb25a-7f8a-4726-8aa3-1131ccde692d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3543973388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3543973388
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4139369416
Short name T750
Test name
Test status
Simulation time 8630103 ps
CPU time 1.37 seconds
Started Jul 15 07:17:54 PM PDT 24
Finished Jul 15 07:19:51 PM PDT 24
Peak memory 237540 kb
Host smart-c6161869-cbe9-4587-9dff-2cb0c777b1ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4139369416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4139369416
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.109361663
Short name T751
Test name
Test status
Simulation time 686769309 ps
CPU time 18.65 seconds
Started Jul 15 07:17:54 PM PDT 24
Finished Jul 15 07:20:03 PM PDT 24
Peak memory 244792 kb
Host smart-90bd2248-98b7-4d02-8129-0a663f5e480a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=109361663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.109361663
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1331122512
Short name T123
Test name
Test status
Simulation time 13593133236 ps
CPU time 80.02 seconds
Started Jul 15 07:17:53 PM PDT 24
Finished Jul 15 07:21:00 PM PDT 24
Peak memory 257192 kb
Host smart-78b9d875-0631-438f-b48e-22929f9bea22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1331122512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1331122512
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1541169577
Short name T816
Test name
Test status
Simulation time 10235442854 ps
CPU time 467 seconds
Started Jul 15 07:17:57 PM PDT 24
Finished Jul 15 07:27:23 PM PDT 24
Peak memory 265348 kb
Host smart-51b9068a-a57a-45dc-b189-feab0e0aec5a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541169577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1541169577
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3860898065
Short name T777
Test name
Test status
Simulation time 250671662 ps
CPU time 8.76 seconds
Started Jul 15 07:17:55 PM PDT 24
Finished Jul 15 07:20:05 PM PDT 24
Peak memory 253444 kb
Host smart-39ab5bd9-9673-4f19-bf9d-c3e252e2fc28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3860898065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3860898065
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1035810555
Short name T767
Test name
Test status
Simulation time 495650724 ps
CPU time 9.87 seconds
Started Jul 15 07:18:04 PM PDT 24
Finished Jul 15 07:20:00 PM PDT 24
Peak memory 243564 kb
Host smart-4f425652-48cd-43e8-8c9b-2d1bb341c399
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035810555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1035810555
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.4083327460
Short name T758
Test name
Test status
Simulation time 117611201 ps
CPU time 4.52 seconds
Started Jul 15 07:17:55 PM PDT 24
Finished Jul 15 07:20:01 PM PDT 24
Peak memory 236592 kb
Host smart-6326cfed-6b1e-4811-a6a5-f1efbe80f5ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4083327460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.4083327460
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1378253119
Short name T340
Test name
Test status
Simulation time 9784603 ps
CPU time 1.36 seconds
Started Jul 15 07:17:52 PM PDT 24
Finished Jul 15 07:19:46 PM PDT 24
Peak memory 236652 kb
Host smart-ad211391-5856-4f36-84ee-d20ecbf4b86d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1378253119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1378253119
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.590118064
Short name T184
Test name
Test status
Simulation time 535384376 ps
CPU time 36.67 seconds
Started Jul 15 07:18:02 PM PDT 24
Finished Jul 15 07:20:40 PM PDT 24
Peak memory 248696 kb
Host smart-39b569a4-b78b-4a85-93d8-b3329d891fe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=590118064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.590118064
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1248197296
Short name T712
Test name
Test status
Simulation time 310993773 ps
CPU time 10.25 seconds
Started Jul 15 07:17:54 PM PDT 24
Finished Jul 15 07:20:00 PM PDT 24
Peak memory 254392 kb
Host smart-62110ea9-48d0-4903-afea-609497f7bb17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1248197296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1248197296
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3605925566
Short name T781
Test name
Test status
Simulation time 103969342 ps
CPU time 2.53 seconds
Started Jul 15 07:18:03 PM PDT 24
Finished Jul 15 07:19:52 PM PDT 24
Peak memory 236616 kb
Host smart-2c277eb9-97e9-4aae-a759-57a13d0bf77b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3605925566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3605925566
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2773745529
Short name T776
Test name
Test status
Simulation time 64550932 ps
CPU time 8.25 seconds
Started Jul 15 07:17:58 PM PDT 24
Finished Jul 15 07:19:45 PM PDT 24
Peak memory 256940 kb
Host smart-52aa4017-44dc-42ae-831e-15a7336b4a37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773745529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2773745529
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2356932025
Short name T222
Test name
Test status
Simulation time 64892033 ps
CPU time 4.92 seconds
Started Jul 15 07:19:11 PM PDT 24
Finished Jul 15 07:20:25 PM PDT 24
Peak memory 240492 kb
Host smart-4cbe70b2-b23d-407c-b0a3-94c9c6eb1502
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2356932025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2356932025
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3503664686
Short name T765
Test name
Test status
Simulation time 11285747 ps
CPU time 1.57 seconds
Started Jul 15 07:18:02 PM PDT 24
Finished Jul 15 07:19:46 PM PDT 24
Peak memory 236696 kb
Host smart-b5e5b49c-8cce-4046-a4a3-561096cbcd3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3503664686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3503664686
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.261096429
Short name T800
Test name
Test status
Simulation time 1020270466 ps
CPU time 20.76 seconds
Started Jul 15 07:17:58 PM PDT 24
Finished Jul 15 07:19:57 PM PDT 24
Peak memory 245772 kb
Host smart-22b06d56-f608-452b-8a4e-c5edcc97a3ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=261096429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.261096429
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3548368863
Short name T118
Test name
Test status
Simulation time 885552743 ps
CPU time 87.91 seconds
Started Jul 15 07:18:02 PM PDT 24
Finished Jul 15 07:21:17 PM PDT 24
Peak memory 257220 kb
Host smart-93988438-ef96-4c31-95f0-f03f1abe3156
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3548368863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3548368863
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2871410808
Short name T127
Test name
Test status
Simulation time 2404595232 ps
CPU time 294.89 seconds
Started Jul 15 07:18:04 PM PDT 24
Finished Jul 15 07:24:39 PM PDT 24
Peak memory 265564 kb
Host smart-d3e677fd-c337-4b8b-9a7e-f7841563ef0a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871410808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2871410808
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2325453552
Short name T741
Test name
Test status
Simulation time 257848553 ps
CPU time 13.28 seconds
Started Jul 15 07:19:08 PM PDT 24
Finished Jul 15 07:20:32 PM PDT 24
Peak memory 248752 kb
Host smart-ba380951-4c75-4477-9fa1-e6bd39b218ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2325453552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2325453552
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4276976933
Short name T819
Test name
Test status
Simulation time 123569013 ps
CPU time 10.44 seconds
Started Jul 15 07:18:09 PM PDT 24
Finished Jul 15 07:20:13 PM PDT 24
Peak memory 251212 kb
Host smart-5152ccbb-0701-44c1-b165-72bbc3829956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276976933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.4276976933
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1530020003
Short name T822
Test name
Test status
Simulation time 32676826 ps
CPU time 3.13 seconds
Started Jul 15 07:18:16 PM PDT 24
Finished Jul 15 07:20:02 PM PDT 24
Peak memory 237580 kb
Host smart-c152852a-b028-4bcf-a8df-d7f0d6250898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1530020003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1530020003
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.63940815
Short name T149
Test name
Test status
Simulation time 11243720 ps
CPU time 1.55 seconds
Started Jul 15 07:18:12 PM PDT 24
Finished Jul 15 07:20:05 PM PDT 24
Peak memory 237576 kb
Host smart-774b19fa-e69c-4b71-9de3-d5b62ef1a566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=63940815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.63940815
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1281907635
Short name T808
Test name
Test status
Simulation time 2791770954 ps
CPU time 24.62 seconds
Started Jul 15 07:18:12 PM PDT 24
Finished Jul 15 07:20:15 PM PDT 24
Peak memory 245836 kb
Host smart-6bf47a77-cf99-4039-87e3-c38a610b4a44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1281907635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1281907635
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.521601218
Short name T143
Test name
Test status
Simulation time 2320299414 ps
CPU time 272.47 seconds
Started Jul 15 07:18:03 PM PDT 24
Finished Jul 15 07:24:22 PM PDT 24
Peak memory 265420 kb
Host smart-94064a72-cf29-4ccf-81cf-c2b983d85a65
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521601218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.521601218
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2697754414
Short name T779
Test name
Test status
Simulation time 4718328809 ps
CPU time 22.69 seconds
Started Jul 15 07:18:11 PM PDT 24
Finished Jul 15 07:20:13 PM PDT 24
Peak memory 248848 kb
Host smart-5375f69c-d130-496d-8703-6ddfd358fbb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2697754414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2697754414
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2897724514
Short name T747
Test name
Test status
Simulation time 2055207934 ps
CPU time 10.68 seconds
Started Jul 15 07:18:22 PM PDT 24
Finished Jul 15 07:20:17 PM PDT 24
Peak memory 255952 kb
Host smart-98e5628c-0c68-4580-a3fc-db10132acabf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897724514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2897724514
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3926507172
Short name T735
Test name
Test status
Simulation time 111212948 ps
CPU time 4.77 seconds
Started Jul 15 07:18:13 PM PDT 24
Finished Jul 15 07:19:55 PM PDT 24
Peak memory 236560 kb
Host smart-f0fb108f-906b-49a3-95cb-ffa0d58dead7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3926507172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3926507172
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1851468478
Short name T798
Test name
Test status
Simulation time 10984980 ps
CPU time 1.62 seconds
Started Jul 15 07:18:10 PM PDT 24
Finished Jul 15 07:20:00 PM PDT 24
Peak memory 237548 kb
Host smart-8bdc37d7-3a75-406e-b743-9d47bf5a8f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1851468478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1851468478
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3115026066
Short name T823
Test name
Test status
Simulation time 598266526 ps
CPU time 10.89 seconds
Started Jul 15 07:18:10 PM PDT 24
Finished Jul 15 07:20:00 PM PDT 24
Peak memory 245772 kb
Host smart-1d4d6942-2344-46ec-bccc-cdbf729f5583
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3115026066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3115026066
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2193972064
Short name T124
Test name
Test status
Simulation time 5397418682 ps
CPU time 93.94 seconds
Started Jul 15 07:18:22 PM PDT 24
Finished Jul 15 07:21:38 PM PDT 24
Peak memory 257140 kb
Host smart-08f024c0-a0db-4792-a982-f320591de38b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2193972064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2193972064
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2930893707
Short name T797
Test name
Test status
Simulation time 363504335 ps
CPU time 10.52 seconds
Started Jul 15 07:18:14 PM PDT 24
Finished Jul 15 07:20:01 PM PDT 24
Peak memory 248996 kb
Host smart-a62d8a91-cb53-40f4-9f78-5bdbae942d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2930893707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2930893707
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.476247500
Short name T42
Test name
Test status
Simulation time 23630555051 ps
CPU time 1331.24 seconds
Started Jul 15 05:10:59 PM PDT 24
Finished Jul 15 05:33:12 PM PDT 24
Peak memory 266720 kb
Host smart-5faf50c8-e2fa-498e-a77f-5b2b91989ab5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476247500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.476247500
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.475740516
Short name T499
Test name
Test status
Simulation time 205149628 ps
CPU time 7.76 seconds
Started Jul 15 05:11:02 PM PDT 24
Finished Jul 15 05:11:11 PM PDT 24
Peak memory 249148 kb
Host smart-ee05d46f-7b24-4dc5-a565-1b1dee5ecb6c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=475740516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.475740516
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.478140583
Short name T373
Test name
Test status
Simulation time 1605641545 ps
CPU time 163.3 seconds
Started Jul 15 05:10:54 PM PDT 24
Finished Jul 15 05:13:41 PM PDT 24
Peak memory 257080 kb
Host smart-be10a02b-ab54-4a2d-a3f8-be12b10a87ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47814
0583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.478140583
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2825757770
Short name T574
Test name
Test status
Simulation time 1247935739 ps
CPU time 66.75 seconds
Started Jul 15 05:10:53 PM PDT 24
Finished Jul 15 05:12:04 PM PDT 24
Peak memory 249284 kb
Host smart-c400a7d9-53e1-4e56-98eb-79a1e10f9f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28257
57770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2825757770
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2340210640
Short name T420
Test name
Test status
Simulation time 49411039350 ps
CPU time 3128 seconds
Started Jul 15 05:10:59 PM PDT 24
Finished Jul 15 06:03:09 PM PDT 24
Peak memory 290024 kb
Host smart-4b5697c9-4966-4c34-b794-fa9d261039b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340210640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2340210640
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1290917605
Short name T619
Test name
Test status
Simulation time 2208652005 ps
CPU time 31.04 seconds
Started Jul 15 05:10:51 PM PDT 24
Finished Jul 15 05:11:28 PM PDT 24
Peak memory 249240 kb
Host smart-ae9dc1ee-d6f7-433e-81cf-1e486bb09450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12909
17605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1290917605
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2505189224
Short name T30
Test name
Test status
Simulation time 837186009 ps
CPU time 12.92 seconds
Started Jul 15 05:11:00 PM PDT 24
Finished Jul 15 05:11:14 PM PDT 24
Peak memory 273936 kb
Host smart-a46ad21a-d22b-411a-9ad9-aa762eabb580
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2505189224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2505189224
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.10567338
Short name T542
Test name
Test status
Simulation time 442235643 ps
CPU time 38.4 seconds
Started Jul 15 05:10:59 PM PDT 24
Finished Jul 15 05:11:38 PM PDT 24
Peak memory 249564 kb
Host smart-74178d98-e3b8-4c0b-8cca-54d3011b58ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10567
338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.10567338
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2995016821
Short name T700
Test name
Test status
Simulation time 886270370 ps
CPU time 22.01 seconds
Started Jul 15 05:10:51 PM PDT 24
Finished Jul 15 05:11:19 PM PDT 24
Peak memory 257256 kb
Host smart-d8c0b8f3-683f-43d3-b190-237de3976cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29950
16821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2995016821
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4066250016
Short name T236
Test name
Test status
Simulation time 78456025021 ps
CPU time 984.14 seconds
Started Jul 15 05:11:07 PM PDT 24
Finished Jul 15 05:27:33 PM PDT 24
Peak memory 272784 kb
Host smart-ba3281db-7334-47a0-8987-ab110ac11bba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066250016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4066250016
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2522463247
Short name T669
Test name
Test status
Simulation time 4981186313 ps
CPU time 260.56 seconds
Started Jul 15 05:11:09 PM PDT 24
Finished Jul 15 05:15:30 PM PDT 24
Peak memory 257076 kb
Host smart-dc056045-a281-49f0-ba79-b0c448674a90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25224
63247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2522463247
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.809960514
Short name T394
Test name
Test status
Simulation time 341013678 ps
CPU time 35.63 seconds
Started Jul 15 05:11:06 PM PDT 24
Finished Jul 15 05:11:44 PM PDT 24
Peak memory 256908 kb
Host smart-efaeb6a3-a4ae-4747-9168-cb999a2bb662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80996
0514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.809960514
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3232613325
Short name T668
Test name
Test status
Simulation time 51392818760 ps
CPU time 2804.28 seconds
Started Jul 15 05:11:07 PM PDT 24
Finished Jul 15 05:57:53 PM PDT 24
Peak memory 290296 kb
Host smart-1753c0c4-3000-4133-b3c1-3fb3ef7ab8a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232613325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3232613325
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.33530147
Short name T450
Test name
Test status
Simulation time 24759612286 ps
CPU time 1119.82 seconds
Started Jul 15 05:11:11 PM PDT 24
Finished Jul 15 05:29:52 PM PDT 24
Peak memory 273736 kb
Host smart-456f4059-a1de-493f-9d2a-449e2498dc15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33530147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.33530147
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1701763097
Short name T610
Test name
Test status
Simulation time 915084206 ps
CPU time 47.18 seconds
Started Jul 15 05:11:09 PM PDT 24
Finished Jul 15 05:11:58 PM PDT 24
Peak memory 256676 kb
Host smart-49b02731-b56c-46c4-b85c-9db849b46a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17017
63097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1701763097
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.383659665
Short name T708
Test name
Test status
Simulation time 423436109 ps
CPU time 14.28 seconds
Started Jul 15 05:11:07 PM PDT 24
Finished Jul 15 05:11:22 PM PDT 24
Peak memory 256844 kb
Host smart-7c411a73-5023-437d-9d71-4c54cf3d958a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38365
9665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.383659665
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4063496433
Short name T11
Test name
Test status
Simulation time 612644151 ps
CPU time 26.69 seconds
Started Jul 15 05:11:14 PM PDT 24
Finished Jul 15 05:11:46 PM PDT 24
Peak memory 274384 kb
Host smart-3e22e918-0315-4011-b295-02c0b817f1e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4063496433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4063496433
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.414282223
Short name T212
Test name
Test status
Simulation time 487050807 ps
CPU time 34.49 seconds
Started Jul 15 05:11:12 PM PDT 24
Finished Jul 15 05:11:48 PM PDT 24
Peak memory 248932 kb
Host smart-cdbcb1ab-1bfc-4611-a488-1c29f63e15c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41428
2223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.414282223
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3287744337
Short name T445
Test name
Test status
Simulation time 561872170 ps
CPU time 17.98 seconds
Started Jul 15 05:11:08 PM PDT 24
Finished Jul 15 05:11:27 PM PDT 24
Peak memory 257316 kb
Host smart-e71e3a47-db9d-4ffc-af59-9833348fc2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32877
44337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3287744337
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2149979918
Short name T551
Test name
Test status
Simulation time 93322888919 ps
CPU time 2859.66 seconds
Started Jul 15 05:11:07 PM PDT 24
Finished Jul 15 05:58:48 PM PDT 24
Peak memory 289944 kb
Host smart-67762215-7726-4e60-b269-64a4229855e9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149979918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2149979918
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.202496967
Short name T59
Test name
Test status
Simulation time 29356459758 ps
CPU time 3265.36 seconds
Started Jul 15 05:11:13 PM PDT 24
Finished Jul 15 06:05:42 PM PDT 24
Peak memory 322860 kb
Host smart-411560a7-3f3c-454a-a11a-6c2c6bce1e1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202496967 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.202496967
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1243465507
Short name T191
Test name
Test status
Simulation time 39766071 ps
CPU time 2.21 seconds
Started Jul 15 05:12:42 PM PDT 24
Finished Jul 15 05:12:45 PM PDT 24
Peak memory 249544 kb
Host smart-9e954f60-973b-45f2-90bb-a15a6ba1e3ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1243465507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1243465507
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1680900598
Short name T449
Test name
Test status
Simulation time 7840432511 ps
CPU time 850.86 seconds
Started Jul 15 05:12:44 PM PDT 24
Finished Jul 15 05:26:55 PM PDT 24
Peak memory 273804 kb
Host smart-ed4b69d2-67d5-4242-8eee-06d0069761be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680900598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1680900598
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1322689569
Short name T647
Test name
Test status
Simulation time 768091846 ps
CPU time 19.07 seconds
Started Jul 15 05:12:42 PM PDT 24
Finished Jul 15 05:13:02 PM PDT 24
Peak memory 249100 kb
Host smart-6adfc21e-98f2-4ab6-a9a8-23e4990da171
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1322689569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1322689569
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1383613140
Short name T247
Test name
Test status
Simulation time 7866060480 ps
CPU time 150.05 seconds
Started Jul 15 05:12:32 PM PDT 24
Finished Jul 15 05:15:02 PM PDT 24
Peak memory 257516 kb
Host smart-df9b7a61-eaf1-4ad4-bfca-570cfd1cc89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13836
13140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1383613140
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.202126607
Short name T617
Test name
Test status
Simulation time 623468408 ps
CPU time 39.2 seconds
Started Jul 15 05:12:34 PM PDT 24
Finished Jul 15 05:13:13 PM PDT 24
Peak memory 249228 kb
Host smart-d066dee6-d014-4aee-bc64-55770de3c371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20212
6607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.202126607
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.142786277
Short name T295
Test name
Test status
Simulation time 114043723020 ps
CPU time 1557 seconds
Started Jul 15 05:12:43 PM PDT 24
Finished Jul 15 05:38:41 PM PDT 24
Peak memory 273888 kb
Host smart-bb447dc0-7cb8-4f05-a073-e11ba4a4ebc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142786277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.142786277
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3674833829
Short name T566
Test name
Test status
Simulation time 39884260960 ps
CPU time 1508.22 seconds
Started Jul 15 05:12:42 PM PDT 24
Finished Jul 15 05:37:52 PM PDT 24
Peak memory 289744 kb
Host smart-e5da26f5-6db7-466f-8648-73ffa2dfe7c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674833829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3674833829
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2626372617
Short name T306
Test name
Test status
Simulation time 2677314928 ps
CPU time 115.16 seconds
Started Jul 15 05:12:43 PM PDT 24
Finished Jul 15 05:14:39 PM PDT 24
Peak memory 249028 kb
Host smart-534595eb-a22a-4879-be9f-1620591cd119
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626372617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2626372617
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1226220991
Short name T655
Test name
Test status
Simulation time 463704995 ps
CPU time 16.08 seconds
Started Jul 15 05:12:32 PM PDT 24
Finished Jul 15 05:12:49 PM PDT 24
Peak memory 249224 kb
Host smart-b89b312e-5b70-48de-a96d-b72bf2cc393b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12262
20991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1226220991
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3636915615
Short name T609
Test name
Test status
Simulation time 479635476 ps
CPU time 31.88 seconds
Started Jul 15 05:12:35 PM PDT 24
Finished Jul 15 05:13:07 PM PDT 24
Peak memory 256948 kb
Host smart-ac00d860-d579-4f6e-b344-f8be589906d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36369
15615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3636915615
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2262084661
Short name T2
Test name
Test status
Simulation time 1015772611 ps
CPU time 16.27 seconds
Started Jul 15 05:12:43 PM PDT 24
Finished Jul 15 05:13:00 PM PDT 24
Peak memory 248468 kb
Host smart-4191f423-850f-4fc0-bf98-4627a19f4266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22620
84661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2262084661
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1110082547
Short name T454
Test name
Test status
Simulation time 715005035 ps
CPU time 40.92 seconds
Started Jul 15 05:12:37 PM PDT 24
Finished Jul 15 05:13:18 PM PDT 24
Peak memory 257372 kb
Host smart-7a476369-b6a7-4a22-8821-4f798802ad17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11100
82547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1110082547
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.861006084
Short name T221
Test name
Test status
Simulation time 33894528631 ps
CPU time 1038.52 seconds
Started Jul 15 05:12:42 PM PDT 24
Finished Jul 15 05:30:02 PM PDT 24
Peak memory 273772 kb
Host smart-01dbe976-6439-4219-a5c8-46c1ab40d24d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861006084 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.861006084
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1562701430
Short name T200
Test name
Test status
Simulation time 104682171 ps
CPU time 3.18 seconds
Started Jul 15 05:12:52 PM PDT 24
Finished Jul 15 05:12:56 PM PDT 24
Peak memory 249544 kb
Host smart-29f55928-5e1c-4734-bb47-69fcd7f32239
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1562701430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1562701430
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2715231471
Short name T104
Test name
Test status
Simulation time 111221127884 ps
CPU time 2021.72 seconds
Started Jul 15 05:12:53 PM PDT 24
Finished Jul 15 05:46:36 PM PDT 24
Peak memory 281688 kb
Host smart-35fa7ec6-70b4-4cbb-9a3b-c6a21c9877c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715231471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2715231471
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3702315522
Short name T6
Test name
Test status
Simulation time 283957738 ps
CPU time 15.68 seconds
Started Jul 15 05:12:53 PM PDT 24
Finished Jul 15 05:13:09 PM PDT 24
Peak memory 249140 kb
Host smart-afdd424c-6e67-421f-a466-3d18d2c6d40d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3702315522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3702315522
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3690013096
Short name T400
Test name
Test status
Simulation time 2164185614 ps
CPU time 116.33 seconds
Started Jul 15 05:12:54 PM PDT 24
Finished Jul 15 05:14:51 PM PDT 24
Peak memory 256636 kb
Host smart-ec3f7288-6939-4f10-a04a-c2afb0bccfc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36900
13096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3690013096
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.723855642
Short name T272
Test name
Test status
Simulation time 4462840810 ps
CPU time 70.97 seconds
Started Jul 15 05:12:54 PM PDT 24
Finished Jul 15 05:14:06 PM PDT 24
Peak memory 256524 kb
Host smart-c1258629-b513-43c9-b28a-1efbd973b0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72385
5642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.723855642
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2108268737
Short name T324
Test name
Test status
Simulation time 71312645302 ps
CPU time 1818.96 seconds
Started Jul 15 05:12:52 PM PDT 24
Finished Jul 15 05:43:11 PM PDT 24
Peak memory 273724 kb
Host smart-ace4b821-2e4c-46b3-8b47-56d17a765cfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108268737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2108268737
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.178917397
Short name T32
Test name
Test status
Simulation time 75688999910 ps
CPU time 1261.18 seconds
Started Jul 15 05:12:53 PM PDT 24
Finished Jul 15 05:33:55 PM PDT 24
Peak memory 288084 kb
Host smart-5530d19f-7690-4120-a5cf-98edaaaa3a75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178917397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.178917397
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.840554235
Short name T292
Test name
Test status
Simulation time 8833442294 ps
CPU time 359.8 seconds
Started Jul 15 05:12:54 PM PDT 24
Finished Jul 15 05:18:55 PM PDT 24
Peak memory 249220 kb
Host smart-2fe933c8-0950-4a4f-888c-703ef9bbb44a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840554235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.840554235
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.4218178663
Short name T349
Test name
Test status
Simulation time 5497885437 ps
CPU time 59.6 seconds
Started Jul 15 05:12:52 PM PDT 24
Finished Jul 15 05:13:52 PM PDT 24
Peak memory 256776 kb
Host smart-983eaa90-2654-4b10-a48c-77d0345f7ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42181
78663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.4218178663
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1025614112
Short name T580
Test name
Test status
Simulation time 379399505 ps
CPU time 13.17 seconds
Started Jul 15 05:12:54 PM PDT 24
Finished Jul 15 05:13:07 PM PDT 24
Peak memory 255128 kb
Host smart-b512a056-5b02-422b-9716-6727aff64389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10256
14112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1025614112
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1506596310
Short name T176
Test name
Test status
Simulation time 898794054 ps
CPU time 22.63 seconds
Started Jul 15 05:12:43 PM PDT 24
Finished Jul 15 05:13:06 PM PDT 24
Peak memory 256724 kb
Host smart-b5db9d4e-40d1-49b1-a71c-2706f357b215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15065
96310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1506596310
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.114016895
Short name T37
Test name
Test status
Simulation time 57270936503 ps
CPU time 4591.4 seconds
Started Jul 15 05:12:52 PM PDT 24
Finished Jul 15 06:29:24 PM PDT 24
Peak memory 287328 kb
Host smart-492c215d-9967-4e0f-99b5-3bc71b42fce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114016895 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.114016895
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3365249478
Short name T651
Test name
Test status
Simulation time 48759699328 ps
CPU time 2818.67 seconds
Started Jul 15 05:13:01 PM PDT 24
Finished Jul 15 06:00:01 PM PDT 24
Peak memory 286196 kb
Host smart-b1435153-3a24-43ea-b359-f188c1779479
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365249478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3365249478
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1528209129
Short name T516
Test name
Test status
Simulation time 634682763 ps
CPU time 9.49 seconds
Started Jul 15 05:13:02 PM PDT 24
Finished Jul 15 05:13:12 PM PDT 24
Peak memory 249156 kb
Host smart-a0931eeb-64aa-415a-ba67-8f7eff31f5c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1528209129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1528209129
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2615726122
Short name T690
Test name
Test status
Simulation time 3429341368 ps
CPU time 182.19 seconds
Started Jul 15 05:13:02 PM PDT 24
Finished Jul 15 05:16:05 PM PDT 24
Peak memory 257124 kb
Host smart-26cf6b4e-cc5a-42ea-aeab-9560a4f79d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26157
26122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2615726122
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2979967109
Short name T70
Test name
Test status
Simulation time 331496675 ps
CPU time 20.73 seconds
Started Jul 15 05:12:54 PM PDT 24
Finished Jul 15 05:13:15 PM PDT 24
Peak memory 248740 kb
Host smart-3b9e9d97-ad16-4463-a630-8e9fa5578e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29799
67109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2979967109
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3740323411
Short name T538
Test name
Test status
Simulation time 7742511879 ps
CPU time 977.47 seconds
Started Jul 15 05:13:02 PM PDT 24
Finished Jul 15 05:29:20 PM PDT 24
Peak memory 273792 kb
Host smart-dafe3d0e-432a-4a30-b16c-e60ff586d4cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740323411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3740323411
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2773620402
Short name T433
Test name
Test status
Simulation time 65332693932 ps
CPU time 1900.21 seconds
Started Jul 15 05:13:02 PM PDT 24
Finished Jul 15 05:44:42 PM PDT 24
Peak memory 273888 kb
Host smart-19ac2ea3-c373-49bd-be04-80a6f77bbbe6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773620402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2773620402
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.110452006
Short name T527
Test name
Test status
Simulation time 31617905246 ps
CPU time 172.25 seconds
Started Jul 15 05:13:03 PM PDT 24
Finished Jul 15 05:15:56 PM PDT 24
Peak memory 248924 kb
Host smart-90adcc33-c7cc-4f3a-9e3c-c0ae5a00f362
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110452006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.110452006
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.519907182
Short name T354
Test name
Test status
Simulation time 802798456 ps
CPU time 19.36 seconds
Started Jul 15 05:12:57 PM PDT 24
Finished Jul 15 05:13:17 PM PDT 24
Peak memory 249232 kb
Host smart-3dd8d0a4-9d6b-4c05-9a6d-6e6e2aca538e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51990
7182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.519907182
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3506781629
Short name T411
Test name
Test status
Simulation time 2504981331 ps
CPU time 26.65 seconds
Started Jul 15 05:12:54 PM PDT 24
Finished Jul 15 05:13:21 PM PDT 24
Peak memory 249384 kb
Host smart-6a0c9368-bb48-4f00-a06c-d282c90728f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35067
81629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3506781629
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.42737069
Short name T179
Test name
Test status
Simulation time 3032516307 ps
CPU time 56.42 seconds
Started Jul 15 05:13:02 PM PDT 24
Finished Jul 15 05:13:59 PM PDT 24
Peak memory 248880 kb
Host smart-f1c9c7fe-a2f5-4773-a534-4d5e495e59b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42737
069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.42737069
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.489468931
Short name T369
Test name
Test status
Simulation time 1372803214 ps
CPU time 33.66 seconds
Started Jul 15 05:12:53 PM PDT 24
Finished Jul 15 05:13:27 PM PDT 24
Peak memory 257380 kb
Host smart-830c2956-d678-4374-bca1-a055e21633a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48946
8931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.489468931
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.969677760
Short name T237
Test name
Test status
Simulation time 12627245385 ps
CPU time 1372.5 seconds
Started Jul 15 05:13:02 PM PDT 24
Finished Jul 15 05:35:55 PM PDT 24
Peak memory 289668 kb
Host smart-0481d950-f5da-43ac-b534-59ca9ceab4ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969677760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.969677760
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1981949854
Short name T181
Test name
Test status
Simulation time 74734479908 ps
CPU time 7673.43 seconds
Started Jul 15 05:13:04 PM PDT 24
Finished Jul 15 07:20:59 PM PDT 24
Peak memory 355000 kb
Host smart-3899ce83-64e4-4e62-97d4-42d9c612b153
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981949854 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1981949854
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1992103970
Short name T593
Test name
Test status
Simulation time 29071048997 ps
CPU time 1790.22 seconds
Started Jul 15 05:13:06 PM PDT 24
Finished Jul 15 05:42:57 PM PDT 24
Peak memory 273732 kb
Host smart-aff46403-4cee-4650-b53b-285ec1e80213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992103970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1992103970
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1265874106
Short name T424
Test name
Test status
Simulation time 157883874 ps
CPU time 8.88 seconds
Started Jul 15 05:13:02 PM PDT 24
Finished Jul 15 05:13:11 PM PDT 24
Peak memory 249132 kb
Host smart-32f5f99d-ae2d-4cf3-816c-fb411e0cd7c3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1265874106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1265874106
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1925949318
Short name T226
Test name
Test status
Simulation time 590428038 ps
CPU time 32.87 seconds
Started Jul 15 05:13:03 PM PDT 24
Finished Jul 15 05:13:37 PM PDT 24
Peak memory 256824 kb
Host smart-71d78902-50fc-4677-a994-b1884043f0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19259
49318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1925949318
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1007857998
Short name T98
Test name
Test status
Simulation time 1815294332 ps
CPU time 69.31 seconds
Started Jul 15 05:13:03 PM PDT 24
Finished Jul 15 05:14:12 PM PDT 24
Peak memory 249116 kb
Host smart-51fd992c-33b2-45c3-a2bd-bc01d518734a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10078
57998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1007857998
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2686972455
Short name T547
Test name
Test status
Simulation time 49824792889 ps
CPU time 1745.41 seconds
Started Jul 15 05:13:09 PM PDT 24
Finished Jul 15 05:42:15 PM PDT 24
Peak memory 289188 kb
Host smart-7a3e1a9e-c7bd-47f8-8d69-4dd8c60c44f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686972455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2686972455
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.4112892585
Short name T643
Test name
Test status
Simulation time 9289807569 ps
CPU time 974.46 seconds
Started Jul 15 05:13:04 PM PDT 24
Finished Jul 15 05:29:19 PM PDT 24
Peak memory 273160 kb
Host smart-7656d22f-2dee-4460-b214-28e86fc7fcbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112892585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.4112892585
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2130667199
Short name T303
Test name
Test status
Simulation time 63515826229 ps
CPU time 638.03 seconds
Started Jul 15 05:13:08 PM PDT 24
Finished Jul 15 05:23:46 PM PDT 24
Peak memory 249208 kb
Host smart-3fd357d5-f077-4de5-9a8d-fa555a85d031
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130667199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2130667199
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3615818084
Short name T683
Test name
Test status
Simulation time 620500999 ps
CPU time 18.52 seconds
Started Jul 15 05:13:02 PM PDT 24
Finished Jul 15 05:13:21 PM PDT 24
Peak memory 256748 kb
Host smart-51102a6e-2593-483a-acd2-9e0d7a8b29f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36158
18084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3615818084
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.4268212020
Short name T602
Test name
Test status
Simulation time 2096521049 ps
CPU time 60.75 seconds
Started Jul 15 05:13:08 PM PDT 24
Finished Jul 15 05:14:09 PM PDT 24
Peak memory 249124 kb
Host smart-90985117-2d3f-40d5-af4c-2dedc5849b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42682
12020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.4268212020
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.4203043982
Short name T45
Test name
Test status
Simulation time 1111300177 ps
CPU time 65.4 seconds
Started Jul 15 05:13:08 PM PDT 24
Finished Jul 15 05:14:14 PM PDT 24
Peak memory 257228 kb
Host smart-47fa3179-d2d8-4ded-85bc-d219412f787b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42030
43982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4203043982
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.538679588
Short name T511
Test name
Test status
Simulation time 293741697 ps
CPU time 16.29 seconds
Started Jul 15 05:13:09 PM PDT 24
Finished Jul 15 05:13:26 PM PDT 24
Peak memory 256500 kb
Host smart-14d74b51-3865-4a58-a564-9bed2fec2976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53867
9588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.538679588
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3680963800
Short name T24
Test name
Test status
Simulation time 79485918189 ps
CPU time 1963.31 seconds
Started Jul 15 05:13:09 PM PDT 24
Finished Jul 15 05:45:53 PM PDT 24
Peak memory 305836 kb
Host smart-c0e02c27-d093-450f-9638-596ba964264a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680963800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3680963800
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3856780875
Short name T171
Test name
Test status
Simulation time 28022996926 ps
CPU time 2771.53 seconds
Started Jul 15 05:13:11 PM PDT 24
Finished Jul 15 05:59:23 PM PDT 24
Peak memory 321460 kb
Host smart-c82793ab-6543-49de-8aa8-ad91a31e5ff9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856780875 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3856780875
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.243776898
Short name T16
Test name
Test status
Simulation time 147987969 ps
CPU time 2.2 seconds
Started Jul 15 05:13:24 PM PDT 24
Finished Jul 15 05:13:27 PM PDT 24
Peak memory 249436 kb
Host smart-86a6d918-fcd5-4d7e-aece-9fa9ba76fdf3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=243776898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.243776898
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1584656757
Short name T437
Test name
Test status
Simulation time 83645871694 ps
CPU time 2382.58 seconds
Started Jul 15 05:13:13 PM PDT 24
Finished Jul 15 05:52:56 PM PDT 24
Peak memory 283888 kb
Host smart-1e8f8f66-2476-4630-b4f0-169cd804347a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584656757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1584656757
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2662686737
Short name T15
Test name
Test status
Simulation time 531312163 ps
CPU time 8.58 seconds
Started Jul 15 05:13:24 PM PDT 24
Finished Jul 15 05:13:33 PM PDT 24
Peak memory 249080 kb
Host smart-ecba5dc2-e4bb-4674-a284-1f72ea99cd9a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2662686737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2662686737
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1544014936
Short name T430
Test name
Test status
Simulation time 2306555295 ps
CPU time 45.38 seconds
Started Jul 15 05:13:12 PM PDT 24
Finished Jul 15 05:13:58 PM PDT 24
Peak memory 256728 kb
Host smart-c412731a-51d7-4e08-88cb-5d32debe8c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15440
14936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1544014936
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.813418163
Short name T432
Test name
Test status
Simulation time 2107716819 ps
CPU time 17.01 seconds
Started Jul 15 05:13:12 PM PDT 24
Finished Jul 15 05:13:29 PM PDT 24
Peak memory 249520 kb
Host smart-8f0ab6f1-e026-4097-9c05-fcb2e2d663ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81341
8163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.813418163
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3769036959
Short name T329
Test name
Test status
Simulation time 131345701796 ps
CPU time 1678 seconds
Started Jul 15 05:13:26 PM PDT 24
Finished Jul 15 05:41:25 PM PDT 24
Peak memory 273228 kb
Host smart-adb57643-50b7-4499-94cb-29e0dea24aed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769036959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3769036959
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3449922681
Short name T601
Test name
Test status
Simulation time 21502714232 ps
CPU time 1418.34 seconds
Started Jul 15 05:13:23 PM PDT 24
Finished Jul 15 05:37:02 PM PDT 24
Peak memory 285676 kb
Host smart-dd1fd502-8f8f-4172-bcfe-c3965dc1a81e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449922681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3449922681
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.598590431
Short name T214
Test name
Test status
Simulation time 3949365109 ps
CPU time 86.66 seconds
Started Jul 15 05:13:11 PM PDT 24
Finished Jul 15 05:14:39 PM PDT 24
Peak memory 254840 kb
Host smart-c9e2b3bb-733a-4348-a24a-8d87772a6da5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598590431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.598590431
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3774416190
Short name T570
Test name
Test status
Simulation time 921720193 ps
CPU time 58.47 seconds
Started Jul 15 05:13:13 PM PDT 24
Finished Jul 15 05:14:12 PM PDT 24
Peak memory 256648 kb
Host smart-515d2225-8aa3-44c4-92f3-463051f8ced2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37744
16190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3774416190
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1544454699
Short name T529
Test name
Test status
Simulation time 37249255 ps
CPU time 3.14 seconds
Started Jul 15 05:13:12 PM PDT 24
Finished Jul 15 05:13:16 PM PDT 24
Peak memory 240532 kb
Host smart-6f75116d-2aeb-481b-89da-805957d091cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15444
54699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1544454699
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.359860657
Short name T388
Test name
Test status
Simulation time 1440811155 ps
CPU time 23.08 seconds
Started Jul 15 05:13:13 PM PDT 24
Finished Jul 15 05:13:37 PM PDT 24
Peak memory 248676 kb
Host smart-ed867e78-f92f-4123-b6ce-9ae502015e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35986
0657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.359860657
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3679607431
Short name T489
Test name
Test status
Simulation time 4028352095 ps
CPU time 20.73 seconds
Started Jul 15 05:13:12 PM PDT 24
Finished Jul 15 05:13:33 PM PDT 24
Peak memory 249396 kb
Host smart-533de67c-0b34-4f5f-831c-672aad33ecbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36796
07431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3679607431
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2870360232
Short name T34
Test name
Test status
Simulation time 2518134137 ps
CPU time 163.71 seconds
Started Jul 15 05:13:23 PM PDT 24
Finished Jul 15 05:16:07 PM PDT 24
Peak memory 257460 kb
Host smart-8b332e31-c6fa-46ff-9cd8-6e038db6dccb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870360232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2870360232
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3117395848
Short name T204
Test name
Test status
Simulation time 294017445 ps
CPU time 3.75 seconds
Started Jul 15 05:13:26 PM PDT 24
Finished Jul 15 05:13:31 PM PDT 24
Peak memory 249508 kb
Host smart-23d6a5c2-1d38-4fcf-954a-df8f0107db26
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3117395848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3117395848
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2365934714
Short name T490
Test name
Test status
Simulation time 29541378502 ps
CPU time 1527 seconds
Started Jul 15 05:13:24 PM PDT 24
Finished Jul 15 05:38:52 PM PDT 24
Peak memory 290300 kb
Host smart-bf132f6d-9ecc-4343-8247-08e8b942ccfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365934714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2365934714
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3074115444
Short name T588
Test name
Test status
Simulation time 384847518 ps
CPU time 19.77 seconds
Started Jul 15 05:13:22 PM PDT 24
Finished Jul 15 05:13:43 PM PDT 24
Peak memory 249108 kb
Host smart-a7c9aacb-9f75-4af5-81b3-ce210d177c35
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3074115444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3074115444
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3349563568
Short name T360
Test name
Test status
Simulation time 1753315266 ps
CPU time 86.97 seconds
Started Jul 15 05:13:23 PM PDT 24
Finished Jul 15 05:14:51 PM PDT 24
Peak memory 256908 kb
Host smart-315ae1da-bd2b-4f49-b7ae-7a82b780d8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33495
63568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3349563568
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1863060410
Short name T467
Test name
Test status
Simulation time 50690244 ps
CPU time 5.37 seconds
Started Jul 15 05:13:22 PM PDT 24
Finished Jul 15 05:13:27 PM PDT 24
Peak memory 248660 kb
Host smart-9ef9d2ab-1759-4de2-b484-89688ef6ad7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18630
60410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1863060410
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3183129069
Short name T277
Test name
Test status
Simulation time 31835638704 ps
CPU time 713.5 seconds
Started Jul 15 05:13:24 PM PDT 24
Finished Jul 15 05:25:18 PM PDT 24
Peak memory 272968 kb
Host smart-50f00fc9-32f1-4f44-9966-0ca041e56822
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183129069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3183129069
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.571335023
Short name T665
Test name
Test status
Simulation time 51043663216 ps
CPU time 1756.67 seconds
Started Jul 15 05:13:24 PM PDT 24
Finished Jul 15 05:42:42 PM PDT 24
Peak memory 273644 kb
Host smart-45907b70-7195-45a1-925f-e6b4a1db3ba7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571335023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.571335023
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.112076873
Short name T621
Test name
Test status
Simulation time 2354027713 ps
CPU time 103.88 seconds
Started Jul 15 05:13:22 PM PDT 24
Finished Jul 15 05:15:06 PM PDT 24
Peak memory 249364 kb
Host smart-d9ae57a5-89a1-44cc-b6ae-250ca2842b07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112076873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.112076873
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1969503380
Short name T422
Test name
Test status
Simulation time 84139527 ps
CPU time 4.97 seconds
Started Jul 15 05:13:23 PM PDT 24
Finished Jul 15 05:13:28 PM PDT 24
Peak memory 249224 kb
Host smart-e3facebf-c73f-4d3a-a599-3589f0e78530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19695
03380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1969503380
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2908586613
Short name T625
Test name
Test status
Simulation time 3238505584 ps
CPU time 52.2 seconds
Started Jul 15 05:13:26 PM PDT 24
Finished Jul 15 05:14:19 PM PDT 24
Peak memory 256940 kb
Host smart-363a47e0-1751-4a89-8c2c-9bd6dcd38092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29085
86613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2908586613
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1644930246
Short name T684
Test name
Test status
Simulation time 492065459 ps
CPU time 15.56 seconds
Started Jul 15 05:13:24 PM PDT 24
Finished Jul 15 05:13:40 PM PDT 24
Peak memory 249260 kb
Host smart-fd40e6aa-22b2-47c3-940f-b0c39e8fb3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16449
30246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1644930246
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1790046985
Short name T689
Test name
Test status
Simulation time 208726713 ps
CPU time 4.16 seconds
Started Jul 15 05:13:21 PM PDT 24
Finished Jul 15 05:13:26 PM PDT 24
Peak memory 251480 kb
Host smart-283608f0-3341-4365-b05f-9c13f4027d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17900
46985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1790046985
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1317377234
Short name T541
Test name
Test status
Simulation time 44527053401 ps
CPU time 2694.75 seconds
Started Jul 15 05:13:23 PM PDT 24
Finished Jul 15 05:58:19 PM PDT 24
Peak memory 289688 kb
Host smart-ec63de56-5b4c-4002-9119-4adb0b239b8a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317377234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1317377234
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.479598827
Short name T637
Test name
Test status
Simulation time 33735448674 ps
CPU time 3494.11 seconds
Started Jul 15 05:13:24 PM PDT 24
Finished Jul 15 06:11:40 PM PDT 24
Peak memory 322724 kb
Host smart-90f8b3a4-a9fb-4ff0-a070-9de51bc24a9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479598827 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.479598827
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.957076529
Short name T63
Test name
Test status
Simulation time 46643529 ps
CPU time 3.35 seconds
Started Jul 15 05:13:31 PM PDT 24
Finished Jul 15 05:13:35 PM PDT 24
Peak memory 249496 kb
Host smart-ee8ecf22-246f-4026-b384-816c69bba67a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=957076529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.957076529
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.355556458
Short name T548
Test name
Test status
Simulation time 18321176285 ps
CPU time 1150.67 seconds
Started Jul 15 05:13:30 PM PDT 24
Finished Jul 15 05:32:42 PM PDT 24
Peak memory 282020 kb
Host smart-6d12c24b-0f91-476e-abd5-993cf03bad11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355556458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.355556458
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1416705892
Short name T366
Test name
Test status
Simulation time 870595030 ps
CPU time 11.85 seconds
Started Jul 15 05:13:30 PM PDT 24
Finished Jul 15 05:13:42 PM PDT 24
Peak memory 249168 kb
Host smart-55e1808a-a378-484a-8514-5cdfa9e667bc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1416705892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1416705892
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1758245022
Short name T39
Test name
Test status
Simulation time 6776460492 ps
CPU time 217.89 seconds
Started Jul 15 05:13:23 PM PDT 24
Finished Jul 15 05:17:02 PM PDT 24
Peak memory 257076 kb
Host smart-7a11b66f-6e9e-43e1-ba52-c667f8cbbd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17582
45022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1758245022
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3177282694
Short name T691
Test name
Test status
Simulation time 5241954354 ps
CPU time 35.1 seconds
Started Jul 15 05:13:25 PM PDT 24
Finished Jul 15 05:14:01 PM PDT 24
Peak memory 257248 kb
Host smart-60944619-4a48-4df0-9135-bd1df0eff6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31772
82694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3177282694
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2510170402
Short name T632
Test name
Test status
Simulation time 147401552563 ps
CPU time 1322.03 seconds
Started Jul 15 05:13:30 PM PDT 24
Finished Jul 15 05:35:33 PM PDT 24
Peak memory 272020 kb
Host smart-a20b6341-7864-44f8-92e0-b31ad8fd108c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510170402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2510170402
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1572795868
Short name T495
Test name
Test status
Simulation time 25518574633 ps
CPU time 1356.62 seconds
Started Jul 15 05:13:33 PM PDT 24
Finished Jul 15 05:36:10 PM PDT 24
Peak memory 284832 kb
Host smart-dc936752-c040-4ca8-a045-6a0bc9255700
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572795868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1572795868
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2903996592
Short name T469
Test name
Test status
Simulation time 462215023 ps
CPU time 29.47 seconds
Started Jul 15 05:13:24 PM PDT 24
Finished Jul 15 05:13:54 PM PDT 24
Peak memory 257180 kb
Host smart-e303b913-31d7-43be-b790-6f53ff67a69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29039
96592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2903996592
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.4231202703
Short name T654
Test name
Test status
Simulation time 2059494662 ps
CPU time 34.39 seconds
Started Jul 15 05:13:22 PM PDT 24
Finished Jul 15 05:13:57 PM PDT 24
Peak memory 249072 kb
Host smart-db7330bd-2441-49b1-8f8d-44215b029dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42312
02703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.4231202703
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1842265486
Short name T553
Test name
Test status
Simulation time 332578168 ps
CPU time 27.44 seconds
Started Jul 15 05:13:22 PM PDT 24
Finished Jul 15 05:13:50 PM PDT 24
Peak memory 257344 kb
Host smart-458c74a4-df56-455e-bb5e-457a00faf584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422
65486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1842265486
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3373072491
Short name T507
Test name
Test status
Simulation time 181514331898 ps
CPU time 2517.08 seconds
Started Jul 15 05:13:29 PM PDT 24
Finished Jul 15 05:55:27 PM PDT 24
Peak memory 285216 kb
Host smart-0ca93c12-6de5-45c7-b13c-428b9a08d9fb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373072491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3373072491
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1209375565
Short name T18
Test name
Test status
Simulation time 41308991 ps
CPU time 2.45 seconds
Started Jul 15 05:13:43 PM PDT 24
Finished Jul 15 05:13:45 PM PDT 24
Peak memory 249396 kb
Host smart-6515d8c4-7de5-42c8-925c-a4a07477461d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1209375565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1209375565
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3100221117
Short name T88
Test name
Test status
Simulation time 41098698716 ps
CPU time 2422.14 seconds
Started Jul 15 05:13:38 PM PDT 24
Finished Jul 15 05:54:01 PM PDT 24
Peak memory 282160 kb
Host smart-fa28f9ff-b4f7-430d-bc97-d910f94f65a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100221117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3100221117
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2529017660
Short name T426
Test name
Test status
Simulation time 950355668 ps
CPU time 12.06 seconds
Started Jul 15 05:13:37 PM PDT 24
Finished Jul 15 05:13:49 PM PDT 24
Peak memory 249188 kb
Host smart-5494be5a-ac2f-4b44-820c-cc6a98157803
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2529017660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2529017660
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1252078537
Short name T381
Test name
Test status
Simulation time 4596147461 ps
CPU time 41.38 seconds
Started Jul 15 05:13:37 PM PDT 24
Finished Jul 15 05:14:19 PM PDT 24
Peak memory 256776 kb
Host smart-bd96687d-6e21-4a75-9bfa-68d786e0d4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12520
78537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1252078537
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2365401775
Short name T599
Test name
Test status
Simulation time 4096672226 ps
CPU time 51.94 seconds
Started Jul 15 05:13:31 PM PDT 24
Finished Jul 15 05:14:24 PM PDT 24
Peak memory 249300 kb
Host smart-098ca69e-a0e5-4c34-a2f1-3eae4d237b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23654
01775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2365401775
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1319734271
Short name T90
Test name
Test status
Simulation time 30600460717 ps
CPU time 735.82 seconds
Started Jul 15 05:13:36 PM PDT 24
Finished Jul 15 05:25:53 PM PDT 24
Peak memory 272516 kb
Host smart-965502c6-a1f7-410d-b072-0de49f3a1b16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319734271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1319734271
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.423291285
Short name T4
Test name
Test status
Simulation time 52915189062 ps
CPU time 1767.84 seconds
Started Jul 15 05:13:36 PM PDT 24
Finished Jul 15 05:43:05 PM PDT 24
Peak memory 273912 kb
Host smart-a929d63a-6fca-43d6-b78c-d385dd6b95b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423291285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.423291285
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1175922665
Short name T648
Test name
Test status
Simulation time 19960814913 ps
CPU time 414.56 seconds
Started Jul 15 05:13:36 PM PDT 24
Finished Jul 15 05:20:31 PM PDT 24
Peak memory 249340 kb
Host smart-f466b431-75f5-489a-8383-1a7da6971496
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175922665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1175922665
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1175358771
Short name T250
Test name
Test status
Simulation time 796131871 ps
CPU time 14.54 seconds
Started Jul 15 05:13:32 PM PDT 24
Finished Jul 15 05:13:47 PM PDT 24
Peak memory 249256 kb
Host smart-c5a25124-01f4-41be-901d-b00f12e5f875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11753
58771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1175358771
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1595227911
Short name T624
Test name
Test status
Simulation time 4495211230 ps
CPU time 23.38 seconds
Started Jul 15 05:13:30 PM PDT 24
Finished Jul 15 05:13:53 PM PDT 24
Peak memory 248652 kb
Host smart-37d60225-6875-4509-9f0b-04e953cb7ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15952
27911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1595227911
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.230754889
Short name T448
Test name
Test status
Simulation time 195602382 ps
CPU time 11.46 seconds
Started Jul 15 05:13:40 PM PDT 24
Finished Jul 15 05:13:52 PM PDT 24
Peak memory 257252 kb
Host smart-f43ff3f3-3b15-48f1-8ccc-e8a2edd2d8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23075
4889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.230754889
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.4180758834
Short name T638
Test name
Test status
Simulation time 4575351672 ps
CPU time 66.98 seconds
Started Jul 15 05:13:29 PM PDT 24
Finished Jul 15 05:14:37 PM PDT 24
Peak memory 256800 kb
Host smart-7345c914-d331-4aeb-b958-14c78f220b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41807
58834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.4180758834
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.824413646
Short name T425
Test name
Test status
Simulation time 32318974544 ps
CPU time 2140.03 seconds
Started Jul 15 05:13:43 PM PDT 24
Finished Jul 15 05:49:24 PM PDT 24
Peak memory 289412 kb
Host smart-1ce6bfc9-a012-46d0-9c76-c3a2f7d3b5a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824413646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.824413646
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2483947290
Short name T524
Test name
Test status
Simulation time 21620958885 ps
CPU time 2681.7 seconds
Started Jul 15 05:13:43 PM PDT 24
Finished Jul 15 05:58:25 PM PDT 24
Peak memory 305940 kb
Host smart-5ccf265f-e809-4fb2-a389-ee5fb6c9d562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483947290 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2483947290
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.286570143
Short name T197
Test name
Test status
Simulation time 99778274 ps
CPU time 2.69 seconds
Started Jul 15 05:13:53 PM PDT 24
Finished Jul 15 05:13:56 PM PDT 24
Peak memory 249464 kb
Host smart-e3ec6041-c27b-4558-abd6-cca5869a892e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=286570143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.286570143
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1785896054
Short name T498
Test name
Test status
Simulation time 19480687379 ps
CPU time 1839.49 seconds
Started Jul 15 05:13:44 PM PDT 24
Finished Jul 15 05:44:24 PM PDT 24
Peak memory 289664 kb
Host smart-c00a81fc-1944-4b7c-823a-9870cf971084
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785896054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1785896054
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.231939793
Short name T474
Test name
Test status
Simulation time 1649809578 ps
CPU time 24.73 seconds
Started Jul 15 05:13:53 PM PDT 24
Finished Jul 15 05:14:18 PM PDT 24
Peak memory 249156 kb
Host smart-d884dea3-c26d-40fb-844c-524d45d512d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=231939793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.231939793
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1275024443
Short name T476
Test name
Test status
Simulation time 4783309590 ps
CPU time 81.69 seconds
Started Jul 15 05:13:43 PM PDT 24
Finished Jul 15 05:15:05 PM PDT 24
Peak memory 256564 kb
Host smart-3ef214fa-cc56-4544-8a41-66b7e737dfb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12750
24443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1275024443
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.656456392
Short name T215
Test name
Test status
Simulation time 181853555 ps
CPU time 15.89 seconds
Started Jul 15 05:13:47 PM PDT 24
Finished Jul 15 05:14:04 PM PDT 24
Peak memory 248680 kb
Host smart-1c58668d-d6ba-4330-addd-8d71ae3adf2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65645
6392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.656456392
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.76995845
Short name T218
Test name
Test status
Simulation time 36396654266 ps
CPU time 703.97 seconds
Started Jul 15 05:13:45 PM PDT 24
Finished Jul 15 05:25:30 PM PDT 24
Peak memory 273560 kb
Host smart-5fe8c277-c440-4577-a094-a4cb85763e16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76995845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.76995845
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2864499055
Short name T421
Test name
Test status
Simulation time 5514920153 ps
CPU time 664.5 seconds
Started Jul 15 05:13:55 PM PDT 24
Finished Jul 15 05:25:00 PM PDT 24
Peak memory 267812 kb
Host smart-d6e7a0aa-4bab-4dd4-9f9a-470447d39af1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864499055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2864499055
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1049566492
Short name T693
Test name
Test status
Simulation time 61666582099 ps
CPU time 178.15 seconds
Started Jul 15 05:13:47 PM PDT 24
Finished Jul 15 05:16:46 PM PDT 24
Peak memory 256264 kb
Host smart-352c7cef-1a04-418e-9e55-9399ce8cd24a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049566492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1049566492
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.646491198
Short name T634
Test name
Test status
Simulation time 20135313411 ps
CPU time 71.23 seconds
Started Jul 15 05:13:43 PM PDT 24
Finished Jul 15 05:14:55 PM PDT 24
Peak memory 249332 kb
Host smart-886e425f-7343-41d6-b175-4d3cab315b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64649
1198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.646491198
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1597282857
Short name T664
Test name
Test status
Simulation time 1571957782 ps
CPU time 24.38 seconds
Started Jul 15 05:13:47 PM PDT 24
Finished Jul 15 05:14:12 PM PDT 24
Peak memory 248648 kb
Host smart-e9b643ab-9323-426e-b02d-a0fea33b9c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15972
82857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1597282857
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.755891206
Short name T346
Test name
Test status
Simulation time 774877662 ps
CPU time 14.54 seconds
Started Jul 15 05:13:45 PM PDT 24
Finished Jul 15 05:14:00 PM PDT 24
Peak memory 254152 kb
Host smart-3f7857eb-658c-4db4-9666-6d160652ed4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75589
1206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.755891206
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.489555429
Short name T271
Test name
Test status
Simulation time 162324075718 ps
CPU time 2822.6 seconds
Started Jul 15 05:13:52 PM PDT 24
Finished Jul 15 06:00:56 PM PDT 24
Peak memory 287960 kb
Host smart-29af4439-6ae9-4e8f-8d28-cf541ce38198
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489555429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.489555429
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2770089206
Short name T202
Test name
Test status
Simulation time 40991029 ps
CPU time 3.8 seconds
Started Jul 15 05:13:59 PM PDT 24
Finished Jul 15 05:14:05 PM PDT 24
Peak memory 249528 kb
Host smart-fb09771f-46cd-4081-a706-dd6fb6818a11
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2770089206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2770089206
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3582205284
Short name T465
Test name
Test status
Simulation time 38153234244 ps
CPU time 2247.67 seconds
Started Jul 15 05:13:59 PM PDT 24
Finished Jul 15 05:51:29 PM PDT 24
Peak memory 289504 kb
Host smart-9016fdc0-3b10-4ab0-8391-14bc8f4c9a63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582205284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3582205284
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2917199850
Short name T370
Test name
Test status
Simulation time 12184862183 ps
CPU time 35.72 seconds
Started Jul 15 05:14:00 PM PDT 24
Finished Jul 15 05:14:37 PM PDT 24
Peak memory 249348 kb
Host smart-d94ff3a7-7749-4f38-8a5b-d30a9220966f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2917199850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2917199850
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3408908526
Short name T699
Test name
Test status
Simulation time 1368343137 ps
CPU time 66.6 seconds
Started Jul 15 05:14:01 PM PDT 24
Finished Jul 15 05:15:09 PM PDT 24
Peak memory 256920 kb
Host smart-358ef943-8e95-4607-b88a-b81368a658b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34089
08526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3408908526
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.909124838
Short name T703
Test name
Test status
Simulation time 187366359 ps
CPU time 7.9 seconds
Started Jul 15 05:13:59 PM PDT 24
Finished Jul 15 05:14:08 PM PDT 24
Peak memory 248672 kb
Host smart-4c269b05-b8b8-4517-9e89-b2a3404a68d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90912
4838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.909124838
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1569459984
Short name T332
Test name
Test status
Simulation time 105660517628 ps
CPU time 1536.65 seconds
Started Jul 15 05:14:00 PM PDT 24
Finished Jul 15 05:39:38 PM PDT 24
Peak memory 289688 kb
Host smart-bca6936b-6641-49fd-a2bf-f83566085706
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569459984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1569459984
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.755580269
Short name T701
Test name
Test status
Simulation time 25619290008 ps
CPU time 1573.71 seconds
Started Jul 15 05:13:59 PM PDT 24
Finished Jul 15 05:40:15 PM PDT 24
Peak memory 290028 kb
Host smart-563b2e5b-24f0-44e0-aa74-84a00623b6da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755580269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.755580269
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3929255599
Short name T307
Test name
Test status
Simulation time 35598147173 ps
CPU time 387.89 seconds
Started Jul 15 05:13:59 PM PDT 24
Finished Jul 15 05:20:28 PM PDT 24
Peak memory 249300 kb
Host smart-78fa43a4-2b4f-433a-9257-31477b7bbcc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929255599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3929255599
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.718203461
Short name T389
Test name
Test status
Simulation time 2600398337 ps
CPU time 47.01 seconds
Started Jul 15 05:13:58 PM PDT 24
Finished Jul 15 05:14:46 PM PDT 24
Peak memory 257092 kb
Host smart-b0e0df2c-a164-4cca-a3e8-366db80c283c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71820
3461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.718203461
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.562331618
Short name T410
Test name
Test status
Simulation time 1830953071 ps
CPU time 41.1 seconds
Started Jul 15 05:13:58 PM PDT 24
Finished Jul 15 05:14:40 PM PDT 24
Peak memory 249036 kb
Host smart-162a8eae-6359-4799-a084-e62c4579d4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56233
1618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.562331618
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.785784464
Short name T545
Test name
Test status
Simulation time 249843871 ps
CPU time 17.22 seconds
Started Jul 15 05:15:01 PM PDT 24
Finished Jul 15 05:15:18 PM PDT 24
Peak memory 254764 kb
Host smart-39f91afb-13fb-44ea-93b5-c070f0abcda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78578
4464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.785784464
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3422537155
Short name T596
Test name
Test status
Simulation time 273738869 ps
CPU time 28.52 seconds
Started Jul 15 05:13:52 PM PDT 24
Finished Jul 15 05:14:21 PM PDT 24
Peak memory 256388 kb
Host smart-80de8826-f17a-4f75-9b0b-05d52061feed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34225
37155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3422537155
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3702597956
Short name T49
Test name
Test status
Simulation time 48499115837 ps
CPU time 918.76 seconds
Started Jul 15 05:13:59 PM PDT 24
Finished Jul 15 05:29:20 PM PDT 24
Peak memory 284520 kb
Host smart-508914e5-83fd-40d7-a081-a09b6ef2c380
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702597956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3702597956
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1808142326
Short name T105
Test name
Test status
Simulation time 204963564994 ps
CPU time 4249.67 seconds
Started Jul 15 05:13:59 PM PDT 24
Finished Jul 15 06:24:50 PM PDT 24
Peak memory 339016 kb
Host smart-4c072e03-3e31-4e9e-b576-66dee9f97705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808142326 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1808142326
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2435923552
Short name T198
Test name
Test status
Simulation time 109225015 ps
CPU time 4.05 seconds
Started Jul 15 05:11:22 PM PDT 24
Finished Jul 15 05:11:30 PM PDT 24
Peak memory 249432 kb
Host smart-340163d2-856e-4d9a-8f73-22b3d1d9ed12
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2435923552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2435923552
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1014402705
Short name T576
Test name
Test status
Simulation time 111248118075 ps
CPU time 1951.25 seconds
Started Jul 15 05:11:22 PM PDT 24
Finished Jul 15 05:43:58 PM PDT 24
Peak memory 273568 kb
Host smart-0693554d-7536-46aa-b627-8a31cbb71741
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014402705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1014402705
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3927015323
Short name T614
Test name
Test status
Simulation time 3103589335 ps
CPU time 20.95 seconds
Started Jul 15 05:11:23 PM PDT 24
Finished Jul 15 05:11:48 PM PDT 24
Peak memory 249228 kb
Host smart-5e31aed2-3626-46a9-8e5e-f14ad964b58c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3927015323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3927015323
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.665105420
Short name T695
Test name
Test status
Simulation time 3213488415 ps
CPU time 197.37 seconds
Started Jul 15 05:11:14 PM PDT 24
Finished Jul 15 05:14:37 PM PDT 24
Peak memory 257080 kb
Host smart-fb6088a5-9379-47e6-a496-973ef555b173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66510
5420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.665105420
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2652453331
Short name T466
Test name
Test status
Simulation time 845797963 ps
CPU time 31.43 seconds
Started Jul 15 05:11:18 PM PDT 24
Finished Jul 15 05:11:57 PM PDT 24
Peak memory 248720 kb
Host smart-1a58b82f-ad60-4d80-a068-3d240c7264a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26524
53331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2652453331
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.644271752
Short name T372
Test name
Test status
Simulation time 158715501579 ps
CPU time 2663.5 seconds
Started Jul 15 05:11:25 PM PDT 24
Finished Jul 15 05:55:51 PM PDT 24
Peak memory 283832 kb
Host smart-0bd32ae4-2950-4ed8-82ee-344d4f6186ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644271752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.644271752
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2257983013
Short name T485
Test name
Test status
Simulation time 62175628804 ps
CPU time 357.46 seconds
Started Jul 15 05:11:22 PM PDT 24
Finished Jul 15 05:17:24 PM PDT 24
Peak memory 256068 kb
Host smart-e8d7f769-7a95-416d-a54c-164dff592d4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257983013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2257983013
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3170450740
Short name T348
Test name
Test status
Simulation time 9490504793 ps
CPU time 56.45 seconds
Started Jul 15 05:11:14 PM PDT 24
Finished Jul 15 05:12:17 PM PDT 24
Peak memory 257532 kb
Host smart-64502211-3b15-4fb8-ab3a-240cba35a83e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31704
50740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3170450740
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1636795324
Short name T577
Test name
Test status
Simulation time 1261861514 ps
CPU time 76.62 seconds
Started Jul 15 05:11:15 PM PDT 24
Finished Jul 15 05:12:38 PM PDT 24
Peak memory 256444 kb
Host smart-0552daaf-7c4a-4d32-aeee-61b2fd2aa721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16367
95324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1636795324
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.371116334
Short name T29
Test name
Test status
Simulation time 324231842 ps
CPU time 11.22 seconds
Started Jul 15 05:11:21 PM PDT 24
Finished Jul 15 05:11:37 PM PDT 24
Peak memory 271444 kb
Host smart-05d70994-250e-46c6-92ad-1cf76d4e943c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=371116334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.371116334
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2527359943
Short name T563
Test name
Test status
Simulation time 401055862 ps
CPU time 12.39 seconds
Started Jul 15 05:11:25 PM PDT 24
Finished Jul 15 05:11:40 PM PDT 24
Peak memory 249380 kb
Host smart-008a038d-3c06-4675-937b-61111e4709fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25273
59943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2527359943
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2252796260
Short name T71
Test name
Test status
Simulation time 549640855 ps
CPU time 31.93 seconds
Started Jul 15 05:11:15 PM PDT 24
Finished Jul 15 05:11:54 PM PDT 24
Peak memory 257332 kb
Host smart-c4a79bfc-1f04-4918-b0b1-9f3298d0b5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527
96260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2252796260
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.210062939
Short name T493
Test name
Test status
Simulation time 45480954523 ps
CPU time 1085.75 seconds
Started Jul 15 05:14:08 PM PDT 24
Finished Jul 15 05:32:14 PM PDT 24
Peak memory 273544 kb
Host smart-e0343275-1c27-4796-ade3-e29551f7631c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210062939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.210062939
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1186097730
Short name T509
Test name
Test status
Simulation time 3774988233 ps
CPU time 87.54 seconds
Started Jul 15 05:14:05 PM PDT 24
Finished Jul 15 05:15:34 PM PDT 24
Peak memory 257484 kb
Host smart-1fdb88bf-68c9-48e4-9ae0-fe926043f667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11860
97730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1186097730
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1033805085
Short name T72
Test name
Test status
Simulation time 3269888320 ps
CPU time 53.21 seconds
Started Jul 15 05:14:07 PM PDT 24
Finished Jul 15 05:15:01 PM PDT 24
Peak memory 249360 kb
Host smart-2ec9bed7-6c7d-4952-bc4f-9e35c847ed5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10338
05085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1033805085
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1816271434
Short name T36
Test name
Test status
Simulation time 55286908431 ps
CPU time 1688.88 seconds
Started Jul 15 05:14:06 PM PDT 24
Finished Jul 15 05:42:16 PM PDT 24
Peak memory 273704 kb
Host smart-6ff0b43f-f594-4aba-a5fe-29dcbf2b6d0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816271434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1816271434
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.142580880
Short name T561
Test name
Test status
Simulation time 70345289194 ps
CPU time 1833.3 seconds
Started Jul 15 05:14:06 PM PDT 24
Finished Jul 15 05:44:40 PM PDT 24
Peak memory 290252 kb
Host smart-d36fe095-0d1d-436a-83e5-0e77746c49fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142580880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.142580880
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3404810513
Short name T302
Test name
Test status
Simulation time 62247361168 ps
CPU time 406.82 seconds
Started Jul 15 05:14:07 PM PDT 24
Finished Jul 15 05:20:54 PM PDT 24
Peak memory 248280 kb
Host smart-d98f1c86-1fed-4280-b5ba-dd3699e955d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404810513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3404810513
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2616795883
Short name T461
Test name
Test status
Simulation time 3274071746 ps
CPU time 55.15 seconds
Started Jul 15 05:14:08 PM PDT 24
Finished Jul 15 05:15:04 PM PDT 24
Peak memory 257112 kb
Host smart-bfdd7d4d-d6c1-4195-ac6a-98917dcf9171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26167
95883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2616795883
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2059881682
Short name T628
Test name
Test status
Simulation time 1281156269 ps
CPU time 76.87 seconds
Started Jul 15 05:14:08 PM PDT 24
Finished Jul 15 05:15:26 PM PDT 24
Peak memory 256504 kb
Host smart-aa19beb1-6557-4ed9-92eb-6fc4d0247855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20598
81682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2059881682
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.4277020059
Short name T673
Test name
Test status
Simulation time 238779295 ps
CPU time 10.18 seconds
Started Jul 15 05:14:07 PM PDT 24
Finished Jul 15 05:14:18 PM PDT 24
Peak memory 248448 kb
Host smart-be9e8272-af3b-477e-ba78-427a9a23f535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
20059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4277020059
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2974559567
Short name T626
Test name
Test status
Simulation time 971498775 ps
CPU time 30.87 seconds
Started Jul 15 05:14:01 PM PDT 24
Finished Jul 15 05:14:33 PM PDT 24
Peak memory 257416 kb
Host smart-70206cd0-c626-490b-9a7e-75679e16ff7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29745
59567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2974559567
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.4245098755
Short name T685
Test name
Test status
Simulation time 170754625787 ps
CPU time 2788.35 seconds
Started Jul 15 05:14:09 PM PDT 24
Finished Jul 15 06:00:38 PM PDT 24
Peak memory 289900 kb
Host smart-823392dd-7ff8-4cad-8d43-d5931be90e5c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245098755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.4245098755
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.704944348
Short name T235
Test name
Test status
Simulation time 163121702464 ps
CPU time 2061.91 seconds
Started Jul 15 05:14:07 PM PDT 24
Finished Jul 15 05:48:30 PM PDT 24
Peak memory 305940 kb
Host smart-2c21b6fb-072b-49e1-9c75-2135f1e7614b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704944348 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.704944348
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2653857800
Short name T473
Test name
Test status
Simulation time 104102741054 ps
CPU time 1403.01 seconds
Started Jul 15 05:14:14 PM PDT 24
Finished Jul 15 05:37:38 PM PDT 24
Peak memory 273648 kb
Host smart-d1cabb18-17c8-4cab-b6ff-65e42e371394
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653857800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2653857800
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.528592477
Short name T526
Test name
Test status
Simulation time 14604537730 ps
CPU time 334.07 seconds
Started Jul 15 05:14:07 PM PDT 24
Finished Jul 15 05:19:42 PM PDT 24
Peak memory 257448 kb
Host smart-3ea87af6-4010-4a6b-b2e2-9090d3385158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52859
2477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.528592477
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.4051269005
Short name T459
Test name
Test status
Simulation time 71379736 ps
CPU time 7.76 seconds
Started Jul 15 05:14:09 PM PDT 24
Finished Jul 15 05:14:17 PM PDT 24
Peak memory 249520 kb
Host smart-1e917e21-4647-46c9-a983-30ff71478eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40512
69005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.4051269005
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2843758322
Short name T334
Test name
Test status
Simulation time 206772634028 ps
CPU time 2923.83 seconds
Started Jul 15 05:14:16 PM PDT 24
Finished Jul 15 06:03:00 PM PDT 24
Peak memory 290208 kb
Host smart-8e4b3c6e-3781-4bca-9c6d-c63325f9feef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843758322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2843758322
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2386544110
Short name T246
Test name
Test status
Simulation time 47351695356 ps
CPU time 2731.36 seconds
Started Jul 15 05:14:14 PM PDT 24
Finished Jul 15 05:59:46 PM PDT 24
Peak memory 287432 kb
Host smart-03c2fda8-de47-440d-9851-a3f0eb634bc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386544110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2386544110
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.163200815
Short name T297
Test name
Test status
Simulation time 9210608103 ps
CPU time 377.71 seconds
Started Jul 15 05:14:16 PM PDT 24
Finished Jul 15 05:20:34 PM PDT 24
Peak memory 248164 kb
Host smart-7d4c214c-8133-4602-ae8b-4d5b3b02277e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163200815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.163200815
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.4066487448
Short name T682
Test name
Test status
Simulation time 266258548 ps
CPU time 30.91 seconds
Started Jul 15 05:14:10 PM PDT 24
Finished Jul 15 05:14:42 PM PDT 24
Peak memory 256796 kb
Host smart-b18e6df2-ca69-4526-abce-72e62bb5a167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664
87448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.4066487448
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.957742081
Short name T52
Test name
Test status
Simulation time 825559788 ps
CPU time 34.94 seconds
Started Jul 15 05:14:05 PM PDT 24
Finished Jul 15 05:14:41 PM PDT 24
Peak memory 248688 kb
Host smart-776db9de-4c5c-4161-81aa-08557a6224d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95774
2081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.957742081
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2743619361
Short name T633
Test name
Test status
Simulation time 233194786 ps
CPU time 20.97 seconds
Started Jul 15 05:14:09 PM PDT 24
Finished Jul 15 05:14:30 PM PDT 24
Peak memory 256672 kb
Host smart-13d9d13b-723c-4246-b7db-35fe9eb0cb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27436
19361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2743619361
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3056024209
Short name T704
Test name
Test status
Simulation time 65314371807 ps
CPU time 2359.66 seconds
Started Jul 15 05:14:14 PM PDT 24
Finished Jul 15 05:53:35 PM PDT 24
Peak memory 289448 kb
Host smart-c7be6fd6-1b7f-4910-a61d-1cbd51925dbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056024209 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3056024209
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.127060214
Short name T169
Test name
Test status
Simulation time 2236046735 ps
CPU time 54.47 seconds
Started Jul 15 05:14:16 PM PDT 24
Finished Jul 15 05:15:11 PM PDT 24
Peak memory 256760 kb
Host smart-30033f6c-0ff1-4253-919a-5268726130fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12706
0214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.127060214
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.367352670
Short name T630
Test name
Test status
Simulation time 1950858619 ps
CPU time 29.33 seconds
Started Jul 15 05:14:14 PM PDT 24
Finished Jul 15 05:14:44 PM PDT 24
Peak memory 256600 kb
Host smart-3fda15fb-0084-409a-9e29-58c12dee9b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36735
2670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.367352670
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.4294904510
Short name T569
Test name
Test status
Simulation time 169034225064 ps
CPU time 2622.24 seconds
Started Jul 15 05:14:22 PM PDT 24
Finished Jul 15 05:58:06 PM PDT 24
Peak memory 289360 kb
Host smart-25ace230-cc8b-487b-aa66-e0e67516f3e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294904510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.4294904510
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.49795500
Short name T670
Test name
Test status
Simulation time 17924771724 ps
CPU time 380.82 seconds
Started Jul 15 05:14:22 PM PDT 24
Finished Jul 15 05:20:44 PM PDT 24
Peak memory 249388 kb
Host smart-fb621194-dc9c-42d2-bdc2-1a8e7dd8d62e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49795500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.49795500
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.29529292
Short name T353
Test name
Test status
Simulation time 6586945219 ps
CPU time 27.57 seconds
Started Jul 15 05:14:13 PM PDT 24
Finished Jul 15 05:14:41 PM PDT 24
Peak memory 256752 kb
Host smart-56e6203a-217b-46d6-8a0d-539f9a321e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29529
292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.29529292
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1866230872
Short name T168
Test name
Test status
Simulation time 84118653 ps
CPU time 4.03 seconds
Started Jul 15 05:14:15 PM PDT 24
Finished Jul 15 05:14:19 PM PDT 24
Peak memory 240588 kb
Host smart-a484b6ee-657c-4400-8257-d8a3daf2991c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18662
30872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1866230872
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.949308436
Short name T382
Test name
Test status
Simulation time 2842441596 ps
CPU time 53.93 seconds
Started Jul 15 05:14:13 PM PDT 24
Finished Jul 15 05:15:08 PM PDT 24
Peak memory 257488 kb
Host smart-0e578d73-0fa4-4461-98c7-cdcf5b938cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94930
8436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.949308436
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.18536206
Short name T594
Test name
Test status
Simulation time 265587284 ps
CPU time 17.99 seconds
Started Jul 15 05:14:17 PM PDT 24
Finished Jul 15 05:14:35 PM PDT 24
Peak memory 256420 kb
Host smart-e8b9f3bd-4055-43b6-866d-809808bcbdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18536
206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.18536206
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1247690547
Short name T627
Test name
Test status
Simulation time 1010978504 ps
CPU time 65.76 seconds
Started Jul 15 05:14:21 PM PDT 24
Finished Jul 15 05:15:28 PM PDT 24
Peak memory 257464 kb
Host smart-68c1931d-7cf3-4965-a449-50b7cd3ffce3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247690547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1247690547
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2798535922
Short name T436
Test name
Test status
Simulation time 15139387369 ps
CPU time 266.87 seconds
Started Jul 15 05:14:19 PM PDT 24
Finished Jul 15 05:18:47 PM PDT 24
Peak memory 257540 kb
Host smart-1a1122a9-e3f2-443b-9108-5090f8b26df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27985
35922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2798535922
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.293442661
Short name T409
Test name
Test status
Simulation time 746524624 ps
CPU time 15.44 seconds
Started Jul 15 05:14:21 PM PDT 24
Finished Jul 15 05:14:37 PM PDT 24
Peak memory 249172 kb
Host smart-488fa780-5360-4320-9156-ca4e4bac660d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29344
2661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.293442661
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.4260292727
Short name T514
Test name
Test status
Simulation time 64057279515 ps
CPU time 1170.01 seconds
Started Jul 15 05:14:27 PM PDT 24
Finished Jul 15 05:33:58 PM PDT 24
Peak memory 290092 kb
Host smart-8710331f-0ad0-4388-af67-293e250aa52f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260292727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.4260292727
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2344554362
Short name T462
Test name
Test status
Simulation time 31577519071 ps
CPU time 1866.02 seconds
Started Jul 15 05:14:26 PM PDT 24
Finished Jul 15 05:45:33 PM PDT 24
Peak memory 289032 kb
Host smart-03d643a2-50ef-4878-9bff-673409f41cad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344554362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2344554362
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2834332157
Short name T285
Test name
Test status
Simulation time 7169724519 ps
CPU time 294.81 seconds
Started Jul 15 05:14:27 PM PDT 24
Finished Jul 15 05:19:22 PM PDT 24
Peak memory 255684 kb
Host smart-600ddd5d-ae9c-4f05-8d97-297bbbc89632
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834332157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2834332157
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3240793068
Short name T696
Test name
Test status
Simulation time 362719103 ps
CPU time 12.45 seconds
Started Jul 15 05:14:20 PM PDT 24
Finished Jul 15 05:14:33 PM PDT 24
Peak memory 257396 kb
Host smart-0e6bbb07-6bd7-4ecf-a3d1-b45545642a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32407
93068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3240793068
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2928698814
Short name T379
Test name
Test status
Simulation time 3111296424 ps
CPU time 47.93 seconds
Started Jul 15 05:14:22 PM PDT 24
Finished Jul 15 05:15:11 PM PDT 24
Peak memory 249416 kb
Host smart-83d160b9-5f84-47cf-ab6c-38d1899aa2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29286
98814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2928698814
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3418853986
Short name T268
Test name
Test status
Simulation time 356568910 ps
CPU time 17.27 seconds
Started Jul 15 05:14:28 PM PDT 24
Finished Jul 15 05:14:46 PM PDT 24
Peak memory 248608 kb
Host smart-ecf5640a-361d-452a-a1b0-9b59fb5360db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34188
53986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3418853986
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2045305545
Short name T581
Test name
Test status
Simulation time 102403375 ps
CPU time 7.27 seconds
Started Jul 15 05:14:21 PM PDT 24
Finished Jul 15 05:14:29 PM PDT 24
Peak memory 257312 kb
Host smart-c17e0227-e161-45a9-95ce-d5b1071df890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20453
05545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2045305545
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3488695318
Short name T595
Test name
Test status
Simulation time 36499297212 ps
CPU time 983.09 seconds
Started Jul 15 05:14:34 PM PDT 24
Finished Jul 15 05:30:58 PM PDT 24
Peak memory 284668 kb
Host smart-847dc926-b6f0-4600-bef7-950ed2b5ca58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488695318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3488695318
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1487428733
Short name T694
Test name
Test status
Simulation time 526486785 ps
CPU time 10.72 seconds
Started Jul 15 05:14:34 PM PDT 24
Finished Jul 15 05:14:45 PM PDT 24
Peak memory 255428 kb
Host smart-74abffdd-1a8e-4857-b45a-cbb32e42e683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14874
28733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1487428733
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.615290603
Short name T533
Test name
Test status
Simulation time 1174257432 ps
CPU time 40.93 seconds
Started Jul 15 05:14:33 PM PDT 24
Finished Jul 15 05:15:15 PM PDT 24
Peak memory 257324 kb
Host smart-892d58ac-946a-4382-afde-f8d2d9fe0697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61529
0603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.615290603
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1594350137
Short name T326
Test name
Test status
Simulation time 16906119270 ps
CPU time 1257.15 seconds
Started Jul 15 05:14:42 PM PDT 24
Finished Jul 15 05:35:40 PM PDT 24
Peak memory 273736 kb
Host smart-45439699-83b8-4564-934c-cd952d36e8ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594350137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1594350137
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3039135633
Short name T7
Test name
Test status
Simulation time 121469282603 ps
CPU time 1691.49 seconds
Started Jul 15 05:14:41 PM PDT 24
Finished Jul 15 05:42:54 PM PDT 24
Peak memory 273916 kb
Host smart-1b08d9b7-ef51-46ba-b333-03551e83b39d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039135633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3039135633
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2710058732
Short name T310
Test name
Test status
Simulation time 53865258031 ps
CPU time 575.63 seconds
Started Jul 15 05:14:41 PM PDT 24
Finished Jul 15 05:24:18 PM PDT 24
Peak memory 256192 kb
Host smart-19742b6b-73d4-4472-9fc1-952eec1bb5e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710058732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2710058732
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1662650297
Short name T456
Test name
Test status
Simulation time 4233434635 ps
CPU time 62.76 seconds
Started Jul 15 05:14:35 PM PDT 24
Finished Jul 15 05:15:38 PM PDT 24
Peak memory 256620 kb
Host smart-76ff2bee-d020-40a2-a443-8f95e9a5678c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16626
50297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1662650297
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.822036855
Short name T175
Test name
Test status
Simulation time 832024874 ps
CPU time 56.79 seconds
Started Jul 15 05:14:33 PM PDT 24
Finished Jul 15 05:15:31 PM PDT 24
Peak memory 248900 kb
Host smart-9bdd186c-0cb0-4b0b-a730-16b53ce4409e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82203
6855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.822036855
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1532860477
Short name T249
Test name
Test status
Simulation time 1490498723 ps
CPU time 25.33 seconds
Started Jul 15 05:14:34 PM PDT 24
Finished Jul 15 05:15:00 PM PDT 24
Peak memory 249152 kb
Host smart-c690ef32-b55f-4e36-82b1-86625705edfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15328
60477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1532860477
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1214624655
Short name T471
Test name
Test status
Simulation time 110042670 ps
CPU time 8.5 seconds
Started Jul 15 05:14:33 PM PDT 24
Finished Jul 15 05:14:42 PM PDT 24
Peak memory 257256 kb
Host smart-9994a28d-fc5b-44f1-a154-7b2803d1a1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12146
24655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1214624655
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.120824854
Short name T562
Test name
Test status
Simulation time 43755907102 ps
CPU time 2052.03 seconds
Started Jul 15 05:14:43 PM PDT 24
Finished Jul 15 05:48:55 PM PDT 24
Peak memory 290000 kb
Host smart-5308d38a-707e-4547-9247-cfdc16fbb377
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120824854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.120824854
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1107697079
Short name T479
Test name
Test status
Simulation time 79013976864 ps
CPU time 2406.83 seconds
Started Jul 15 05:14:49 PM PDT 24
Finished Jul 15 05:54:57 PM PDT 24
Peak memory 290244 kb
Host smart-8ebc1ff0-1559-4d03-a708-8a8ed486cf50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107697079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1107697079
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.4176829657
Short name T390
Test name
Test status
Simulation time 661530666 ps
CPU time 73.02 seconds
Started Jul 15 05:14:50 PM PDT 24
Finished Jul 15 05:16:05 PM PDT 24
Peak memory 257216 kb
Host smart-72167423-9c2f-4e6d-9a20-d1db7711d813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41768
29657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.4176829657
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1454021524
Short name T505
Test name
Test status
Simulation time 127710195 ps
CPU time 3.83 seconds
Started Jul 15 05:14:49 PM PDT 24
Finished Jul 15 05:14:54 PM PDT 24
Peak memory 240904 kb
Host smart-25ad0255-d0aa-4b28-84f1-8499e4bef414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14540
21524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1454021524
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3342922664
Short name T321
Test name
Test status
Simulation time 37154272137 ps
CPU time 2181.71 seconds
Started Jul 15 05:14:51 PM PDT 24
Finished Jul 15 05:51:15 PM PDT 24
Peak memory 273804 kb
Host smart-11617875-3d82-4148-8c73-d53561c5f34c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342922664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3342922664
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2154190973
Short name T531
Test name
Test status
Simulation time 29665185333 ps
CPU time 1473.14 seconds
Started Jul 15 05:14:50 PM PDT 24
Finished Jul 15 05:39:25 PM PDT 24
Peak memory 289912 kb
Host smart-4652a7e3-0a76-46e7-b88c-0fe21d337357
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154190973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2154190973
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3721151594
Short name T649
Test name
Test status
Simulation time 25089461215 ps
CPU time 513.52 seconds
Started Jul 15 05:14:51 PM PDT 24
Finished Jul 15 05:23:27 PM PDT 24
Peak memory 249264 kb
Host smart-8d3a165f-b66b-4513-9ba1-0012b9402a39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721151594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3721151594
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1510445720
Short name T612
Test name
Test status
Simulation time 3605260299 ps
CPU time 56.47 seconds
Started Jul 15 05:14:51 PM PDT 24
Finished Jul 15 05:15:49 PM PDT 24
Peak memory 249328 kb
Host smart-360b7b8a-3e26-43d0-8f95-89cd061db8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15104
45720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1510445720
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2181967553
Short name T663
Test name
Test status
Simulation time 2286061548 ps
CPU time 41.96 seconds
Started Jul 15 05:14:49 PM PDT 24
Finished Jul 15 05:15:33 PM PDT 24
Peak memory 249244 kb
Host smart-ac16bd28-69bc-48f1-8733-31dfe45d9c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21819
67553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2181967553
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3736469277
Short name T243
Test name
Test status
Simulation time 137262667 ps
CPU time 13.3 seconds
Started Jul 15 05:14:51 PM PDT 24
Finished Jul 15 05:15:06 PM PDT 24
Peak memory 256636 kb
Host smart-058d6525-5369-4c94-89f8-e95568879b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37364
69277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3736469277
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3404631586
Short name T213
Test name
Test status
Simulation time 609184106 ps
CPU time 26.78 seconds
Started Jul 15 05:14:42 PM PDT 24
Finished Jul 15 05:15:10 PM PDT 24
Peak memory 249196 kb
Host smart-72495f4c-8a74-4a4d-81af-6dc8e3d6e1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34046
31586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3404631586
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1906240731
Short name T48
Test name
Test status
Simulation time 46800961930 ps
CPU time 1958.07 seconds
Started Jul 15 05:14:51 PM PDT 24
Finished Jul 15 05:47:31 PM PDT 24
Peak memory 302756 kb
Host smart-4f227c22-65d0-40b7-b7ea-2325a0e5cee0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906240731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1906240731
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.865715318
Short name T481
Test name
Test status
Simulation time 105299488363 ps
CPU time 3332.06 seconds
Started Jul 15 05:15:02 PM PDT 24
Finished Jul 15 06:10:35 PM PDT 24
Peak memory 289792 kb
Host smart-aa9ab629-7e9a-4eb6-a922-e228d6833b50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865715318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.865715318
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.4172147677
Short name T227
Test name
Test status
Simulation time 4973291081 ps
CPU time 314.42 seconds
Started Jul 15 05:14:59 PM PDT 24
Finished Jul 15 05:20:14 PM PDT 24
Peak memory 257380 kb
Host smart-15b1ce2c-4fba-49b5-a2b1-25482d0ae94e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41721
47677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.4172147677
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3152156497
Short name T5
Test name
Test status
Simulation time 359971749 ps
CPU time 28.59 seconds
Started Jul 15 05:15:03 PM PDT 24
Finished Jul 15 05:15:33 PM PDT 24
Peak memory 256368 kb
Host smart-5a74d7b6-a094-4392-9e9e-ba478e67bdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31521
56497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3152156497
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.4275110926
Short name T330
Test name
Test status
Simulation time 203393866996 ps
CPU time 3212.47 seconds
Started Jul 15 05:15:00 PM PDT 24
Finished Jul 15 06:08:33 PM PDT 24
Peak memory 281956 kb
Host smart-19c08a4c-6575-4216-8468-5c25ea28115b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275110926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4275110926
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1971947228
Short name T517
Test name
Test status
Simulation time 14188606610 ps
CPU time 1378.67 seconds
Started Jul 15 05:14:58 PM PDT 24
Finished Jul 15 05:37:57 PM PDT 24
Peak memory 290032 kb
Host smart-d084fa3b-06c8-4bd3-9578-c602d6d42c8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971947228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1971947228
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2091551076
Short name T575
Test name
Test status
Simulation time 1279043710 ps
CPU time 37.77 seconds
Started Jul 15 05:14:59 PM PDT 24
Finished Jul 15 05:15:37 PM PDT 24
Peak memory 257100 kb
Host smart-18bb6bda-2feb-4ee5-a90d-f8988f6f34ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20915
51076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2091551076
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.433695236
Short name T416
Test name
Test status
Simulation time 614977751 ps
CPU time 18.52 seconds
Started Jul 15 05:15:00 PM PDT 24
Finished Jul 15 05:15:19 PM PDT 24
Peak memory 255632 kb
Host smart-0f98f2da-1e48-440c-829a-7a71ffd7ff9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43369
5236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.433695236
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.564651636
Short name T398
Test name
Test status
Simulation time 1217052674 ps
CPU time 22.77 seconds
Started Jul 15 05:15:03 PM PDT 24
Finished Jul 15 05:15:26 PM PDT 24
Peak memory 256332 kb
Host smart-a4cd414c-2ca0-4439-8b3b-01bde0dfe0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56465
1636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.564651636
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.454399902
Short name T520
Test name
Test status
Simulation time 419993350 ps
CPU time 41.05 seconds
Started Jul 15 05:14:58 PM PDT 24
Finished Jul 15 05:15:40 PM PDT 24
Peak memory 257100 kb
Host smart-7709f637-2d0b-48ef-8f7a-f5df9952d77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45439
9902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.454399902
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3745266963
Short name T565
Test name
Test status
Simulation time 13336497623 ps
CPU time 731.35 seconds
Started Jul 15 05:15:07 PM PDT 24
Finished Jul 15 05:27:19 PM PDT 24
Peak memory 273596 kb
Host smart-d5fc10ae-65cc-4e5a-bfc6-bf4c5809aa60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745266963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3745266963
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.222265690
Short name T352
Test name
Test status
Simulation time 30732367507 ps
CPU time 213.83 seconds
Started Jul 15 05:15:08 PM PDT 24
Finished Jul 15 05:18:42 PM PDT 24
Peak memory 257384 kb
Host smart-bc1ba51e-a27c-41f8-8a77-10cfb6dca374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
5690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.222265690
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.111571432
Short name T412
Test name
Test status
Simulation time 427184007 ps
CPU time 23.13 seconds
Started Jul 15 05:15:07 PM PDT 24
Finished Jul 15 05:15:30 PM PDT 24
Peak memory 249168 kb
Host smart-6a73c164-6f0d-4ce4-9878-7bc8e0f1c8b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11157
1432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.111571432
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.262400669
Short name T319
Test name
Test status
Simulation time 19336668701 ps
CPU time 1136.23 seconds
Started Jul 15 05:15:15 PM PDT 24
Finished Jul 15 05:34:12 PM PDT 24
Peak memory 282176 kb
Host smart-837779a2-1cad-453b-ac7f-50bdf7498e1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262400669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.262400669
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2038274654
Short name T491
Test name
Test status
Simulation time 7399037840 ps
CPU time 794.43 seconds
Started Jul 15 05:15:16 PM PDT 24
Finished Jul 15 05:28:31 PM PDT 24
Peak memory 273824 kb
Host smart-7b4f9e67-5113-40ec-b42b-7d6a5850aa57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038274654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2038274654
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3560519841
Short name T298
Test name
Test status
Simulation time 6626382012 ps
CPU time 267.31 seconds
Started Jul 15 05:15:06 PM PDT 24
Finished Jul 15 05:19:34 PM PDT 24
Peak memory 249364 kb
Host smart-0d487fec-0b6f-4baa-b557-dfba7faac107
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560519841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3560519841
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.4266287935
Short name T87
Test name
Test status
Simulation time 527418609 ps
CPU time 31.86 seconds
Started Jul 15 05:15:09 PM PDT 24
Finished Jul 15 05:15:41 PM PDT 24
Peak memory 249236 kb
Host smart-c954f7c4-385f-4b47-b292-113fc203f1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42662
87935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.4266287935
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3260621901
Short name T209
Test name
Test status
Simulation time 421745482 ps
CPU time 12.32 seconds
Started Jul 15 05:15:08 PM PDT 24
Finished Jul 15 05:15:21 PM PDT 24
Peak memory 257324 kb
Host smart-13842d54-2360-4aba-bde7-8bcccb3aa926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32606
21901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3260621901
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3459693934
Short name T241
Test name
Test status
Simulation time 309017015 ps
CPU time 36.14 seconds
Started Jul 15 05:15:09 PM PDT 24
Finished Jul 15 05:15:46 PM PDT 24
Peak memory 248748 kb
Host smart-84d6ba5b-739f-4386-891f-2439aacbad3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34596
93934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3459693934
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1607458660
Short name T86
Test name
Test status
Simulation time 313259234 ps
CPU time 9.04 seconds
Started Jul 15 05:15:08 PM PDT 24
Finished Jul 15 05:15:18 PM PDT 24
Peak memory 255320 kb
Host smart-7c1aee85-3b2e-4481-bf13-7d4dfd91f0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16074
58660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1607458660
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.957284188
Short name T219
Test name
Test status
Simulation time 78731753900 ps
CPU time 1327.99 seconds
Started Jul 15 05:15:14 PM PDT 24
Finished Jul 15 05:37:23 PM PDT 24
Peak memory 285540 kb
Host smart-4a06904f-4c59-44af-953c-5838bff19c93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957284188 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.957284188
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3740876871
Short name T620
Test name
Test status
Simulation time 158961973165 ps
CPU time 1703.84 seconds
Started Jul 15 05:15:18 PM PDT 24
Finished Jul 15 05:43:42 PM PDT 24
Peak memory 290124 kb
Host smart-19a3e00c-4f5e-4fc5-be35-e7f93e43733f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740876871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3740876871
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3572385080
Short name T82
Test name
Test status
Simulation time 3041704843 ps
CPU time 178.14 seconds
Started Jul 15 05:15:17 PM PDT 24
Finished Jul 15 05:18:16 PM PDT 24
Peak memory 257072 kb
Host smart-740fc8fc-fc21-4a6f-9a17-8144d483ac77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35723
85080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3572385080
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.340040746
Short name T242
Test name
Test status
Simulation time 1483251204 ps
CPU time 40.35 seconds
Started Jul 15 05:15:15 PM PDT 24
Finished Jul 15 05:15:56 PM PDT 24
Peak memory 249116 kb
Host smart-d1983893-28dc-4bb5-82df-57cb33d63e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34004
0746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.340040746
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.882789601
Short name T674
Test name
Test status
Simulation time 59346914352 ps
CPU time 1889.68 seconds
Started Jul 15 05:15:23 PM PDT 24
Finished Jul 15 05:46:54 PM PDT 24
Peak memory 273920 kb
Host smart-fee23cb3-16cb-473c-85cd-3ab611123cf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882789601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.882789601
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1203498970
Short name T438
Test name
Test status
Simulation time 20901910837 ps
CPU time 1228.82 seconds
Started Jul 15 05:15:23 PM PDT 24
Finished Jul 15 05:35:52 PM PDT 24
Peak memory 273124 kb
Host smart-1c77a7e5-45c2-4d71-8fb6-1e8f75c87a2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203498970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1203498970
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3221998236
Short name T282
Test name
Test status
Simulation time 14794140949 ps
CPU time 325.65 seconds
Started Jul 15 05:15:24 PM PDT 24
Finished Jul 15 05:20:50 PM PDT 24
Peak memory 255864 kb
Host smart-7b0c1439-372a-4faf-a8e9-e46ed8551c1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221998236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3221998236
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.4185346629
Short name T592
Test name
Test status
Simulation time 1366177886 ps
CPU time 51.7 seconds
Started Jul 15 05:15:14 PM PDT 24
Finished Jul 15 05:16:06 PM PDT 24
Peak memory 257360 kb
Host smart-bf23b910-ab7f-4058-a6f8-4e4d7ad0f777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41853
46629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.4185346629
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2525878992
Short name T107
Test name
Test status
Simulation time 1683054021 ps
CPU time 50.7 seconds
Started Jul 15 05:15:16 PM PDT 24
Finished Jul 15 05:16:07 PM PDT 24
Peak memory 249296 kb
Host smart-6fda07a3-b4e9-412d-aed4-3ceffd5fa4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25258
78992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2525878992
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2228290393
Short name T607
Test name
Test status
Simulation time 2742343497 ps
CPU time 58.96 seconds
Started Jul 15 05:15:15 PM PDT 24
Finished Jul 15 05:16:15 PM PDT 24
Peak memory 257500 kb
Host smart-a2f4c240-eab9-4235-92d9-6353b5590f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22282
90393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2228290393
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2630952014
Short name T97
Test name
Test status
Simulation time 38466546335 ps
CPU time 2631.85 seconds
Started Jul 15 05:15:24 PM PDT 24
Finished Jul 15 05:59:16 PM PDT 24
Peak memory 289940 kb
Host smart-d39c9d6f-21b4-486c-955e-34a296183ec3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630952014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2630952014
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.628761267
Short name T189
Test name
Test status
Simulation time 297834951722 ps
CPU time 3966.46 seconds
Started Jul 15 05:15:25 PM PDT 24
Finished Jul 15 06:21:32 PM PDT 24
Peak memory 306516 kb
Host smart-11c67851-e849-48c3-bb39-bf126d58c77d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628761267 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.628761267
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3030442888
Short name T452
Test name
Test status
Simulation time 10185099986 ps
CPU time 807.8 seconds
Started Jul 15 05:15:26 PM PDT 24
Finished Jul 15 05:28:55 PM PDT 24
Peak memory 273516 kb
Host smart-08857ec8-98f3-4e0b-b1cc-66927b5601f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030442888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3030442888
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2729605463
Short name T367
Test name
Test status
Simulation time 378024207 ps
CPU time 41.29 seconds
Started Jul 15 05:15:26 PM PDT 24
Finished Jul 15 05:16:08 PM PDT 24
Peak memory 257024 kb
Host smart-aab176eb-0281-4062-ae73-f463fa49fcf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27296
05463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2729605463
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2208976834
Short name T211
Test name
Test status
Simulation time 529536249 ps
CPU time 45.35 seconds
Started Jul 15 05:15:24 PM PDT 24
Finished Jul 15 05:16:10 PM PDT 24
Peak memory 249220 kb
Host smart-11c7759d-a856-4878-8d6b-6e6c2ef4fd97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22089
76834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2208976834
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.668802486
Short name T316
Test name
Test status
Simulation time 13738204357 ps
CPU time 1227.87 seconds
Started Jul 15 05:15:24 PM PDT 24
Finished Jul 15 05:35:53 PM PDT 24
Peak memory 290252 kb
Host smart-35728f00-b3e2-48d0-b11f-1e3df44ae559
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668802486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.668802486
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.4127575637
Short name T376
Test name
Test status
Simulation time 49357159799 ps
CPU time 1211.88 seconds
Started Jul 15 05:15:24 PM PDT 24
Finished Jul 15 05:35:37 PM PDT 24
Peak memory 283284 kb
Host smart-b2631aab-d91a-4053-bc9b-c34d6ffec025
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127575637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.4127575637
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.270030732
Short name T308
Test name
Test status
Simulation time 14167205943 ps
CPU time 241.66 seconds
Started Jul 15 05:15:23 PM PDT 24
Finished Jul 15 05:19:25 PM PDT 24
Peak memory 249132 kb
Host smart-7676edd3-e313-473e-90ac-206c0b1cb38c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270030732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.270030732
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3528688892
Short name T501
Test name
Test status
Simulation time 3280247013 ps
CPU time 53.59 seconds
Started Jul 15 05:15:24 PM PDT 24
Finished Jul 15 05:16:19 PM PDT 24
Peak memory 256864 kb
Host smart-c66d4e42-17e4-4575-8770-76d268fe0129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35286
88892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3528688892
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.956283992
Short name T28
Test name
Test status
Simulation time 358844171 ps
CPU time 41.5 seconds
Started Jul 15 05:15:26 PM PDT 24
Finished Jul 15 05:16:08 PM PDT 24
Peak memory 248552 kb
Host smart-d11b70d9-a34d-4642-9415-07bebf69e21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95628
3992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.956283992
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1593168291
Short name T539
Test name
Test status
Simulation time 667606982 ps
CPU time 44.79 seconds
Started Jul 15 05:15:25 PM PDT 24
Finished Jul 15 05:16:11 PM PDT 24
Peak memory 248780 kb
Host smart-2750347a-03f3-453a-9187-f39d51b0d563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15931
68291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1593168291
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.4037384642
Short name T522
Test name
Test status
Simulation time 63221481 ps
CPU time 5.01 seconds
Started Jul 15 05:15:24 PM PDT 24
Finished Jul 15 05:15:30 PM PDT 24
Peak memory 249224 kb
Host smart-5b710fe1-62af-4f5d-a3d9-be44554be72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
84642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.4037384642
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2227880386
Short name T257
Test name
Test status
Simulation time 135712645066 ps
CPU time 663.46 seconds
Started Jul 15 05:15:31 PM PDT 24
Finished Jul 15 05:26:35 PM PDT 24
Peak memory 283800 kb
Host smart-255c6af2-90ab-486a-9bf2-23a60a09c7d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227880386 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2227880386
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2705967009
Short name T192
Test name
Test status
Simulation time 69208866 ps
CPU time 2.97 seconds
Started Jul 15 05:11:38 PM PDT 24
Finished Jul 15 05:11:42 PM PDT 24
Peak memory 249520 kb
Host smart-92f0770d-271d-42d8-ab30-47f32978c2bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2705967009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2705967009
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2118228578
Short name T590
Test name
Test status
Simulation time 12537734958 ps
CPU time 1529.02 seconds
Started Jul 15 05:11:30 PM PDT 24
Finished Jul 15 05:37:00 PM PDT 24
Peak memory 290304 kb
Host smart-f67395f1-caf2-4e55-9199-712edbc82d94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118228578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2118228578
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2041015829
Short name T401
Test name
Test status
Simulation time 3369156748 ps
CPU time 28.38 seconds
Started Jul 15 05:11:42 PM PDT 24
Finished Jul 15 05:12:11 PM PDT 24
Peak memory 249244 kb
Host smart-536bb5f0-91d3-4422-b3ba-a8fdc95136f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2041015829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2041015829
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3242972098
Short name T482
Test name
Test status
Simulation time 1790198347 ps
CPU time 120.16 seconds
Started Jul 15 05:11:30 PM PDT 24
Finished Jul 15 05:13:32 PM PDT 24
Peak memory 257196 kb
Host smart-bff08d13-5d34-4c2e-b08a-e5ef40dd953e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
72098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3242972098
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.4031085900
Short name T480
Test name
Test status
Simulation time 32288462 ps
CPU time 4.44 seconds
Started Jul 15 05:11:31 PM PDT 24
Finished Jul 15 05:11:36 PM PDT 24
Peak memory 249120 kb
Host smart-34808b7e-e032-4f25-b85f-f9ae5a19102a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40310
85900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.4031085900
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.4000608756
Short name T550
Test name
Test status
Simulation time 173031214297 ps
CPU time 1888.36 seconds
Started Jul 15 05:11:38 PM PDT 24
Finished Jul 15 05:43:07 PM PDT 24
Peak memory 284740 kb
Host smart-6edc126b-cabd-4153-b3ca-de2bbfb24d80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000608756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4000608756
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2294753079
Short name T304
Test name
Test status
Simulation time 39217007237 ps
CPU time 392.85 seconds
Started Jul 15 05:11:30 PM PDT 24
Finished Jul 15 05:18:04 PM PDT 24
Peak memory 249172 kb
Host smart-0798a012-356c-46e7-a60e-5b09d7c908aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294753079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2294753079
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2837204084
Short name T440
Test name
Test status
Simulation time 974055710 ps
CPU time 58.08 seconds
Started Jul 15 05:11:23 PM PDT 24
Finished Jul 15 05:12:25 PM PDT 24
Peak memory 256588 kb
Host smart-5d1cb7b4-929b-49ec-9bd7-28a4844af310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28372
04084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2837204084
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1464349573
Short name T418
Test name
Test status
Simulation time 3082116304 ps
CPU time 48.37 seconds
Started Jul 15 05:11:23 PM PDT 24
Finished Jul 15 05:12:15 PM PDT 24
Peak memory 248832 kb
Host smart-d51fe25c-15f1-466f-98e7-971c54b18b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14643
49573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1464349573
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3173304596
Short name T597
Test name
Test status
Simulation time 160400519 ps
CPU time 11.58 seconds
Started Jul 15 05:11:30 PM PDT 24
Finished Jul 15 05:11:42 PM PDT 24
Peak memory 248592 kb
Host smart-7668b05a-c2d7-4300-b48b-5ae362bbf6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31733
04596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3173304596
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2860603338
Short name T406
Test name
Test status
Simulation time 4565496039 ps
CPU time 51.6 seconds
Started Jul 15 05:11:25 PM PDT 24
Finished Jul 15 05:12:19 PM PDT 24
Peak memory 249688 kb
Host smart-e7dae87d-d1ee-4752-a83b-d8659844c0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28606
03338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2860603338
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1818143988
Short name T54
Test name
Test status
Simulation time 138139679993 ps
CPU time 1064.17 seconds
Started Jul 15 05:11:38 PM PDT 24
Finished Jul 15 05:29:23 PM PDT 24
Peak memory 273956 kb
Host smart-b4b2134b-9ee3-40e2-8040-522b8d8e04e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818143988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1818143988
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2252637047
Short name T55
Test name
Test status
Simulation time 12913829918 ps
CPU time 1338.63 seconds
Started Jul 15 05:15:30 PM PDT 24
Finished Jul 15 05:37:50 PM PDT 24
Peak memory 282160 kb
Host smart-399e828b-4176-419c-90e7-c42e5ee229e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252637047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2252637047
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.208441729
Short name T641
Test name
Test status
Simulation time 61010070661 ps
CPU time 232.25 seconds
Started Jul 15 05:15:33 PM PDT 24
Finished Jul 15 05:19:25 PM PDT 24
Peak memory 256728 kb
Host smart-a4eb7626-494b-4985-963c-6a31a5a19969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20844
1729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.208441729
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.266879111
Short name T535
Test name
Test status
Simulation time 543311905 ps
CPU time 45.64 seconds
Started Jul 15 05:15:32 PM PDT 24
Finished Jul 15 05:16:18 PM PDT 24
Peak memory 257224 kb
Host smart-71b2a9d1-31bd-4b23-999d-d0f25a2c5115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26687
9111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.266879111
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2493155871
Short name T44
Test name
Test status
Simulation time 49795254703 ps
CPU time 2543.18 seconds
Started Jul 15 05:15:38 PM PDT 24
Finished Jul 15 05:58:02 PM PDT 24
Peak memory 289376 kb
Host smart-72f1a9a6-7208-4f24-867c-07bf7df57da7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493155871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2493155871
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.506598742
Short name T289
Test name
Test status
Simulation time 34427835409 ps
CPU time 531.34 seconds
Started Jul 15 05:15:32 PM PDT 24
Finished Jul 15 05:24:24 PM PDT 24
Peak memory 249364 kb
Host smart-e5e06c78-4a64-4738-86d2-d3832c15fbf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506598742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.506598742
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2797889539
Short name T589
Test name
Test status
Simulation time 174872057 ps
CPU time 17.38 seconds
Started Jul 15 05:15:31 PM PDT 24
Finished Jul 15 05:15:49 PM PDT 24
Peak memory 256660 kb
Host smart-da0d0b72-c35b-4495-8bc2-bd58c413f8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27978
89539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2797889539
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1136105736
Short name T27
Test name
Test status
Simulation time 573624078 ps
CPU time 9.76 seconds
Started Jul 15 05:15:32 PM PDT 24
Finished Jul 15 05:15:43 PM PDT 24
Peak memory 248684 kb
Host smart-25222127-28b3-461c-9f60-b0f305e82577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11361
05736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1136105736
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.990431183
Short name T66
Test name
Test status
Simulation time 1053004645 ps
CPU time 14.97 seconds
Started Jul 15 05:15:32 PM PDT 24
Finished Jul 15 05:15:47 PM PDT 24
Peak memory 256500 kb
Host smart-92161a86-a723-4892-8002-fa74615c6af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99043
1183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.990431183
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.4242783151
Short name T441
Test name
Test status
Simulation time 140976190 ps
CPU time 21.3 seconds
Started Jul 15 05:15:30 PM PDT 24
Finished Jul 15 05:15:52 PM PDT 24
Peak memory 257012 kb
Host smart-b11dfee1-f57d-4d8a-99e8-4614a03ffc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42427
83151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.4242783151
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1527878260
Short name T57
Test name
Test status
Simulation time 15228163886 ps
CPU time 1691.84 seconds
Started Jul 15 05:15:38 PM PDT 24
Finished Jul 15 05:43:51 PM PDT 24
Peak memory 290228 kb
Host smart-2f41275a-0967-4294-8fa5-a3396c683bfa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527878260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1527878260
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1143383823
Short name T89
Test name
Test status
Simulation time 1030926719431 ps
CPU time 5741.38 seconds
Started Jul 15 05:15:39 PM PDT 24
Finished Jul 15 06:51:21 PM PDT 24
Peak memory 355468 kb
Host smart-a0d8a400-ccc2-44fa-8a10-0e9920c4f5b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143383823 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1143383823
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2745901756
Short name T23
Test name
Test status
Simulation time 131279772712 ps
CPU time 1986.29 seconds
Started Jul 15 05:15:46 PM PDT 24
Finished Jul 15 05:48:53 PM PDT 24
Peak memory 273972 kb
Host smart-284ecc0a-6b50-4bbf-a056-d3aa3f18efdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745901756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2745901756
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2169991584
Short name T385
Test name
Test status
Simulation time 1450843086 ps
CPU time 87.51 seconds
Started Jul 15 05:15:46 PM PDT 24
Finished Jul 15 05:17:14 PM PDT 24
Peak memory 256416 kb
Host smart-12572de1-cb98-4a6a-9241-62feb9bcf22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21699
91584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2169991584
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2613629564
Short name T180
Test name
Test status
Simulation time 765417034 ps
CPU time 27.55 seconds
Started Jul 15 05:15:38 PM PDT 24
Finished Jul 15 05:16:06 PM PDT 24
Peak memory 257508 kb
Host smart-d8a31d76-50e7-4f96-ab61-a4b086ca2bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26136
29564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2613629564
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1307560136
Short name T84
Test name
Test status
Simulation time 83840981078 ps
CPU time 2580.09 seconds
Started Jul 15 05:15:46 PM PDT 24
Finished Jul 15 05:58:47 PM PDT 24
Peak memory 290344 kb
Host smart-ceab08fb-d496-403a-a4c1-95ff32107b68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307560136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1307560136
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2807412739
Short name T510
Test name
Test status
Simulation time 1057120730 ps
CPU time 21.05 seconds
Started Jul 15 05:15:38 PM PDT 24
Finished Jul 15 05:16:00 PM PDT 24
Peak memory 249092 kb
Host smart-7dc8ed85-2b56-44cf-ac69-134ee248b3bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28074
12739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2807412739
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.182606898
Short name T93
Test name
Test status
Simulation time 808455515 ps
CPU time 47.2 seconds
Started Jul 15 05:15:38 PM PDT 24
Finished Jul 15 05:16:26 PM PDT 24
Peak memory 248640 kb
Host smart-117c7014-b5f4-47bd-b861-658712ae0edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18260
6898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.182606898
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2375763575
Short name T497
Test name
Test status
Simulation time 815586939 ps
CPU time 31.09 seconds
Started Jul 15 05:15:48 PM PDT 24
Finished Jul 15 05:16:20 PM PDT 24
Peak memory 256664 kb
Host smart-76a418d8-9438-4a58-8cfc-f49c0ea1f606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23757
63575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2375763575
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2752563368
Short name T435
Test name
Test status
Simulation time 113052758 ps
CPU time 7.88 seconds
Started Jul 15 05:15:39 PM PDT 24
Finished Jul 15 05:15:48 PM PDT 24
Peak memory 249620 kb
Host smart-e2ef0922-20bd-4d7f-aec4-fcd4f4d247da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27525
63368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2752563368
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3596997993
Short name T536
Test name
Test status
Simulation time 39660879019 ps
CPU time 1111.75 seconds
Started Jul 15 05:15:46 PM PDT 24
Finished Jul 15 05:34:19 PM PDT 24
Peak memory 290372 kb
Host smart-55a736e3-1048-49b3-a8b4-153cd59ce4ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596997993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3596997993
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.374550773
Short name T91
Test name
Test status
Simulation time 54762937932 ps
CPU time 1603.02 seconds
Started Jul 15 05:16:02 PM PDT 24
Finished Jul 15 05:42:45 PM PDT 24
Peak memory 273656 kb
Host smart-15874a78-2421-4a26-be1e-014a568d3969
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374550773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.374550773
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2487452220
Short name T679
Test name
Test status
Simulation time 1598862942 ps
CPU time 138.17 seconds
Started Jul 15 05:15:55 PM PDT 24
Finished Jul 15 05:18:14 PM PDT 24
Peak memory 257376 kb
Host smart-be4da6e8-afb6-47b3-a66f-75e89b03520f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874
52220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2487452220
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.3588203590
Short name T357
Test name
Test status
Simulation time 419874426 ps
CPU time 27.16 seconds
Started Jul 15 05:15:55 PM PDT 24
Finished Jul 15 05:16:22 PM PDT 24
Peak memory 257364 kb
Host smart-d860fa30-685e-4a37-a04f-0e77dcf1d30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35882
03590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3588203590
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3455684688
Short name T587
Test name
Test status
Simulation time 51864435925 ps
CPU time 2940.1 seconds
Started Jul 15 05:16:02 PM PDT 24
Finished Jul 15 06:05:02 PM PDT 24
Peak memory 289644 kb
Host smart-70d377bf-bb4a-405b-a7b7-2862d443f689
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455684688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3455684688
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.153243656
Short name T395
Test name
Test status
Simulation time 99036651829 ps
CPU time 3064.87 seconds
Started Jul 15 05:15:59 PM PDT 24
Finished Jul 15 06:07:05 PM PDT 24
Peak memory 290156 kb
Host smart-93abac89-11b1-4a90-8ee0-01a3ac391602
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153243656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.153243656
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.435293589
Short name T313
Test name
Test status
Simulation time 98681800200 ps
CPU time 510.58 seconds
Started Jul 15 05:16:01 PM PDT 24
Finished Jul 15 05:24:32 PM PDT 24
Peak memory 256100 kb
Host smart-f8fba854-7d8a-4df7-9eee-a40a469c9943
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435293589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.435293589
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1390020615
Short name T355
Test name
Test status
Simulation time 787753333 ps
CPU time 50.39 seconds
Started Jul 15 05:15:48 PM PDT 24
Finished Jul 15 05:16:39 PM PDT 24
Peak memory 256460 kb
Host smart-472fd52b-c674-4bf8-a30e-f77a997893df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13900
20615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1390020615
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1448534423
Short name T95
Test name
Test status
Simulation time 357677221 ps
CPU time 43.21 seconds
Started Jul 15 05:15:54 PM PDT 24
Finished Jul 15 05:16:37 PM PDT 24
Peak memory 256384 kb
Host smart-3847e404-a2ea-43bd-a2d7-3fa2c9063e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14485
34423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1448534423
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4061182024
Short name T75
Test name
Test status
Simulation time 1087313182 ps
CPU time 41.2 seconds
Started Jul 15 05:15:54 PM PDT 24
Finished Jul 15 05:16:36 PM PDT 24
Peak memory 248756 kb
Host smart-ce10c291-1268-4144-bc9b-e9953dff9782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40611
82024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4061182024
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3211461476
Short name T477
Test name
Test status
Simulation time 219378401 ps
CPU time 30.48 seconds
Started Jul 15 05:15:46 PM PDT 24
Finished Jul 15 05:16:17 PM PDT 24
Peak memory 257328 kb
Host smart-4eb9404c-69e7-4a8e-b05f-2588988ab023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32114
61476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3211461476
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1344683498
Short name T636
Test name
Test status
Simulation time 3265885822 ps
CPU time 203.84 seconds
Started Jul 15 05:15:59 PM PDT 24
Finished Jul 15 05:19:24 PM PDT 24
Peak memory 257512 kb
Host smart-fe9eb261-56d3-4d53-8d71-bd5a54dc5600
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344683498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1344683498
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3113752966
Short name T534
Test name
Test status
Simulation time 66117703048 ps
CPU time 1087.21 seconds
Started Jul 15 05:16:05 PM PDT 24
Finished Jul 15 05:34:13 PM PDT 24
Peak memory 273532 kb
Host smart-b6c496bf-20e2-4e6c-9072-9867fcede3f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113752966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3113752966
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2289554497
Short name T555
Test name
Test status
Simulation time 213491962 ps
CPU time 6.29 seconds
Started Jul 15 05:16:13 PM PDT 24
Finished Jul 15 05:16:19 PM PDT 24
Peak memory 255372 kb
Host smart-434baad0-b014-4b24-9396-1437240c2441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22895
54497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2289554497
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3478177167
Short name T478
Test name
Test status
Simulation time 623256960 ps
CPU time 14.24 seconds
Started Jul 15 05:16:07 PM PDT 24
Finished Jul 15 05:16:22 PM PDT 24
Peak memory 256256 kb
Host smart-ecaed3c5-0bae-4d1e-931c-46331b61b7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34781
77167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3478177167
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2211934957
Short name T328
Test name
Test status
Simulation time 549609072302 ps
CPU time 2520.29 seconds
Started Jul 15 05:16:07 PM PDT 24
Finished Jul 15 05:58:08 PM PDT 24
Peak memory 287168 kb
Host smart-f88d8a35-6ce3-4552-9337-ce001493a9f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211934957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2211934957
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2241810916
Short name T455
Test name
Test status
Simulation time 38653880649 ps
CPU time 2573.43 seconds
Started Jul 15 05:16:13 PM PDT 24
Finished Jul 15 05:59:08 PM PDT 24
Peak memory 289200 kb
Host smart-f3264da5-ccad-4b59-a323-2197bdcc1a5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241810916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2241810916
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1777831719
Short name T573
Test name
Test status
Simulation time 182138051 ps
CPU time 12.08 seconds
Started Jul 15 05:16:06 PM PDT 24
Finished Jul 15 05:16:19 PM PDT 24
Peak memory 249248 kb
Host smart-bc5cbcb4-10ce-4fa7-ac73-dc1afeec717c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17778
31719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1777831719
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.845663483
Short name T404
Test name
Test status
Simulation time 677610022 ps
CPU time 13.35 seconds
Started Jul 15 05:16:12 PM PDT 24
Finished Jul 15 05:16:25 PM PDT 24
Peak memory 257376 kb
Host smart-f586370a-cc93-4b2c-84d5-728684f8cdfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84566
3483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.845663483
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3527628143
Short name T256
Test name
Test status
Simulation time 773719851 ps
CPU time 59.11 seconds
Started Jul 15 05:16:06 PM PDT 24
Finished Jul 15 05:17:06 PM PDT 24
Peak memory 256460 kb
Host smart-a610aecd-0d5f-4de5-bb15-3241da2df034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35276
28143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3527628143
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1094358690
Short name T623
Test name
Test status
Simulation time 1503096617 ps
CPU time 47.25 seconds
Started Jul 15 05:16:12 PM PDT 24
Finished Jul 15 05:17:00 PM PDT 24
Peak memory 257332 kb
Host smart-25980915-36c1-44b0-a0e8-51b821df1be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
58690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1094358690
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3617784579
Short name T8
Test name
Test status
Simulation time 199761485838 ps
CPU time 3435.06 seconds
Started Jul 15 05:16:23 PM PDT 24
Finished Jul 15 06:13:39 PM PDT 24
Peak memory 289956 kb
Host smart-af89c51e-e846-4968-b959-54b841277324
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617784579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3617784579
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1642487213
Short name T686
Test name
Test status
Simulation time 564213654 ps
CPU time 45.03 seconds
Started Jul 15 05:16:13 PM PDT 24
Finished Jul 15 05:16:58 PM PDT 24
Peak memory 256732 kb
Host smart-86a79d7c-cdca-4fc7-ba32-15e41c87352d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16424
87213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1642487213
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2581601118
Short name T618
Test name
Test status
Simulation time 131281580 ps
CPU time 12.85 seconds
Started Jul 15 05:16:14 PM PDT 24
Finished Jul 15 05:16:28 PM PDT 24
Peak memory 248772 kb
Host smart-57596e33-0515-4c06-bb63-3da6d2d0c7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25816
01118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2581601118
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1679594587
Short name T519
Test name
Test status
Simulation time 28116699830 ps
CPU time 1668.88 seconds
Started Jul 15 05:16:23 PM PDT 24
Finished Jul 15 05:44:13 PM PDT 24
Peak memory 289276 kb
Host smart-8a415885-671e-4381-b887-66a8c3244795
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679594587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1679594587
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2391082828
Short name T293
Test name
Test status
Simulation time 16738127675 ps
CPU time 690.98 seconds
Started Jul 15 05:16:22 PM PDT 24
Finished Jul 15 05:27:54 PM PDT 24
Peak memory 249000 kb
Host smart-ced5515e-5de2-4f9d-8dd3-113af55fa622
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391082828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2391082828
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.72682933
Short name T371
Test name
Test status
Simulation time 390079813 ps
CPU time 5.6 seconds
Started Jul 15 05:16:13 PM PDT 24
Finished Jul 15 05:16:19 PM PDT 24
Peak memory 249092 kb
Host smart-c2f6cfc9-aaf1-4c71-9998-35cbcb01392d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72682
933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.72682933
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1161951989
Short name T351
Test name
Test status
Simulation time 371096076 ps
CPU time 23.3 seconds
Started Jul 15 05:16:13 PM PDT 24
Finished Jul 15 05:16:37 PM PDT 24
Peak memory 256776 kb
Host smart-43b7067b-6738-48c6-90a4-188bc35b3767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11619
51989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1161951989
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.625487076
Short name T423
Test name
Test status
Simulation time 518769981 ps
CPU time 32.41 seconds
Started Jul 15 05:16:23 PM PDT 24
Finished Jul 15 05:16:56 PM PDT 24
Peak memory 256480 kb
Host smart-03425390-c8de-4502-8a83-cc5738017fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62548
7076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.625487076
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3732321319
Short name T415
Test name
Test status
Simulation time 196730212 ps
CPU time 18.79 seconds
Started Jul 15 05:16:15 PM PDT 24
Finished Jul 15 05:16:34 PM PDT 24
Peak memory 249384 kb
Host smart-7b58a0dd-fa7e-450f-97ea-c7aac9cecee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37323
21319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3732321319
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2085747300
Short name T702
Test name
Test status
Simulation time 6007868702 ps
CPU time 113.46 seconds
Started Jul 15 05:16:30 PM PDT 24
Finished Jul 15 05:18:25 PM PDT 24
Peak memory 257560 kb
Host smart-8d88bf97-03d9-4c50-bdc0-31637ac9f87d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085747300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2085747300
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2596886776
Short name T69
Test name
Test status
Simulation time 26020796990 ps
CPU time 1566.99 seconds
Started Jul 15 05:16:33 PM PDT 24
Finished Jul 15 05:42:40 PM PDT 24
Peak memory 271748 kb
Host smart-8c2fb2ce-1dc9-4c57-a2a9-7f0e62840129
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596886776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2596886776
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1626201152
Short name T358
Test name
Test status
Simulation time 58235642890 ps
CPU time 244.95 seconds
Started Jul 15 05:16:28 PM PDT 24
Finished Jul 15 05:20:33 PM PDT 24
Peak memory 257488 kb
Host smart-c521472c-6633-4ca2-b517-e03de48c040e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16262
01152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1626201152
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2020778953
Short name T492
Test name
Test status
Simulation time 656575035 ps
CPU time 22.49 seconds
Started Jul 15 05:16:30 PM PDT 24
Finished Jul 15 05:16:54 PM PDT 24
Peak memory 256592 kb
Host smart-682842bf-0919-48c9-9117-2933aee41394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20207
78953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2020778953
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1306824339
Short name T278
Test name
Test status
Simulation time 39382101961 ps
CPU time 2196.43 seconds
Started Jul 15 05:16:37 PM PDT 24
Finished Jul 15 05:53:15 PM PDT 24
Peak memory 283544 kb
Host smart-9721f532-9eb7-4bc3-a961-e43a2ed61a81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306824339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1306824339
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1869969419
Short name T606
Test name
Test status
Simulation time 86646344915 ps
CPU time 2768.39 seconds
Started Jul 15 05:16:38 PM PDT 24
Finished Jul 15 06:02:47 PM PDT 24
Peak memory 289684 kb
Host smart-7309e991-4a21-48b3-b5a0-890315a7ece5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869969419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1869969419
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1656808027
Short name T586
Test name
Test status
Simulation time 1857734418 ps
CPU time 51.7 seconds
Started Jul 15 05:16:30 PM PDT 24
Finished Jul 15 05:17:23 PM PDT 24
Peak memory 249068 kb
Host smart-cb696a25-0c76-465f-9569-4548e647b570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16568
08027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1656808027
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.4194576116
Short name T96
Test name
Test status
Simulation time 2581687442 ps
CPU time 41.76 seconds
Started Jul 15 05:16:30 PM PDT 24
Finished Jul 15 05:17:13 PM PDT 24
Peak memory 248676 kb
Host smart-cfa6dd78-8d91-4181-97e6-9bc06afb5411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41945
76116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.4194576116
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2326423733
Short name T41
Test name
Test status
Simulation time 3263651608 ps
CPU time 49.79 seconds
Started Jul 15 05:16:31 PM PDT 24
Finished Jul 15 05:17:22 PM PDT 24
Peak memory 256592 kb
Host smart-7fc4ce29-635b-4359-a0ec-1d41b86b716f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23264
23733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2326423733
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2613269239
Short name T494
Test name
Test status
Simulation time 1603056332 ps
CPU time 16.44 seconds
Started Jul 15 05:16:30 PM PDT 24
Finished Jul 15 05:16:47 PM PDT 24
Peak memory 257296 kb
Host smart-d63f726d-9b8d-4f35-b10a-1ba69586c8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26132
69239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2613269239
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3505406133
Short name T264
Test name
Test status
Simulation time 76473964272 ps
CPU time 1982.58 seconds
Started Jul 15 05:16:37 PM PDT 24
Finished Jul 15 05:49:40 PM PDT 24
Peak memory 305776 kb
Host smart-36d82b4f-e7f5-49ff-9960-9d90894cab09
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505406133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3505406133
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.3780748148
Short name T443
Test name
Test status
Simulation time 44383443480 ps
CPU time 4400.08 seconds
Started Jul 15 05:16:37 PM PDT 24
Finished Jul 15 06:29:58 PM PDT 24
Peak memory 322696 kb
Host smart-6d1bfd21-bbfa-4b91-9746-b123438b5d48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780748148 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.3780748148
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3386391895
Short name T650
Test name
Test status
Simulation time 73333924162 ps
CPU time 1473.55 seconds
Started Jul 15 05:16:49 PM PDT 24
Finished Jul 15 05:41:23 PM PDT 24
Peak memory 273048 kb
Host smart-e85e34af-2b0c-40d2-8a02-c95f02e6f981
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386391895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3386391895
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2248541481
Short name T658
Test name
Test status
Simulation time 699516935 ps
CPU time 42.24 seconds
Started Jul 15 05:16:48 PM PDT 24
Finished Jul 15 05:17:31 PM PDT 24
Peak memory 256828 kb
Host smart-5d9b1b06-c760-4351-b384-2686582db8cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22485
41481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2248541481
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2637060174
Short name T646
Test name
Test status
Simulation time 616835631 ps
CPU time 27.83 seconds
Started Jul 15 05:16:44 PM PDT 24
Finished Jul 15 05:17:12 PM PDT 24
Peak memory 249208 kb
Host smart-7378ab17-1d7a-4ff8-8082-92569e219dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26370
60174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2637060174
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3463777798
Short name T567
Test name
Test status
Simulation time 139488228475 ps
CPU time 2012.69 seconds
Started Jul 15 05:16:46 PM PDT 24
Finished Jul 15 05:50:19 PM PDT 24
Peak memory 273268 kb
Host smart-5a464599-37e6-4734-b0cb-6b9d834376c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463777798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3463777798
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2499269999
Short name T100
Test name
Test status
Simulation time 65866668832 ps
CPU time 1855.7 seconds
Started Jul 15 05:16:46 PM PDT 24
Finished Jul 15 05:47:43 PM PDT 24
Peak memory 273004 kb
Host smart-fb25ae86-f9fb-4da4-971a-51a5047dceb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499269999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2499269999
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.4071936168
Short name T578
Test name
Test status
Simulation time 530508181 ps
CPU time 33.15 seconds
Started Jul 15 05:16:43 PM PDT 24
Finished Jul 15 05:17:17 PM PDT 24
Peak memory 256648 kb
Host smart-e4424c77-3539-4603-9b70-722e00f34b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40719
36168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.4071936168
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1733145923
Short name T530
Test name
Test status
Simulation time 181908293 ps
CPU time 13.97 seconds
Started Jul 15 05:16:46 PM PDT 24
Finished Jul 15 05:17:00 PM PDT 24
Peak memory 248696 kb
Host smart-3472bfc6-ec53-4d91-956e-ba3385695b44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17331
45923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1733145923
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2351352992
Short name T615
Test name
Test status
Simulation time 462944195 ps
CPU time 13.91 seconds
Started Jul 15 05:16:45 PM PDT 24
Finished Jul 15 05:16:59 PM PDT 24
Peak memory 256956 kb
Host smart-140fec22-6a42-4b46-be05-3c121474ab9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23513
52992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2351352992
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.583609775
Short name T434
Test name
Test status
Simulation time 1064236798 ps
CPU time 31.46 seconds
Started Jul 15 05:16:38 PM PDT 24
Finished Jul 15 05:17:10 PM PDT 24
Peak memory 256860 kb
Host smart-999e5810-b084-4d44-81d4-e2f2a92d6a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58360
9775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.583609775
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2840380018
Short name T94
Test name
Test status
Simulation time 3749295215 ps
CPU time 156.31 seconds
Started Jul 15 05:16:45 PM PDT 24
Finished Jul 15 05:19:22 PM PDT 24
Peak memory 257568 kb
Host smart-d62234be-b38b-4ac1-a9d6-19a5696c40d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840380018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2840380018
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2383532941
Short name T451
Test name
Test status
Simulation time 218851108018 ps
CPU time 1556.49 seconds
Started Jul 15 05:16:51 PM PDT 24
Finished Jul 15 05:42:48 PM PDT 24
Peak memory 289336 kb
Host smart-e94be508-1a93-4579-96b1-730315f9c2e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383532941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2383532941
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.206591831
Short name T697
Test name
Test status
Simulation time 10280073583 ps
CPU time 325.38 seconds
Started Jul 15 05:16:53 PM PDT 24
Finished Jul 15 05:22:19 PM PDT 24
Peak memory 257004 kb
Host smart-e9286862-b311-4e70-9c9c-1cebc8032bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20659
1831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.206591831
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3595023644
Short name T546
Test name
Test status
Simulation time 231926959 ps
CPU time 7.35 seconds
Started Jul 15 05:16:51 PM PDT 24
Finished Jul 15 05:17:00 PM PDT 24
Peak memory 249192 kb
Host smart-8fe9a496-09d3-4893-b0a2-ae03962a2774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35950
23644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3595023644
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2764978629
Short name T483
Test name
Test status
Simulation time 43644377011 ps
CPU time 2526.22 seconds
Started Jul 15 05:16:59 PM PDT 24
Finished Jul 15 05:59:08 PM PDT 24
Peak memory 289216 kb
Host smart-9d13a1d2-5921-43e1-b4d9-592d323fad58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764978629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2764978629
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2340998782
Short name T296
Test name
Test status
Simulation time 8966372627 ps
CPU time 383.7 seconds
Started Jul 15 05:16:53 PM PDT 24
Finished Jul 15 05:23:18 PM PDT 24
Peak memory 249320 kb
Host smart-7be43e63-7fec-4cd9-809f-1662c3583a38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340998782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2340998782
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3821702381
Short name T380
Test name
Test status
Simulation time 740146061 ps
CPU time 11.63 seconds
Started Jul 15 05:16:47 PM PDT 24
Finished Jul 15 05:17:00 PM PDT 24
Peak memory 249392 kb
Host smart-03487e01-ae77-4367-bd76-bc4205fda348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38217
02381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3821702381
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3118243087
Short name T560
Test name
Test status
Simulation time 1426261773 ps
CPU time 35.74 seconds
Started Jul 15 05:16:44 PM PDT 24
Finished Jul 15 05:17:20 PM PDT 24
Peak memory 257384 kb
Host smart-958d6323-4bae-4c6a-9e61-eda83cba2cdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31182
43087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3118243087
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4048108654
Short name T266
Test name
Test status
Simulation time 254660080 ps
CPU time 36.48 seconds
Started Jul 15 05:16:52 PM PDT 24
Finished Jul 15 05:17:30 PM PDT 24
Peak memory 256748 kb
Host smart-f0bc4d23-ebfe-4eb1-998c-892780a9f95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40481
08654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4048108654
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2091215915
Short name T40
Test name
Test status
Simulation time 1412728522 ps
CPU time 27.08 seconds
Started Jul 15 05:16:43 PM PDT 24
Finished Jul 15 05:17:11 PM PDT 24
Peak memory 257188 kb
Host smart-f73c6e74-e738-469e-b4e5-35e84c8b129e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20912
15915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2091215915
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1335308104
Short name T92
Test name
Test status
Simulation time 65453113395 ps
CPU time 1785.08 seconds
Started Jul 15 05:17:00 PM PDT 24
Finished Jul 15 05:46:47 PM PDT 24
Peak memory 290260 kb
Host smart-16463934-5478-4e58-a045-2caa9b95e195
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335308104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1335308104
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2024054570
Short name T413
Test name
Test status
Simulation time 55031289691 ps
CPU time 977.53 seconds
Started Jul 15 05:16:58 PM PDT 24
Finished Jul 15 05:33:17 PM PDT 24
Peak memory 273468 kb
Host smart-0e5f6711-3107-4959-9e98-5f3f93075c55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024054570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2024054570
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3827380651
Short name T173
Test name
Test status
Simulation time 20061614014 ps
CPU time 97.94 seconds
Started Jul 15 05:16:58 PM PDT 24
Finished Jul 15 05:18:38 PM PDT 24
Peak memory 256728 kb
Host smart-d7be08ae-7efc-4b30-be89-978e64cb7d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38273
80651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3827380651
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.974667065
Short name T350
Test name
Test status
Simulation time 1144830346 ps
CPU time 22.23 seconds
Started Jul 15 05:17:00 PM PDT 24
Finished Jul 15 05:17:24 PM PDT 24
Peak memory 256912 kb
Host smart-3531adbd-3a2b-446a-b991-41254a84b8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97466
7065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.974667065
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.524062820
Short name T275
Test name
Test status
Simulation time 134178139081 ps
CPU time 1543.99 seconds
Started Jul 15 05:16:59 PM PDT 24
Finished Jul 15 05:42:45 PM PDT 24
Peak memory 273452 kb
Host smart-91b669ce-a4c4-426b-be9b-0db477086b76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524062820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.524062820
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3112231154
Short name T616
Test name
Test status
Simulation time 19333356549 ps
CPU time 1262.95 seconds
Started Jul 15 05:16:59 PM PDT 24
Finished Jul 15 05:38:04 PM PDT 24
Peak memory 290128 kb
Host smart-ac8e3b72-5ceb-4504-8d6f-5626c2310e0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112231154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3112231154
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3336273911
Short name T568
Test name
Test status
Simulation time 38899564534 ps
CPU time 424.4 seconds
Started Jul 15 05:16:58 PM PDT 24
Finished Jul 15 05:24:04 PM PDT 24
Peak memory 255952 kb
Host smart-4037937c-c4f0-458d-8250-7bf4448345cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336273911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3336273911
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2614433490
Short name T706
Test name
Test status
Simulation time 1248274727 ps
CPU time 47.66 seconds
Started Jul 15 05:17:00 PM PDT 24
Finished Jul 15 05:17:49 PM PDT 24
Peak memory 249236 kb
Host smart-bc20570e-87b4-4dcc-b777-3be26386d10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26144
33490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2614433490
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2709291073
Short name T537
Test name
Test status
Simulation time 368503621 ps
CPU time 40.53 seconds
Started Jul 15 05:17:03 PM PDT 24
Finished Jul 15 05:17:44 PM PDT 24
Peak memory 256688 kb
Host smart-b92cee2d-1c5a-4ca2-89ae-2340eecfdd3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27092
91073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2709291073
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.208801780
Short name T431
Test name
Test status
Simulation time 543659293 ps
CPU time 13.63 seconds
Started Jul 15 05:17:01 PM PDT 24
Finished Jul 15 05:17:16 PM PDT 24
Peak memory 249212 kb
Host smart-54bda5bb-8d42-4ad1-b9bc-2463fabf9b90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20880
1780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.208801780
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3863622483
Short name T532
Test name
Test status
Simulation time 3779793807 ps
CPU time 21.49 seconds
Started Jul 15 05:17:00 PM PDT 24
Finished Jul 15 05:17:23 PM PDT 24
Peak memory 255912 kb
Host smart-941f9aee-ff7d-4360-b173-bac872048a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38636
22483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3863622483
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4290717117
Short name T603
Test name
Test status
Simulation time 107583462871 ps
CPU time 3281.5 seconds
Started Jul 15 05:17:07 PM PDT 24
Finished Jul 15 06:11:49 PM PDT 24
Peak memory 289980 kb
Host smart-e6994b0f-2eec-4678-8d14-957a2c3db31f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290717117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4290717117
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.508770113
Short name T680
Test name
Test status
Simulation time 187630772081 ps
CPU time 1294.55 seconds
Started Jul 15 05:17:16 PM PDT 24
Finished Jul 15 05:38:51 PM PDT 24
Peak memory 273836 kb
Host smart-b89ebcba-cafc-4235-83ed-09670a25185b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508770113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.508770113
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2655388841
Short name T364
Test name
Test status
Simulation time 7081557629 ps
CPU time 108.76 seconds
Started Jul 15 05:17:18 PM PDT 24
Finished Jul 15 05:19:07 PM PDT 24
Peak memory 257492 kb
Host smart-b4ea3509-fb7e-4c6d-8aa1-0cccd1d90012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26553
88841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2655388841
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1659772469
Short name T496
Test name
Test status
Simulation time 779347222 ps
CPU time 50.64 seconds
Started Jul 15 05:17:07 PM PDT 24
Finished Jul 15 05:17:58 PM PDT 24
Peak memory 249264 kb
Host smart-fffc2740-5b10-497d-847e-6096183c1fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16597
72469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1659772469
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1795412991
Short name T315
Test name
Test status
Simulation time 180043940505 ps
CPU time 2495.05 seconds
Started Jul 15 05:17:16 PM PDT 24
Finished Jul 15 05:58:51 PM PDT 24
Peak memory 285672 kb
Host smart-749f8cb2-f9fb-4f17-a385-4e2c2d5b17a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795412991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1795412991
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.506906459
Short name T251
Test name
Test status
Simulation time 13332941210 ps
CPU time 766.17 seconds
Started Jul 15 05:17:17 PM PDT 24
Finished Jul 15 05:30:04 PM PDT 24
Peak memory 273908 kb
Host smart-dc1f515c-de1b-4121-8112-2e808a605d94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506906459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.506906459
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.778462741
Short name T656
Test name
Test status
Simulation time 20747695723 ps
CPU time 200.09 seconds
Started Jul 15 05:17:18 PM PDT 24
Finished Jul 15 05:20:38 PM PDT 24
Peak memory 249368 kb
Host smart-b890ab16-7473-419a-bbbd-3d87a69b4c77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778462741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.778462741
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3931564712
Short name T678
Test name
Test status
Simulation time 1398767428 ps
CPU time 31.81 seconds
Started Jul 15 05:17:10 PM PDT 24
Finished Jul 15 05:17:42 PM PDT 24
Peak memory 257344 kb
Host smart-243d7c5b-577b-46cc-a9d9-6d024ec99f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39315
64712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3931564712
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.290550360
Short name T472
Test name
Test status
Simulation time 613420525 ps
CPU time 25.67 seconds
Started Jul 15 05:17:09 PM PDT 24
Finished Jul 15 05:17:35 PM PDT 24
Peak memory 248812 kb
Host smart-7d4863aa-2411-4339-90a7-0baebc31aa28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29055
0360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.290550360
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2690466506
Short name T463
Test name
Test status
Simulation time 2137040372 ps
CPU time 19.97 seconds
Started Jul 15 05:17:06 PM PDT 24
Finished Jul 15 05:17:27 PM PDT 24
Peak memory 255884 kb
Host smart-de500f50-e835-446e-96a0-6afa7ed3c83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26904
66506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2690466506
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2636072097
Short name T67
Test name
Test status
Simulation time 3388377662 ps
CPU time 359.38 seconds
Started Jul 15 05:17:16 PM PDT 24
Finished Jul 15 05:23:16 PM PDT 24
Peak memory 257416 kb
Host smart-dfa49fd3-62aa-4cbd-b8c1-6229c8285629
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636072097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2636072097
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2237096258
Short name T255
Test name
Test status
Simulation time 17084259924 ps
CPU time 584.03 seconds
Started Jul 15 05:17:18 PM PDT 24
Finished Jul 15 05:27:02 PM PDT 24
Peak memory 269608 kb
Host smart-4a25f786-af39-4153-9b75-addddbe8598d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237096258 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2237096258
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1343380307
Short name T195
Test name
Test status
Simulation time 42192064 ps
CPU time 3.89 seconds
Started Jul 15 05:11:48 PM PDT 24
Finished Jul 15 05:11:53 PM PDT 24
Peak memory 249472 kb
Host smart-b52a32b3-e507-4cca-9c31-7c847e1dc610
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1343380307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1343380307
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.72238511
Short name T35
Test name
Test status
Simulation time 32540283731 ps
CPU time 710.61 seconds
Started Jul 15 05:11:48 PM PDT 24
Finished Jul 15 05:23:40 PM PDT 24
Peak memory 267784 kb
Host smart-f6b56391-4884-46da-b9a0-d3e8a443c430
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72238511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.72238511
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.251198688
Short name T362
Test name
Test status
Simulation time 710746526 ps
CPU time 11.1 seconds
Started Jul 15 05:11:48 PM PDT 24
Finished Jul 15 05:11:59 PM PDT 24
Peak memory 249216 kb
Host smart-981d7b3e-f4a8-4a74-84b4-6e1dd52e5a2e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=251198688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.251198688
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3967449627
Short name T403
Test name
Test status
Simulation time 4444567253 ps
CPU time 147.98 seconds
Started Jul 15 05:11:48 PM PDT 24
Finished Jul 15 05:14:17 PM PDT 24
Peak memory 256952 kb
Host smart-b50052e3-a107-4767-aeb4-aa60010b549a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39674
49627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3967449627
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.226766408
Short name T657
Test name
Test status
Simulation time 265254917 ps
CPU time 8.93 seconds
Started Jul 15 05:11:38 PM PDT 24
Finished Jul 15 05:11:47 PM PDT 24
Peak memory 248700 kb
Host smart-812a8275-ee4b-4b0d-bacd-52670190af7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22676
6408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.226766408
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2192118444
Short name T345
Test name
Test status
Simulation time 8653166222 ps
CPU time 944.9 seconds
Started Jul 15 05:11:50 PM PDT 24
Finished Jul 15 05:27:35 PM PDT 24
Peak memory 273284 kb
Host smart-76af25da-df98-40db-a9d0-2581ea5b52c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192118444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2192118444
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.173090890
Short name T508
Test name
Test status
Simulation time 277675716981 ps
CPU time 3193.53 seconds
Started Jul 15 05:11:49 PM PDT 24
Finished Jul 15 06:05:04 PM PDT 24
Peak memory 289956 kb
Host smart-d9231731-9880-4e9d-af49-d145480f007a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173090890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.173090890
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.736940157
Short name T687
Test name
Test status
Simulation time 19895695802 ps
CPU time 222.75 seconds
Started Jul 15 05:11:48 PM PDT 24
Finished Jul 15 05:15:31 PM PDT 24
Peak memory 249268 kb
Host smart-d581e9db-a00f-4473-b52b-4e44ef878c36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736940157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.736940157
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3080374160
Short name T667
Test name
Test status
Simulation time 1215272936 ps
CPU time 13.76 seconds
Started Jul 15 05:11:38 PM PDT 24
Finished Jul 15 05:11:53 PM PDT 24
Peak memory 255624 kb
Host smart-d3b09932-85c4-44a6-8c1f-6e8061f5b40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30803
74160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3080374160
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.111546237
Short name T378
Test name
Test status
Simulation time 1001459742 ps
CPU time 52.65 seconds
Started Jul 15 05:11:41 PM PDT 24
Finished Jul 15 05:12:34 PM PDT 24
Peak memory 256412 kb
Host smart-8020e962-91df-452f-bcf5-5405aa20b0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11154
6237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.111546237
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2292094633
Short name T13
Test name
Test status
Simulation time 609588347 ps
CPU time 29.93 seconds
Started Jul 15 05:11:47 PM PDT 24
Finished Jul 15 05:12:18 PM PDT 24
Peak memory 271900 kb
Host smart-f07b959f-f177-4e8d-8945-c509b47f5312
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2292094633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2292094633
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.186971787
Short name T544
Test name
Test status
Simulation time 123443374 ps
CPU time 14.7 seconds
Started Jul 15 05:11:47 PM PDT 24
Finished Jul 15 05:12:03 PM PDT 24
Peak memory 256828 kb
Host smart-4fb4ca66-257b-4c16-ae12-0e2003788e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18697
1787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.186971787
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.4188553769
Short name T407
Test name
Test status
Simulation time 17344735 ps
CPU time 3.08 seconds
Started Jul 15 05:11:37 PM PDT 24
Finished Jul 15 05:11:41 PM PDT 24
Peak memory 251040 kb
Host smart-65baef53-869b-4104-8413-18bc4c9c2075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41885
53769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.4188553769
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1484476164
Short name T25
Test name
Test status
Simulation time 245756821382 ps
CPU time 2611.41 seconds
Started Jul 15 05:11:48 PM PDT 24
Finished Jul 15 05:55:20 PM PDT 24
Peak memory 283448 kb
Host smart-4b0fc2cb-afd9-448f-af8d-afeddf11c2ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484476164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1484476164
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2070647610
Short name T80
Test name
Test status
Simulation time 70163880500 ps
CPU time 2540.54 seconds
Started Jul 15 05:11:48 PM PDT 24
Finished Jul 15 05:54:09 PM PDT 24
Peak memory 290352 kb
Host smart-3f118355-5adc-4a80-8cd9-ee74ff79153d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070647610 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2070647610
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2747807357
Short name T487
Test name
Test status
Simulation time 95195031419 ps
CPU time 1476.34 seconds
Started Jul 15 05:17:22 PM PDT 24
Finished Jul 15 05:41:59 PM PDT 24
Peak memory 272996 kb
Host smart-d1c64f52-6d25-4a53-ba74-9d967a00593a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747807357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2747807357
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2717228091
Short name T604
Test name
Test status
Simulation time 7975620072 ps
CPU time 118.2 seconds
Started Jul 15 05:17:22 PM PDT 24
Finished Jul 15 05:19:21 PM PDT 24
Peak memory 256988 kb
Host smart-131d2d0a-9496-42ce-89d9-c167e458ccd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27172
28091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2717228091
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3380963908
Short name T356
Test name
Test status
Simulation time 600606070 ps
CPU time 36.68 seconds
Started Jul 15 05:17:24 PM PDT 24
Finished Jul 15 05:18:01 PM PDT 24
Peak memory 249568 kb
Host smart-60eb3aff-8b6e-4901-85c7-d5702d2a09a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33809
63908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3380963908
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3766398465
Short name T327
Test name
Test status
Simulation time 14139210472 ps
CPU time 1455.23 seconds
Started Jul 15 05:17:23 PM PDT 24
Finished Jul 15 05:41:39 PM PDT 24
Peak memory 287816 kb
Host smart-49f60e55-bc3f-4d35-9e23-8992fda0787b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766398465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3766398465
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1415259597
Short name T38
Test name
Test status
Simulation time 89632753012 ps
CPU time 2638.12 seconds
Started Jul 15 05:17:29 PM PDT 24
Finished Jul 15 06:01:28 PM PDT 24
Peak memory 289924 kb
Host smart-f68a5e32-a455-4a12-b852-5cb36fbb3b1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415259597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1415259597
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1760305011
Short name T500
Test name
Test status
Simulation time 6770839485 ps
CPU time 139.99 seconds
Started Jul 15 05:17:22 PM PDT 24
Finished Jul 15 05:19:43 PM PDT 24
Peak memory 249416 kb
Host smart-9f054617-a22f-4bea-8144-4f302b0dd328
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760305011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1760305011
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.4138955208
Short name T470
Test name
Test status
Simulation time 2958836581 ps
CPU time 38.69 seconds
Started Jul 15 05:17:27 PM PDT 24
Finished Jul 15 05:18:06 PM PDT 24
Peak memory 256920 kb
Host smart-a35b37b9-3bb1-480b-8685-7e058ed7e659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41389
55208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.4138955208
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1446822182
Short name T240
Test name
Test status
Simulation time 1696706190 ps
CPU time 52.37 seconds
Started Jul 15 05:17:23 PM PDT 24
Finished Jul 15 05:18:16 PM PDT 24
Peak memory 249188 kb
Host smart-b1e26f2f-e6f6-438b-9d80-6bbffb905a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14468
22182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1446822182
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3639304326
Short name T444
Test name
Test status
Simulation time 309533899 ps
CPU time 19.76 seconds
Started Jul 15 05:17:22 PM PDT 24
Finished Jul 15 05:17:42 PM PDT 24
Peak memory 249140 kb
Host smart-4f4447b8-c488-4198-8909-9c23f1543d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36393
04326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3639304326
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2244408394
Short name T61
Test name
Test status
Simulation time 4367757499 ps
CPU time 58.61 seconds
Started Jul 15 05:17:22 PM PDT 24
Finished Jul 15 05:18:21 PM PDT 24
Peak memory 257420 kb
Host smart-9bb574ba-d354-4f48-96d2-d4571326ed29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22444
08394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2244408394
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.119880329
Short name T258
Test name
Test status
Simulation time 1104982734 ps
CPU time 116.63 seconds
Started Jul 15 05:17:32 PM PDT 24
Finished Jul 15 05:19:29 PM PDT 24
Peak memory 257416 kb
Host smart-2fbcc6e9-4edc-403c-9799-e0d07dabd326
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119880329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.119880329
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1102343465
Short name T269
Test name
Test status
Simulation time 16647976392 ps
CPU time 2032.25 seconds
Started Jul 15 05:17:30 PM PDT 24
Finished Jul 15 05:51:22 PM PDT 24
Peak memory 305740 kb
Host smart-01cd7444-0a04-452c-95ca-16e66931689f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102343465 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1102343465
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2213850982
Short name T611
Test name
Test status
Simulation time 80444852994 ps
CPU time 1591.59 seconds
Started Jul 15 05:17:39 PM PDT 24
Finished Jul 15 05:44:11 PM PDT 24
Peak memory 289124 kb
Host smart-26a69cc8-c706-4df9-81a1-293b689f775c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213850982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2213850982
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2073527574
Short name T631
Test name
Test status
Simulation time 567584582 ps
CPU time 56.78 seconds
Started Jul 15 05:17:40 PM PDT 24
Finished Jul 15 05:18:37 PM PDT 24
Peak memory 250352 kb
Host smart-f83eb965-3417-4cca-912e-8c0cf58ed16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20735
27574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2073527574
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3566104100
Short name T384
Test name
Test status
Simulation time 415142583 ps
CPU time 35.18 seconds
Started Jul 15 05:17:41 PM PDT 24
Finished Jul 15 05:18:17 PM PDT 24
Peak memory 249156 kb
Host smart-ebc79abf-0af4-45ba-ab8f-c011318b3a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35661
04100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3566104100
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.210302877
Short name T322
Test name
Test status
Simulation time 162909236136 ps
CPU time 2688.27 seconds
Started Jul 15 05:17:38 PM PDT 24
Finished Jul 15 06:02:27 PM PDT 24
Peak memory 290048 kb
Host smart-9be6625a-eba9-4942-9ec8-06f77940f1cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210302877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.210302877
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2632008375
Short name T513
Test name
Test status
Simulation time 33896826908 ps
CPU time 1850.6 seconds
Started Jul 15 05:17:39 PM PDT 24
Finished Jul 15 05:48:30 PM PDT 24
Peak memory 272892 kb
Host smart-d14cb4d0-9d89-42e8-9a1e-fd6d0ac63085
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632008375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2632008375
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.4263137926
Short name T705
Test name
Test status
Simulation time 224490432 ps
CPU time 14.93 seconds
Started Jul 15 05:17:37 PM PDT 24
Finished Jul 15 05:17:52 PM PDT 24
Peak memory 254940 kb
Host smart-f31b18c3-3850-425d-b52c-1537e2337927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42631
37926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.4263137926
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.346539634
Short name T106
Test name
Test status
Simulation time 219770099 ps
CPU time 22.3 seconds
Started Jul 15 05:17:31 PM PDT 24
Finished Jul 15 05:17:54 PM PDT 24
Peak memory 256668 kb
Host smart-e0027ebf-5a65-4282-bffe-6921c9313c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34653
9634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.346539634
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.474889956
Short name T359
Test name
Test status
Simulation time 156249143 ps
CPU time 18.07 seconds
Started Jul 15 05:17:42 PM PDT 24
Finished Jul 15 05:18:01 PM PDT 24
Peak memory 256488 kb
Host smart-50eb08dd-926b-40ba-a708-d2072a49c1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47488
9956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.474889956
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3213706426
Short name T210
Test name
Test status
Simulation time 1318253260 ps
CPU time 39.46 seconds
Started Jul 15 05:17:32 PM PDT 24
Finished Jul 15 05:18:12 PM PDT 24
Peak memory 257276 kb
Host smart-8437f7db-9e2c-4517-a103-c8e46e74ab89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32137
06426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3213706426
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1044083279
Short name T244
Test name
Test status
Simulation time 356293614386 ps
CPU time 2605.84 seconds
Started Jul 15 05:17:41 PM PDT 24
Finished Jul 15 06:01:08 PM PDT 24
Peak memory 289540 kb
Host smart-41a69661-6035-413b-93a5-f7a2555f9e77
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044083279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1044083279
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4159068226
Short name T652
Test name
Test status
Simulation time 182123320493 ps
CPU time 2804.77 seconds
Started Jul 15 05:17:48 PM PDT 24
Finished Jul 15 06:04:33 PM PDT 24
Peak memory 290308 kb
Host smart-9536be78-934e-4126-b2db-6afdeb28f498
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159068226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4159068226
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3598505249
Short name T414
Test name
Test status
Simulation time 4894402382 ps
CPU time 91.15 seconds
Started Jul 15 05:17:47 PM PDT 24
Finished Jul 15 05:19:18 PM PDT 24
Peak memory 250420 kb
Host smart-87fb1fd5-ac04-417b-b901-7c3b9da5ea73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35985
05249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3598505249
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1033425076
Short name T506
Test name
Test status
Simulation time 290706183 ps
CPU time 7.4 seconds
Started Jul 15 05:17:47 PM PDT 24
Finished Jul 15 05:17:55 PM PDT 24
Peak memory 249288 kb
Host smart-c96009b7-2afa-4846-89aa-ebbee49b6bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10334
25076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1033425076
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1860845319
Short name T252
Test name
Test status
Simulation time 46869331771 ps
CPU time 932.03 seconds
Started Jul 15 05:17:57 PM PDT 24
Finished Jul 15 05:33:29 PM PDT 24
Peak memory 273048 kb
Host smart-c93cdbe7-34f3-4ba2-8c59-ea7078a7f46a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860845319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1860845319
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3289483734
Short name T468
Test name
Test status
Simulation time 20496663923 ps
CPU time 984.46 seconds
Started Jul 15 05:17:55 PM PDT 24
Finished Jul 15 05:34:20 PM PDT 24
Peak memory 273576 kb
Host smart-d21fd80a-2cda-4324-b15b-7d95c219d84b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289483734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3289483734
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2398777813
Short name T311
Test name
Test status
Simulation time 32252844270 ps
CPU time 311.79 seconds
Started Jul 15 05:17:55 PM PDT 24
Finished Jul 15 05:23:07 PM PDT 24
Peak memory 249388 kb
Host smart-8fe46b17-3e62-477a-aeac-c53c9334fb9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398777813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2398777813
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.835302938
Short name T558
Test name
Test status
Simulation time 902743933 ps
CPU time 39.23 seconds
Started Jul 15 05:17:37 PM PDT 24
Finished Jul 15 05:18:17 PM PDT 24
Peak memory 256640 kb
Host smart-ca425e87-8143-4478-83e6-8ef37d091edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83530
2938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.835302938
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.692528041
Short name T635
Test name
Test status
Simulation time 2994889076 ps
CPU time 31.31 seconds
Started Jul 15 05:17:39 PM PDT 24
Finished Jul 15 05:18:11 PM PDT 24
Peak memory 249308 kb
Host smart-2ab6f68f-eb63-4f5e-941e-0c03ddb61865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69252
8041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.692528041
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2007173418
Short name T377
Test name
Test status
Simulation time 677833104 ps
CPU time 50.2 seconds
Started Jul 15 05:17:49 PM PDT 24
Finished Jul 15 05:18:39 PM PDT 24
Peak memory 248728 kb
Host smart-2a09b3fd-dc31-4f0c-b824-faff1f4f6214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20071
73418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2007173418
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2029467361
Short name T543
Test name
Test status
Simulation time 1616685217 ps
CPU time 19.6 seconds
Started Jul 15 05:17:38 PM PDT 24
Finished Jul 15 05:17:59 PM PDT 24
Peak memory 257420 kb
Host smart-5edb8009-3075-4178-b970-6d0a6946ee00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20294
67361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2029467361
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1781392832
Short name T174
Test name
Test status
Simulation time 263789853095 ps
CPU time 3077.74 seconds
Started Jul 15 05:17:58 PM PDT 24
Finished Jul 15 06:09:16 PM PDT 24
Peak memory 301200 kb
Host smart-1b75a9cc-5d62-463c-8783-82b930cd21c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781392832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1781392832
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.591043825
Short name T692
Test name
Test status
Simulation time 191053553562 ps
CPU time 3244.01 seconds
Started Jul 15 05:17:56 PM PDT 24
Finished Jul 15 06:12:00 PM PDT 24
Peak memory 306308 kb
Host smart-81b7112a-b149-4426-b5e6-e8f3203568c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591043825 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.591043825
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1562107032
Short name T571
Test name
Test status
Simulation time 172943895492 ps
CPU time 2564.25 seconds
Started Jul 15 05:18:05 PM PDT 24
Finished Jul 15 06:00:50 PM PDT 24
Peak memory 287524 kb
Host smart-7d73fb5c-66b1-4846-9912-bd8217cf765c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562107032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1562107032
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3488670853
Short name T557
Test name
Test status
Simulation time 8673136835 ps
CPU time 155.77 seconds
Started Jul 15 05:18:02 PM PDT 24
Finished Jul 15 05:20:39 PM PDT 24
Peak memory 256728 kb
Host smart-9db4dcd0-9684-4505-86cb-5a02ed2a381b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34886
70853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3488670853
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.339887821
Short name T79
Test name
Test status
Simulation time 1953905814 ps
CPU time 65.95 seconds
Started Jul 15 05:18:03 PM PDT 24
Finished Jul 15 05:19:10 PM PDT 24
Peak memory 249132 kb
Host smart-bc24fa6d-37e3-45b3-8be2-81086ec63b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33988
7821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.339887821
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2660367783
Short name T331
Test name
Test status
Simulation time 38042662950 ps
CPU time 1150.65 seconds
Started Jul 15 05:18:02 PM PDT 24
Finished Jul 15 05:37:14 PM PDT 24
Peak memory 285428 kb
Host smart-be5b4cc3-6b2a-4ed0-b610-0719601f6363
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660367783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2660367783
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.4178640348
Short name T671
Test name
Test status
Simulation time 28497569951 ps
CPU time 1653.45 seconds
Started Jul 15 05:18:04 PM PDT 24
Finished Jul 15 05:45:39 PM PDT 24
Peak memory 273548 kb
Host smart-8f9c3a2d-4322-4da0-96b0-05bda52c90b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178640348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.4178640348
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3764398020
Short name T294
Test name
Test status
Simulation time 31947012446 ps
CPU time 299.66 seconds
Started Jul 15 05:18:03 PM PDT 24
Finished Jul 15 05:23:03 PM PDT 24
Peak memory 249108 kb
Host smart-716fa1e4-60b1-4b41-8e83-9a5970310794
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764398020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3764398020
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1139482771
Short name T585
Test name
Test status
Simulation time 329264924 ps
CPU time 10.69 seconds
Started Jul 15 05:17:55 PM PDT 24
Finished Jul 15 05:18:06 PM PDT 24
Peak memory 249132 kb
Host smart-0e9a3561-f720-400c-96cd-8dea39292ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11394
82771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1139482771
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3078935788
Short name T512
Test name
Test status
Simulation time 29824618 ps
CPU time 3.55 seconds
Started Jul 15 05:17:56 PM PDT 24
Finished Jul 15 05:18:00 PM PDT 24
Peak memory 241024 kb
Host smart-6062421f-fb00-464a-aaca-040b0e81e559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30789
35788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3078935788
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.669954788
Short name T232
Test name
Test status
Simulation time 3410749399 ps
CPU time 53.3 seconds
Started Jul 15 05:18:03 PM PDT 24
Finished Jul 15 05:18:57 PM PDT 24
Peak memory 256536 kb
Host smart-9b936bb4-8e58-4e8f-b9e7-e93b46eb8991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66995
4788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.669954788
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.313667965
Short name T661
Test name
Test status
Simulation time 1077092382 ps
CPU time 23.8 seconds
Started Jul 15 05:17:55 PM PDT 24
Finished Jul 15 05:18:20 PM PDT 24
Peak memory 257424 kb
Host smart-09c3b34a-dac0-4a69-988e-16bdbb3df2f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31366
7965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.313667965
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3803036512
Short name T386
Test name
Test status
Simulation time 33518861611 ps
CPU time 2243.31 seconds
Started Jul 15 05:18:11 PM PDT 24
Finished Jul 15 05:55:35 PM PDT 24
Peak memory 289872 kb
Host smart-19365864-f064-4cff-9e60-c38502377deb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803036512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3803036512
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2995506962
Short name T608
Test name
Test status
Simulation time 1301603748 ps
CPU time 36.22 seconds
Started Jul 15 05:18:12 PM PDT 24
Finished Jul 15 05:18:48 PM PDT 24
Peak memory 257348 kb
Host smart-333fdf0c-e787-4861-9624-169bb50473a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29955
06962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2995506962
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3591454582
Short name T504
Test name
Test status
Simulation time 3167518747 ps
CPU time 55.71 seconds
Started Jul 15 05:18:05 PM PDT 24
Finished Jul 15 05:19:01 PM PDT 24
Peak memory 257084 kb
Host smart-de8e4bb6-7ce7-4598-89ee-8c7c77ef6f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35914
54582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3591454582
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3958913874
Short name T318
Test name
Test status
Simulation time 35167289996 ps
CPU time 2103.2 seconds
Started Jul 15 05:18:12 PM PDT 24
Finished Jul 15 05:53:16 PM PDT 24
Peak memory 283836 kb
Host smart-513a9ce9-21d9-4247-83ba-65c8b0810ce3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958913874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3958913874
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2120146715
Short name T484
Test name
Test status
Simulation time 58198930549 ps
CPU time 1472 seconds
Started Jul 15 05:18:10 PM PDT 24
Finished Jul 15 05:42:43 PM PDT 24
Peak memory 273776 kb
Host smart-25d1a147-1f3c-437a-94ac-a19933a9a0af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120146715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2120146715
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4046139438
Short name T290
Test name
Test status
Simulation time 4661435252 ps
CPU time 106.41 seconds
Started Jul 15 05:18:14 PM PDT 24
Finished Jul 15 05:20:01 PM PDT 24
Peak memory 249228 kb
Host smart-15fe72d2-f1f1-4c1e-97a2-0c2ff249a7b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046139438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4046139438
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1223275012
Short name T65
Test name
Test status
Simulation time 3031537198 ps
CPU time 56.4 seconds
Started Jul 15 05:18:04 PM PDT 24
Finished Jul 15 05:19:01 PM PDT 24
Peak memory 257336 kb
Host smart-920d4066-ba1a-4181-a340-f374ea8d1e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12232
75012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1223275012
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.729298393
Short name T676
Test name
Test status
Simulation time 730214592 ps
CPU time 36.01 seconds
Started Jul 15 05:18:02 PM PDT 24
Finished Jul 15 05:18:39 PM PDT 24
Peak memory 248776 kb
Host smart-87c3cec7-0f00-407c-a11a-9b4b7d6075ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72929
8393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.729298393
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1809748824
Short name T17
Test name
Test status
Simulation time 1710899495 ps
CPU time 33.28 seconds
Started Jul 15 05:18:12 PM PDT 24
Finished Jul 15 05:18:46 PM PDT 24
Peak memory 248432 kb
Host smart-0d09b8f3-067d-4191-8b6c-ab07c523ca5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18097
48824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1809748824
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3112818733
Short name T383
Test name
Test status
Simulation time 18266486 ps
CPU time 2.98 seconds
Started Jul 15 05:18:04 PM PDT 24
Finished Jul 15 05:18:08 PM PDT 24
Peak memory 249140 kb
Host smart-5e65809b-5bd0-44ac-ad44-b2efdfdc7baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31128
18733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3112818733
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3200319213
Short name T660
Test name
Test status
Simulation time 1977763048 ps
CPU time 172.54 seconds
Started Jul 15 05:18:19 PM PDT 24
Finished Jul 15 05:21:12 PM PDT 24
Peak memory 257428 kb
Host smart-f8442ff1-3d32-4032-ad28-e01ce51f7cf3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200319213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3200319213
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2165881330
Short name T688
Test name
Test status
Simulation time 11147006261 ps
CPU time 706.01 seconds
Started Jul 15 05:18:36 PM PDT 24
Finished Jul 15 05:30:22 PM PDT 24
Peak memory 272888 kb
Host smart-f7af2dc0-a0f1-4858-b1eb-2b9d15f51ddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165881330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2165881330
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2745051770
Short name T629
Test name
Test status
Simulation time 29103213467 ps
CPU time 150.79 seconds
Started Jul 15 05:18:37 PM PDT 24
Finished Jul 15 05:21:09 PM PDT 24
Peak memory 257416 kb
Host smart-e1484d18-3c1a-496a-8d63-147a00a542bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27450
51770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2745051770
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2713809815
Short name T460
Test name
Test status
Simulation time 2145406935 ps
CPU time 65.73 seconds
Started Jul 15 05:18:27 PM PDT 24
Finished Jul 15 05:19:33 PM PDT 24
Peak memory 249160 kb
Host smart-ff765baa-cf81-44f9-82a5-596996a240ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27138
09815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2713809815
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3491221210
Short name T238
Test name
Test status
Simulation time 31446762663 ps
CPU time 1379.91 seconds
Started Jul 15 05:18:38 PM PDT 24
Finished Jul 15 05:41:38 PM PDT 24
Peak memory 285676 kb
Host smart-e91b2021-7db4-4005-bf5e-f3528cce7889
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491221210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3491221210
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1494897175
Short name T439
Test name
Test status
Simulation time 90126780719 ps
CPU time 2688.88 seconds
Started Jul 15 05:18:35 PM PDT 24
Finished Jul 15 06:03:25 PM PDT 24
Peak memory 282068 kb
Host smart-59fb6426-876c-4393-845d-c2c6506bc0a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494897175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1494897175
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2948620618
Short name T287
Test name
Test status
Simulation time 60247870015 ps
CPU time 578.38 seconds
Started Jul 15 05:18:35 PM PDT 24
Finished Jul 15 05:28:14 PM PDT 24
Peak memory 249376 kb
Host smart-0344a4d0-4ae2-4b52-88bd-232a2f7fa9d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948620618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2948620618
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1978808128
Short name T525
Test name
Test status
Simulation time 1367210330 ps
CPU time 42.36 seconds
Started Jul 15 05:18:27 PM PDT 24
Finished Jul 15 05:19:10 PM PDT 24
Peak memory 256608 kb
Host smart-e0564a68-a353-42d6-bc34-2066bf06c410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19788
08128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1978808128
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2227271354
Short name T502
Test name
Test status
Simulation time 496951164 ps
CPU time 13.67 seconds
Started Jul 15 05:18:28 PM PDT 24
Finished Jul 15 05:18:42 PM PDT 24
Peak memory 256508 kb
Host smart-b94b61e3-c2db-440e-9876-39cc3ccbe6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22272
71354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2227271354
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.4163793172
Short name T261
Test name
Test status
Simulation time 765334534 ps
CPU time 49.87 seconds
Started Jul 15 05:18:35 PM PDT 24
Finished Jul 15 05:19:25 PM PDT 24
Peak memory 249260 kb
Host smart-13624fe0-422d-4788-9201-ddde0e8a8394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41637
93172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.4163793172
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.593823074
Short name T579
Test name
Test status
Simulation time 353208812 ps
CPU time 15.74 seconds
Started Jul 15 05:18:17 PM PDT 24
Finished Jul 15 05:18:33 PM PDT 24
Peak memory 257328 kb
Host smart-cc8c8ae7-edc5-41c8-aa59-56d4f9bd48f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59382
3074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.593823074
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2121882816
Short name T220
Test name
Test status
Simulation time 13115789680 ps
CPU time 917.79 seconds
Started Jul 15 05:18:43 PM PDT 24
Finished Jul 15 05:34:01 PM PDT 24
Peak memory 273996 kb
Host smart-69c18da3-b14c-43e1-9bc2-a817a30cb922
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121882816 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2121882816
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1534362475
Short name T653
Test name
Test status
Simulation time 97826154892 ps
CPU time 1087.25 seconds
Started Jul 15 05:18:46 PM PDT 24
Finished Jul 15 05:36:53 PM PDT 24
Peak memory 289280 kb
Host smart-e4826839-f585-45ec-84ad-8458adb64e84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534362475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1534362475
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2003141167
Short name T397
Test name
Test status
Simulation time 6493808776 ps
CPU time 201.02 seconds
Started Jul 15 05:18:44 PM PDT 24
Finished Jul 15 05:22:06 PM PDT 24
Peak memory 251468 kb
Host smart-2004d116-63ff-4628-82c8-f89c74dbe5b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20031
41167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2003141167
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1491936783
Short name T540
Test name
Test status
Simulation time 313335932 ps
CPU time 32.68 seconds
Started Jul 15 05:18:44 PM PDT 24
Finished Jul 15 05:19:18 PM PDT 24
Peak memory 256404 kb
Host smart-e3692e22-cfd1-46f0-b4f5-1c1f850a82d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14919
36783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1491936783
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2977665352
Short name T622
Test name
Test status
Simulation time 13812947773 ps
CPU time 724.37 seconds
Started Jul 15 05:18:52 PM PDT 24
Finished Jul 15 05:30:57 PM PDT 24
Peak memory 273692 kb
Host smart-5e20d6fc-22eb-4076-ba98-94a3726de195
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977665352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2977665352
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2502606037
Short name T391
Test name
Test status
Simulation time 2951554178 ps
CPU time 43.26 seconds
Started Jul 15 05:18:46 PM PDT 24
Finished Jul 15 05:19:30 PM PDT 24
Peak memory 249316 kb
Host smart-18e98ec1-5442-467a-ad6b-e6439d500593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25026
06037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2502606037
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2102570231
Short name T208
Test name
Test status
Simulation time 4327137974 ps
CPU time 69.22 seconds
Started Jul 15 05:18:43 PM PDT 24
Finished Jul 15 05:19:53 PM PDT 24
Peak memory 249216 kb
Host smart-8a11c4b2-60da-4b35-baa5-a65ab748b04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21025
70231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2102570231
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.840143268
Short name T417
Test name
Test status
Simulation time 22623294 ps
CPU time 3.18 seconds
Started Jul 15 05:18:43 PM PDT 24
Finished Jul 15 05:18:46 PM PDT 24
Peak memory 240460 kb
Host smart-5de4bab3-3e2d-4961-9240-13a7c5633521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84014
3268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.840143268
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1668242048
Short name T446
Test name
Test status
Simulation time 923530612 ps
CPU time 15.86 seconds
Started Jul 15 05:18:45 PM PDT 24
Finished Jul 15 05:19:01 PM PDT 24
Peak memory 257260 kb
Host smart-14213e92-25ee-4fe1-b363-4c33c81235a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16682
42048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1668242048
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2864337241
Short name T20
Test name
Test status
Simulation time 153772000177 ps
CPU time 2765.88 seconds
Started Jul 15 05:18:54 PM PDT 24
Finished Jul 15 06:05:01 PM PDT 24
Peak memory 298508 kb
Host smart-132d98e3-72fe-4603-8af3-0cdadcf0c80f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864337241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2864337241
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.737064570
Short name T56
Test name
Test status
Simulation time 156227581243 ps
CPU time 2506.48 seconds
Started Jul 15 05:19:01 PM PDT 24
Finished Jul 15 06:00:49 PM PDT 24
Peak memory 289888 kb
Host smart-eb16bc68-6ea5-49e9-9334-c87658be804e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737064570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.737064570
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3454717905
Short name T464
Test name
Test status
Simulation time 2905892900 ps
CPU time 193.96 seconds
Started Jul 15 05:18:59 PM PDT 24
Finished Jul 15 05:22:14 PM PDT 24
Peak memory 257492 kb
Host smart-51cf1eaf-dd7a-4b00-8194-006d5c787164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34547
17905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3454717905
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1095601430
Short name T396
Test name
Test status
Simulation time 2204896615 ps
CPU time 35.91 seconds
Started Jul 15 05:19:04 PM PDT 24
Finished Jul 15 05:19:40 PM PDT 24
Peak memory 249236 kb
Host smart-ff91d121-5fd5-4710-8cc2-a0a1ab0bd54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10956
01430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1095601430
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.297619032
Short name T518
Test name
Test status
Simulation time 19226981164 ps
CPU time 819.56 seconds
Started Jul 15 05:18:59 PM PDT 24
Finished Jul 15 05:32:39 PM PDT 24
Peak memory 273768 kb
Host smart-5c11b5bb-10bc-4b18-b3f4-85d4ab898dd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297619032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.297619032
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3634356247
Short name T365
Test name
Test status
Simulation time 139869957250 ps
CPU time 3034.68 seconds
Started Jul 15 05:19:01 PM PDT 24
Finished Jul 15 06:09:37 PM PDT 24
Peak memory 290152 kb
Host smart-e320214d-4756-4561-936b-8aa4bdc07e92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634356247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3634356247
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2677891318
Short name T301
Test name
Test status
Simulation time 17024614790 ps
CPU time 201.65 seconds
Started Jul 15 05:19:01 PM PDT 24
Finished Jul 15 05:22:23 PM PDT 24
Peak memory 249256 kb
Host smart-6b56b9b4-58ea-4ef3-8b12-51a539e337d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677891318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2677891318
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2716462411
Short name T428
Test name
Test status
Simulation time 9503695854 ps
CPU time 43.65 seconds
Started Jul 15 05:19:00 PM PDT 24
Finished Jul 15 05:19:44 PM PDT 24
Peak memory 257284 kb
Host smart-846226f6-d044-4d0c-9373-f8ed2ce27191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27164
62411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2716462411
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3878514597
Short name T559
Test name
Test status
Simulation time 227489871 ps
CPU time 28.12 seconds
Started Jul 15 05:18:59 PM PDT 24
Finished Jul 15 05:19:27 PM PDT 24
Peak memory 248756 kb
Host smart-aa218fc2-5a33-4bbe-b18f-598f82582563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38785
14597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3878514597
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.542317907
Short name T263
Test name
Test status
Simulation time 1169134800 ps
CPU time 71.89 seconds
Started Jul 15 05:19:04 PM PDT 24
Finished Jul 15 05:20:16 PM PDT 24
Peak memory 257144 kb
Host smart-bd07f97f-1083-4993-9070-2f0579bd8c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54231
7907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.542317907
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3193627808
Short name T488
Test name
Test status
Simulation time 7845576806 ps
CPU time 61.19 seconds
Started Jul 15 05:18:52 PM PDT 24
Finished Jul 15 05:19:54 PM PDT 24
Peak memory 256804 kb
Host smart-dbd70421-c715-4cf9-a2ff-399fcc956f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31936
27808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3193627808
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3884596149
Short name T47
Test name
Test status
Simulation time 41792006002 ps
CPU time 2303.75 seconds
Started Jul 15 05:19:09 PM PDT 24
Finished Jul 15 05:57:33 PM PDT 24
Peak memory 287536 kb
Host smart-5cb61a97-ce14-4513-a239-36ac3f55baeb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884596149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3884596149
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.489442104
Short name T167
Test name
Test status
Simulation time 31398040497 ps
CPU time 3099.39 seconds
Started Jul 15 05:19:11 PM PDT 24
Finished Jul 15 06:10:52 PM PDT 24
Peak memory 332364 kb
Host smart-308201d1-7e02-4763-ad2d-9ae5f1bc01c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489442104 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.489442104
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.337717585
Short name T429
Test name
Test status
Simulation time 459315255 ps
CPU time 30.47 seconds
Started Jul 15 05:19:15 PM PDT 24
Finished Jul 15 05:19:46 PM PDT 24
Peak memory 256488 kb
Host smart-c874bf43-e148-420c-8c08-2cad22ab011b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33771
7585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.337717585
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.131656891
Short name T666
Test name
Test status
Simulation time 44797184 ps
CPU time 6.31 seconds
Started Jul 15 05:19:14 PM PDT 24
Finished Jul 15 05:19:21 PM PDT 24
Peak memory 252732 kb
Host smart-58e39b89-5375-48df-8bd2-89beb40fa834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13165
6891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.131656891
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1069103795
Short name T644
Test name
Test status
Simulation time 111411870288 ps
CPU time 1779.43 seconds
Started Jul 15 05:19:14 PM PDT 24
Finished Jul 15 05:48:54 PM PDT 24
Peak memory 273864 kb
Host smart-5fd7d8d6-5fdc-4398-8351-25fb1a079074
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069103795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1069103795
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.437948825
Short name T591
Test name
Test status
Simulation time 68921928245 ps
CPU time 2218.85 seconds
Started Jul 15 05:19:16 PM PDT 24
Finished Jul 15 05:56:16 PM PDT 24
Peak memory 273744 kb
Host smart-24e32922-56d7-40af-98b7-568346c334a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437948825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.437948825
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3467521662
Short name T284
Test name
Test status
Simulation time 23247814680 ps
CPU time 273.01 seconds
Started Jul 15 05:19:23 PM PDT 24
Finished Jul 15 05:23:56 PM PDT 24
Peak memory 256288 kb
Host smart-4272a105-f384-47d3-8c62-25e6e9862798
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467521662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3467521662
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1218035533
Short name T659
Test name
Test status
Simulation time 1133687572 ps
CPU time 34.3 seconds
Started Jul 15 05:19:15 PM PDT 24
Finished Jul 15 05:19:50 PM PDT 24
Peak memory 256552 kb
Host smart-41ce60b1-2b1e-4f79-bc7c-089222fd119e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12180
35533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1218035533
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2574107053
Short name T582
Test name
Test status
Simulation time 1081600438 ps
CPU time 68.51 seconds
Started Jul 15 05:19:17 PM PDT 24
Finished Jul 15 05:20:26 PM PDT 24
Peak memory 249108 kb
Host smart-b3a8f570-d736-42a7-bb12-3a81766ceec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25741
07053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2574107053
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1687392667
Short name T78
Test name
Test status
Simulation time 1900666170 ps
CPU time 32.68 seconds
Started Jul 15 05:19:18 PM PDT 24
Finished Jul 15 05:19:51 PM PDT 24
Peak memory 249376 kb
Host smart-8206969c-cb38-4ace-87a8-0b13146b2043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16873
92667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1687392667
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1075257470
Short name T549
Test name
Test status
Simulation time 1017895030 ps
CPU time 19.47 seconds
Started Jul 15 05:19:08 PM PDT 24
Finished Jul 15 05:19:28 PM PDT 24
Peak memory 256764 kb
Host smart-70e49c1c-d295-4b72-805a-cb3179d14ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10752
57470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1075257470
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.211250591
Short name T552
Test name
Test status
Simulation time 666934899671 ps
CPU time 4776.75 seconds
Started Jul 15 05:19:22 PM PDT 24
Finished Jul 15 06:38:59 PM PDT 24
Peak memory 337728 kb
Host smart-17b0be8d-40fa-4332-9830-5d42ced954df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211250591 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.211250591
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1568477396
Short name T172
Test name
Test status
Simulation time 34511945532 ps
CPU time 2335.9 seconds
Started Jul 15 05:19:32 PM PDT 24
Finished Jul 15 05:58:29 PM PDT 24
Peak memory 282064 kb
Host smart-8981c429-4f19-44b0-be23-10db4b8d7056
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568477396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1568477396
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.300086969
Short name T662
Test name
Test status
Simulation time 28207515504 ps
CPU time 144.9 seconds
Started Jul 15 05:19:32 PM PDT 24
Finished Jul 15 05:21:57 PM PDT 24
Peak memory 257324 kb
Host smart-3e3e2e87-5dee-40d6-a4c3-5abf88b1ee74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30008
6969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.300086969
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3291002662
Short name T447
Test name
Test status
Simulation time 246250407 ps
CPU time 18.57 seconds
Started Jul 15 05:19:21 PM PDT 24
Finished Jul 15 05:19:40 PM PDT 24
Peak memory 249168 kb
Host smart-4c089dec-1303-4853-983b-891e85e1f666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32910
02662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3291002662
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.8135001
Short name T572
Test name
Test status
Simulation time 366929125893 ps
CPU time 2924.98 seconds
Started Jul 15 05:19:41 PM PDT 24
Finished Jul 15 06:08:26 PM PDT 24
Peak memory 287652 kb
Host smart-58ac0c63-2389-41e8-9566-537f92f10877
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8135001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.8135001
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4166213664
Short name T363
Test name
Test status
Simulation time 46362964507 ps
CPU time 2749.43 seconds
Started Jul 15 05:19:40 PM PDT 24
Finished Jul 15 06:05:31 PM PDT 24
Peak memory 289456 kb
Host smart-4811b9d5-e6fa-4998-8a8d-55f18a8f12fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166213664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4166213664
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2273508323
Short name T10
Test name
Test status
Simulation time 5755676522 ps
CPU time 226.51 seconds
Started Jul 15 05:19:31 PM PDT 24
Finished Jul 15 05:23:18 PM PDT 24
Peak memory 249104 kb
Host smart-97050ae9-7d9d-46e1-af18-a342737f33d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273508323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2273508323
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3015829241
Short name T393
Test name
Test status
Simulation time 228920858 ps
CPU time 29.8 seconds
Started Jul 15 05:19:23 PM PDT 24
Finished Jul 15 05:19:53 PM PDT 24
Peak memory 256560 kb
Host smart-1d931485-65eb-468f-81d4-5084c7a5a7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30158
29241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3015829241
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2114802002
Short name T229
Test name
Test status
Simulation time 580067052 ps
CPU time 16.72 seconds
Started Jul 15 05:19:30 PM PDT 24
Finished Jul 15 05:19:47 PM PDT 24
Peak memory 256572 kb
Host smart-8f31f7b5-30b2-4466-b91f-31214f4a5cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21148
02002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2114802002
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1665749633
Short name T43
Test name
Test status
Simulation time 2980887409 ps
CPU time 46.5 seconds
Started Jul 15 05:19:23 PM PDT 24
Finished Jul 15 05:20:10 PM PDT 24
Peak memory 257472 kb
Host smart-e18129a6-8375-43d6-b6b3-5463caefee35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16657
49633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1665749633
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3082003676
Short name T205
Test name
Test status
Simulation time 16603348 ps
CPU time 2.88 seconds
Started Jul 15 05:11:58 PM PDT 24
Finished Jul 15 05:12:02 PM PDT 24
Peak memory 249480 kb
Host smart-4929006f-d48a-489b-a023-9fb4b9afc0f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3082003676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3082003676
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1750811308
Short name T515
Test name
Test status
Simulation time 24969662025 ps
CPU time 1677.99 seconds
Started Jul 15 05:11:58 PM PDT 24
Finished Jul 15 05:39:57 PM PDT 24
Peak memory 271400 kb
Host smart-6b172100-1d92-4954-a55c-37415dd8135c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750811308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1750811308
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1421629255
Short name T408
Test name
Test status
Simulation time 2991601432 ps
CPU time 36.26 seconds
Started Jul 15 05:11:57 PM PDT 24
Finished Jul 15 05:12:35 PM PDT 24
Peak memory 249360 kb
Host smart-e4509da3-f8ec-4ec0-b434-960939b6aa37
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1421629255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1421629255
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2282572580
Short name T85
Test name
Test status
Simulation time 1386159097 ps
CPU time 91.73 seconds
Started Jul 15 05:11:58 PM PDT 24
Finished Jul 15 05:13:31 PM PDT 24
Peak memory 249612 kb
Host smart-7bea1fd0-2827-4a00-af90-8511b4dacf09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22825
72580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2282572580
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1543857334
Short name T33
Test name
Test status
Simulation time 394022169 ps
CPU time 14.41 seconds
Started Jul 15 05:12:00 PM PDT 24
Finished Jul 15 05:12:15 PM PDT 24
Peak memory 253396 kb
Host smart-0f4ab308-5ca2-46ff-bcdc-4fca68ac442b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15438
57334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1543857334
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.939957935
Short name T325
Test name
Test status
Simulation time 57384411526 ps
CPU time 1652.52 seconds
Started Jul 15 05:11:59 PM PDT 24
Finished Jul 15 05:39:33 PM PDT 24
Peak memory 273884 kb
Host smart-caa877b2-321e-4f84-8b3d-401bc8606400
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939957935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.939957935
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2963336041
Short name T675
Test name
Test status
Simulation time 107041874804 ps
CPU time 2712.97 seconds
Started Jul 15 05:11:57 PM PDT 24
Finished Jul 15 05:57:12 PM PDT 24
Peak memory 289984 kb
Host smart-b49765bc-416a-419d-8b15-72e32902b526
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963336041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2963336041
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3583341871
Short name T178
Test name
Test status
Simulation time 12808555856 ps
CPU time 535.09 seconds
Started Jul 15 05:11:57 PM PDT 24
Finished Jul 15 05:20:54 PM PDT 24
Peak memory 255892 kb
Host smart-5eb352db-173e-49f0-925d-256ad8ddb973
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583341871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3583341871
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1995473342
Short name T642
Test name
Test status
Simulation time 482472191 ps
CPU time 17.5 seconds
Started Jul 15 05:11:58 PM PDT 24
Finished Jul 15 05:12:16 PM PDT 24
Peak memory 249176 kb
Host smart-06de9328-8ea5-43d6-8bef-ee3293fa488d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19954
73342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1995473342
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1331909174
Short name T503
Test name
Test status
Simulation time 4114190572 ps
CPU time 30.1 seconds
Started Jul 15 05:11:57 PM PDT 24
Finished Jul 15 05:12:28 PM PDT 24
Peak memory 257152 kb
Host smart-702f9ee4-34cb-45ef-9b7e-d06a5e907f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13319
09174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1331909174
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2262395249
Short name T457
Test name
Test status
Simulation time 1722844629 ps
CPU time 31.51 seconds
Started Jul 15 05:11:59 PM PDT 24
Finished Jul 15 05:12:32 PM PDT 24
Peak memory 256532 kb
Host smart-64cbdfcb-8fd0-48b6-9c74-dd11fb2240fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22623
95249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2262395249
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2637156364
Short name T427
Test name
Test status
Simulation time 1506343405 ps
CPU time 31.83 seconds
Started Jul 15 05:11:49 PM PDT 24
Finished Jul 15 05:12:22 PM PDT 24
Peak memory 257268 kb
Host smart-ab1cdb14-3de4-447e-914d-47bc501abb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26371
56364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2637156364
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1857500586
Short name T273
Test name
Test status
Simulation time 70010536479 ps
CPU time 1957.43 seconds
Started Jul 15 05:11:59 PM PDT 24
Finished Jul 15 05:44:37 PM PDT 24
Peak memory 287748 kb
Host smart-e44d7f49-bdca-4d63-a12f-d5c1a36ed34e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857500586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1857500586
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3215281808
Short name T259
Test name
Test status
Simulation time 27003654819 ps
CPU time 3038.53 seconds
Started Jul 15 05:11:58 PM PDT 24
Finished Jul 15 06:02:38 PM PDT 24
Peak memory 320144 kb
Host smart-115648fe-09e8-4c8c-87f7-2f3e153e29b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215281808 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3215281808
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2381484794
Short name T207
Test name
Test status
Simulation time 17058575 ps
CPU time 2.75 seconds
Started Jul 15 05:12:07 PM PDT 24
Finished Jul 15 05:12:11 PM PDT 24
Peak memory 249384 kb
Host smart-ec9412de-b273-434c-947a-150826e9a67f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2381484794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2381484794
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2354839705
Short name T645
Test name
Test status
Simulation time 54657351899 ps
CPU time 1652.18 seconds
Started Jul 15 05:12:08 PM PDT 24
Finished Jul 15 05:39:42 PM PDT 24
Peak memory 273828 kb
Host smart-2f72ea07-a998-4129-93b3-8ab72f739772
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354839705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2354839705
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2908761662
Short name T677
Test name
Test status
Simulation time 564506625 ps
CPU time 10.25 seconds
Started Jul 15 05:12:08 PM PDT 24
Finished Jul 15 05:12:20 PM PDT 24
Peak memory 249264 kb
Host smart-beb8ca42-651c-4b68-aa23-ba8b6139c919
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2908761662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2908761662
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1866738713
Short name T583
Test name
Test status
Simulation time 5013078147 ps
CPU time 295.19 seconds
Started Jul 15 05:11:57 PM PDT 24
Finished Jul 15 05:16:54 PM PDT 24
Peak memory 256732 kb
Host smart-eb4dabb0-f1de-45c7-af68-f7510ee07a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18667
38713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1866738713
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.496569572
Short name T554
Test name
Test status
Simulation time 181183067 ps
CPU time 16.18 seconds
Started Jul 15 05:11:57 PM PDT 24
Finished Jul 15 05:12:14 PM PDT 24
Peak memory 257256 kb
Host smart-fb7ef585-ac98-4e8f-ad6f-9cbfad9b8cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49656
9572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.496569572
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2341802708
Short name T556
Test name
Test status
Simulation time 17734677731 ps
CPU time 805.85 seconds
Started Jul 15 05:12:07 PM PDT 24
Finished Jul 15 05:25:34 PM PDT 24
Peak memory 273932 kb
Host smart-92abd582-b5df-4932-b59c-291a3c576c93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341802708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2341802708
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.4108873358
Short name T347
Test name
Test status
Simulation time 135795272018 ps
CPU time 1189.72 seconds
Started Jul 15 05:12:07 PM PDT 24
Finished Jul 15 05:31:58 PM PDT 24
Peak memory 283816 kb
Host smart-f893fb5a-615d-4245-9ee7-45d95cce3921
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108873358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.4108873358
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1388297645
Short name T300
Test name
Test status
Simulation time 12379935503 ps
CPU time 256.87 seconds
Started Jul 15 05:12:09 PM PDT 24
Finished Jul 15 05:16:27 PM PDT 24
Peak memory 249328 kb
Host smart-93aaef95-33f5-44dd-b044-278838f970ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388297645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1388297645
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.793324609
Short name T528
Test name
Test status
Simulation time 2688087990 ps
CPU time 21.52 seconds
Started Jul 15 05:11:59 PM PDT 24
Finished Jul 15 05:12:22 PM PDT 24
Peak memory 256132 kb
Host smart-2e64e8bf-48a4-41c8-9739-72c825ec9ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79332
4609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.793324609
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.734047018
Short name T419
Test name
Test status
Simulation time 256040360 ps
CPU time 20.27 seconds
Started Jul 15 05:11:58 PM PDT 24
Finished Jul 15 05:12:20 PM PDT 24
Peak memory 249152 kb
Host smart-ec5140d7-8bad-43f3-95c5-cb77d05a4798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73404
7018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.734047018
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.3918078756
Short name T281
Test name
Test status
Simulation time 908821258 ps
CPU time 30.94 seconds
Started Jul 15 05:12:08 PM PDT 24
Finished Jul 15 05:12:41 PM PDT 24
Peak memory 249140 kb
Host smart-90266b8c-5b7f-4d9c-a486-22c7944bfa15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39180
78756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.3918078756
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3731683536
Short name T170
Test name
Test status
Simulation time 508841400 ps
CPU time 40.26 seconds
Started Jul 15 05:11:59 PM PDT 24
Finished Jul 15 05:12:41 PM PDT 24
Peak memory 256952 kb
Host smart-3e2ed20c-c0cc-42ba-8497-f0e4a85b9d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37316
83536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3731683536
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.737111807
Short name T613
Test name
Test status
Simulation time 72783595912 ps
CPU time 1896.79 seconds
Started Jul 15 05:12:09 PM PDT 24
Finished Jul 15 05:43:47 PM PDT 24
Peak memory 298468 kb
Host smart-af338139-64de-4eda-adea-14890106cbea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737111807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.737111807
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1965857109
Short name T102
Test name
Test status
Simulation time 102691064700 ps
CPU time 2044.78 seconds
Started Jul 15 05:12:11 PM PDT 24
Finished Jul 15 05:46:17 PM PDT 24
Peak memory 285348 kb
Host smart-5e84174d-21b5-42a5-b584-950005dfc510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965857109 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1965857109
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2477178392
Short name T201
Test name
Test status
Simulation time 104079027 ps
CPU time 2.89 seconds
Started Jul 15 05:12:10 PM PDT 24
Finished Jul 15 05:12:14 PM PDT 24
Peak memory 249432 kb
Host smart-cb467499-be1e-4bc9-b562-e5e172ff2daf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2477178392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2477178392
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1442702420
Short name T442
Test name
Test status
Simulation time 29750995587 ps
CPU time 2215.72 seconds
Started Jul 15 05:12:11 PM PDT 24
Finished Jul 15 05:49:07 PM PDT 24
Peak memory 286956 kb
Host smart-5b9a9127-7706-43ef-bb13-f54f77121c68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442702420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1442702420
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3384896156
Short name T392
Test name
Test status
Simulation time 156749275 ps
CPU time 9.69 seconds
Started Jul 15 05:12:09 PM PDT 24
Finished Jul 15 05:12:20 PM PDT 24
Peak memory 249216 kb
Host smart-8f801c27-6574-496a-a844-cd3396a50731
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3384896156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3384896156
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.745167505
Short name T584
Test name
Test status
Simulation time 1625828242 ps
CPU time 33.63 seconds
Started Jul 15 05:12:05 PM PDT 24
Finished Jul 15 05:12:40 PM PDT 24
Peak memory 256716 kb
Host smart-668e4c13-d557-4538-a926-1e7c5e7cf182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74516
7505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.745167505
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1989662963
Short name T681
Test name
Test status
Simulation time 776716869 ps
CPU time 52.84 seconds
Started Jul 15 05:12:06 PM PDT 24
Finished Jul 15 05:13:00 PM PDT 24
Peak memory 249112 kb
Host smart-e41e6bf2-e745-4872-86f6-0211c4dcff13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19896
62963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1989662963
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3380513848
Short name T309
Test name
Test status
Simulation time 66417690990 ps
CPU time 2063.49 seconds
Started Jul 15 05:12:12 PM PDT 24
Finished Jul 15 05:46:36 PM PDT 24
Peak memory 273256 kb
Host smart-46893744-1e9f-4ed5-a503-7a4a26aa1be6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380513848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3380513848
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3092395597
Short name T475
Test name
Test status
Simulation time 282151471969 ps
CPU time 2413.48 seconds
Started Jul 15 05:12:08 PM PDT 24
Finished Jul 15 05:52:23 PM PDT 24
Peak memory 283896 kb
Host smart-686bbc6a-fd0d-4eef-8eee-2e574fae76d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092395597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3092395597
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1839000121
Short name T283
Test name
Test status
Simulation time 11456638367 ps
CPU time 406.67 seconds
Started Jul 15 05:12:10 PM PDT 24
Finished Jul 15 05:18:57 PM PDT 24
Peak memory 249332 kb
Host smart-398cae3d-5fd8-4411-9e34-44a8f0fab8a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839000121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1839000121
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.651465128
Short name T374
Test name
Test status
Simulation time 1519139466 ps
CPU time 8.54 seconds
Started Jul 15 05:12:08 PM PDT 24
Finished Jul 15 05:12:18 PM PDT 24
Peak memory 251916 kb
Host smart-fb83f0ae-79e9-4410-be50-36fb66bcf37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65146
5128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.651465128
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1136967326
Short name T46
Test name
Test status
Simulation time 406218475 ps
CPU time 38.51 seconds
Started Jul 15 05:12:09 PM PDT 24
Finished Jul 15 05:12:49 PM PDT 24
Peak memory 249188 kb
Host smart-6c00512d-ebaa-49a3-8658-ddef0abab8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
67326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1136967326
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1389100645
Short name T598
Test name
Test status
Simulation time 153202414 ps
CPU time 15.83 seconds
Started Jul 15 05:12:07 PM PDT 24
Finished Jul 15 05:12:24 PM PDT 24
Peak memory 249160 kb
Host smart-1b1ba8b6-562c-4374-81e3-68def109eb52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13891
00645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1389100645
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3014192455
Short name T375
Test name
Test status
Simulation time 3239345722 ps
CPU time 45.48 seconds
Started Jul 15 05:12:09 PM PDT 24
Finished Jul 15 05:12:56 PM PDT 24
Peak memory 257480 kb
Host smart-dfa27e70-0715-4edc-a172-6b4ee94e2f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30141
92455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3014192455
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.803980637
Short name T564
Test name
Test status
Simulation time 3153452796 ps
CPU time 265.25 seconds
Started Jul 15 05:12:07 PM PDT 24
Finished Jul 15 05:16:34 PM PDT 24
Peak memory 257476 kb
Host smart-6b43c449-f7aa-497c-ad08-7218089aab48
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803980637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.803980637
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.4285895412
Short name T203
Test name
Test status
Simulation time 38692298 ps
CPU time 2.6 seconds
Started Jul 15 05:12:23 PM PDT 24
Finished Jul 15 05:12:26 PM PDT 24
Peak memory 249392 kb
Host smart-1348f17a-10f1-45b2-80b1-177c8b142210
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4285895412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.4285895412
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3800496256
Short name T600
Test name
Test status
Simulation time 219237178594 ps
CPU time 3126.15 seconds
Started Jul 15 05:12:17 PM PDT 24
Finished Jul 15 06:04:24 PM PDT 24
Peak memory 289192 kb
Host smart-5783e0be-2ac0-4e61-b751-42606fba5be0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800496256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3800496256
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1839340331
Short name T402
Test name
Test status
Simulation time 178698105 ps
CPU time 10.98 seconds
Started Jul 15 05:12:25 PM PDT 24
Finished Jul 15 05:12:36 PM PDT 24
Peak memory 249136 kb
Host smart-97310604-1735-4a75-91ac-efd040a97c90
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1839340331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1839340331
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2384776470
Short name T707
Test name
Test status
Simulation time 1130149344 ps
CPU time 20.28 seconds
Started Jul 15 05:12:17 PM PDT 24
Finished Jul 15 05:12:37 PM PDT 24
Peak memory 256680 kb
Host smart-10cc7dd6-51d7-465b-834e-4c14580a8f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23847
76470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2384776470
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2460059532
Short name T458
Test name
Test status
Simulation time 2246134303 ps
CPU time 66.46 seconds
Started Jul 15 05:12:17 PM PDT 24
Finished Jul 15 05:13:24 PM PDT 24
Peak memory 249072 kb
Host smart-1ff2492f-d159-4f22-972b-f8e00afc0955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24600
59532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2460059532
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3841559563
Short name T317
Test name
Test status
Simulation time 13810596187 ps
CPU time 1219.38 seconds
Started Jul 15 05:12:24 PM PDT 24
Finished Jul 15 05:32:44 PM PDT 24
Peak memory 273660 kb
Host smart-c43814c1-b9e9-4798-a879-98f50523f9aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841559563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3841559563
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.731124722
Short name T99
Test name
Test status
Simulation time 307061364245 ps
CPU time 3176.18 seconds
Started Jul 15 05:12:25 PM PDT 24
Finished Jul 15 06:05:22 PM PDT 24
Peak memory 290140 kb
Host smart-4160adcc-b088-41d0-b936-602f750eca4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731124722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.731124722
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3690030334
Short name T288
Test name
Test status
Simulation time 125184653045 ps
CPU time 359.42 seconds
Started Jul 15 05:12:16 PM PDT 24
Finished Jul 15 05:18:16 PM PDT 24
Peak memory 248392 kb
Host smart-4ba4b8fd-d538-4a9a-aa4d-572798fec408
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690030334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3690030334
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1193674637
Short name T523
Test name
Test status
Simulation time 249585433 ps
CPU time 20.09 seconds
Started Jul 15 05:12:16 PM PDT 24
Finished Jul 15 05:12:36 PM PDT 24
Peak memory 249252 kb
Host smart-e7f7f149-f76f-44e9-8977-8ece5063a2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11936
74637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1193674637
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1588357077
Short name T50
Test name
Test status
Simulation time 642292873 ps
CPU time 19.46 seconds
Started Jul 15 05:12:20 PM PDT 24
Finished Jul 15 05:12:40 PM PDT 24
Peak memory 249220 kb
Host smart-c105d41c-6510-4dc6-9c19-bd94ed56296d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15883
57077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1588357077
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1696624462
Short name T262
Test name
Test status
Simulation time 408955670 ps
CPU time 27.44 seconds
Started Jul 15 05:12:14 PM PDT 24
Finished Jul 15 05:12:42 PM PDT 24
Peak memory 257228 kb
Host smart-89daa2c8-9fe9-411c-8c28-93090b03cba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16966
24462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1696624462
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.437160097
Short name T521
Test name
Test status
Simulation time 596348009 ps
CPU time 46.38 seconds
Started Jul 15 05:12:19 PM PDT 24
Finished Jul 15 05:13:07 PM PDT 24
Peak memory 257376 kb
Host smart-5dc7d2b6-1667-43f5-b763-cb5122ef1758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43716
0097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.437160097
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3863211907
Short name T206
Test name
Test status
Simulation time 43330446 ps
CPU time 4.07 seconds
Started Jul 15 05:12:31 PM PDT 24
Finished Jul 15 05:12:36 PM PDT 24
Peak memory 249344 kb
Host smart-aba2f76f-b9c2-451e-b59d-48ec012dc7c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3863211907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3863211907
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.621216187
Short name T453
Test name
Test status
Simulation time 36112676058 ps
CPU time 2520.4 seconds
Started Jul 15 05:12:35 PM PDT 24
Finished Jul 15 05:54:36 PM PDT 24
Peak memory 289604 kb
Host smart-52a5f0b4-8d32-4900-91bb-f9b7cb771151
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621216187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.621216187
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1115274275
Short name T672
Test name
Test status
Simulation time 208066833 ps
CPU time 11.94 seconds
Started Jul 15 05:12:34 PM PDT 24
Finished Jul 15 05:12:46 PM PDT 24
Peak memory 249252 kb
Host smart-8c1dc4b7-3791-46a3-bceb-d1bdd70ab85f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1115274275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1115274275
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1328213380
Short name T368
Test name
Test status
Simulation time 4408381335 ps
CPU time 32.44 seconds
Started Jul 15 05:12:32 PM PDT 24
Finished Jul 15 05:13:05 PM PDT 24
Peak memory 256844 kb
Host smart-90746119-dafd-4dcd-be00-e36fddeff33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13282
13380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1328213380
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2018083479
Short name T605
Test name
Test status
Simulation time 285424795 ps
CPU time 21.41 seconds
Started Jul 15 05:12:25 PM PDT 24
Finished Jul 15 05:12:47 PM PDT 24
Peak memory 249176 kb
Host smart-48c7a334-8f37-494a-a306-51335f993724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20180
83479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2018083479
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1311459679
Short name T640
Test name
Test status
Simulation time 154012341465 ps
CPU time 2267.96 seconds
Started Jul 15 05:12:33 PM PDT 24
Finished Jul 15 05:50:22 PM PDT 24
Peak memory 273812 kb
Host smart-562796ae-06f9-41b7-84b5-84622f47880a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311459679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1311459679
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.865616699
Short name T387
Test name
Test status
Simulation time 534068751701 ps
CPU time 1761.17 seconds
Started Jul 15 05:12:31 PM PDT 24
Finished Jul 15 05:41:53 PM PDT 24
Peak memory 273752 kb
Host smart-97cb599a-1f67-4fe7-91a2-855b78021157
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865616699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.865616699
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3832411350
Short name T314
Test name
Test status
Simulation time 10601567407 ps
CPU time 458.14 seconds
Started Jul 15 05:12:31 PM PDT 24
Finished Jul 15 05:20:10 PM PDT 24
Peak memory 249328 kb
Host smart-03379d04-364f-4cc5-bf6e-610cfb0848ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832411350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3832411350
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.4033484781
Short name T639
Test name
Test status
Simulation time 719902969 ps
CPU time 12.38 seconds
Started Jul 15 05:12:24 PM PDT 24
Finished Jul 15 05:12:37 PM PDT 24
Peak memory 249200 kb
Host smart-90289246-0776-4163-bcd8-daf5ba6462da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40334
84781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.4033484781
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1166686643
Short name T399
Test name
Test status
Simulation time 1149368050 ps
CPU time 28.46 seconds
Started Jul 15 05:12:25 PM PDT 24
Finished Jul 15 05:12:54 PM PDT 24
Peak memory 248812 kb
Host smart-3105aa61-f153-4c51-b499-cd0b9edf947e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11666
86643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1166686643
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1336422162
Short name T405
Test name
Test status
Simulation time 432868262 ps
CPU time 26.08 seconds
Started Jul 15 05:12:30 PM PDT 24
Finished Jul 15 05:12:56 PM PDT 24
Peak memory 257364 kb
Host smart-c3e9af04-8e21-4294-a436-aa2bac28be27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13364
22162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1336422162
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3773741555
Short name T698
Test name
Test status
Simulation time 212893303 ps
CPU time 14.97 seconds
Started Jul 15 05:12:23 PM PDT 24
Finished Jul 15 05:12:38 PM PDT 24
Peak memory 255324 kb
Host smart-d22e11d1-3682-4aaa-b1e1-6ac7187c1b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37737
41555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3773741555
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.572622884
Short name T265
Test name
Test status
Simulation time 30410459900 ps
CPU time 460.72 seconds
Started Jul 15 05:12:35 PM PDT 24
Finished Jul 15 05:20:16 PM PDT 24
Peak memory 257484 kb
Host smart-ab152d94-3e7b-4eb8-8386-6b6065cef3ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572622884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.572622884
Directory /workspace/9.alert_handler_stress_all/latest
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