Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	86223	1			T1	130		T22	3505		T7	4
class_i[0x1]	77104	1			T6	2441		T25	10		T27	5258
class_i[0x2]	55893	1			T1	120		T9	4		T27	858
class_i[0x3]	58180	1			T6	11		T25	70		T11	5

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	67729	1			T1	31		T6	636		T22	819
alert[0x1]	70788	1			T1	28		T6	590		T22	955
alert[0x2]	67615	1			T1	165		T6	616		T22	817
alert[0x3]	71268	1			T1	26		T6	610		T22	914

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

277110

1

T1

250

T6

2452

T22

3505

esc_ping_fail

290

1

T7

2

T9

1

T11

5

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	67637	1			T1	31		T6	636		T22	819
esc_integrity_fail	alert[0x1]	70725	1			T1	28		T6	590		T22	955
esc_integrity_fail	alert[0x2]	67545	1			T1	165		T6	616		T22	817
esc_integrity_fail	alert[0x3]	71203	1			T1	26		T6	610		T22	914
esc_ping_fail	alert[0x0]	92	1			T7	1		T9	1		T11	2
esc_ping_fail	alert[0x1]	63	1			T7	1		T11	1		T84	1
esc_ping_fail	alert[0x2]	70	1			T84	3		T85	2		T64	1
esc_ping_fail	alert[0x3]	65	1			T11	2		T84	2		T85	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	86131	1			T1	130		T22	3505		T7	2
esc_integrity_fail	class_i[0x1]	77055	1			T6	2441		T25	10		T27	5258
esc_integrity_fail	class_i[0x2]	55852	1			T1	120		T9	3		T27	858
esc_integrity_fail	class_i[0x3]	58072	1			T6	11		T25	70		T85	18
esc_ping_fail	class_i[0x0]	92	1			T7	2		T84	5		T111	2
esc_ping_fail	class_i[0x1]	49	1			T85	8		T64	8		T215	6
esc_ping_fail	class_i[0x2]	41	1			T9	1		T84	1		T183	3
esc_ping_fail	class_i[0x3]	108	1			T11	5		T215	2		T111	8