Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	699378160	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	699378160	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	699378160	699206548	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	699378160	699206548	0	0
tb.dut.EdnKnownO_A	0	0	699378160	699206548	0	0
tb.dut.EscPKnownO_A	0	0	699378160	699206548	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	699378160	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	699378160	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	699378160	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	699378160	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	699378160	80	0	0
tb.dut.IrqAKnownO_A	0	0	699378160	699206548	0	0
tb.dut.IrqBKnownO_A	0	0	699378160	699206548	0	0
tb.dut.IrqCKnownO_A	0	0	699378160	699206548	0	0
tb.dut.IrqDKnownO_A	0	0	699378160	699206548	0	0
tb.dut.TlAReadyKnownO_A	0	0	699378160	699206548	0	0
tb.dut.TlDValidKnownO_A	0	0	699378160	699206548	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	724964780	2888617	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	724964780	14531	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	724964780	15665	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	724964780	14468	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	724964780	14356	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	724964780	14552	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	724964780	15574	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	724964780	14344	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	724964780	14511	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	724964780	14096	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	724964780	14337	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	724964780	14534	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	724964780	14322	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	724964780	14430	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	724964780	14712	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	724964780	14305	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	724964780	15592	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	724964780	14506	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	724964780	14863	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	724964780	14432	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	724964780	14535	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	724964780	15725	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	724964780	15746	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	724964780	14428	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	724964780	14255	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	724964780	14545	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	724964780	14422	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	724964780	14394	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	724964780	14573	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	724964780	14887	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	724964780	14532	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	724964780	14163	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	724964780	14249	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	724964780	14439	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	724964780	15637	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	724964780	15659	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	724964780	14686	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	724964780	14048	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	724964780	14135	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	724964780	15783	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	724964780	15822	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	724964780	15538	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	724964780	14319	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	724964780	14427	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	724964780	14408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	724964780	14498	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	724964780	14231	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	724964780	15217	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	724964780	15580	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	724964780	14561	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	724964780	14515	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	724964780	15531	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	724964780	14667	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	724964780	14650	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	724964780	14481	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	724964780	14834	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	724964780	14265	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	724964780	15568	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	724964780	14416	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	724964780	14095	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	724964780	14738	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	724964780	14348	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	724964780	15856	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	724964780	15696	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	724964780	14429	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	724964780	14399	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	724964780	14630	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	724964780	14161	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	724964780	14387	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	724964780	14215	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	724964780	27538	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	724964780	13967	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	724964780	14547	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	724964780	15701	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	724964780	14367	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	724964780	14585	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	724964780	14365	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	724964780	14510	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	724964780	14453	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	699378160	3007	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	699378160	271286	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	699378160	330959940	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	699378160	279	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	699378160	896	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	699378160	41	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	699378160	441	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	699066942	258765655	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	699378160	996	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	699378160	975	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	699378160	951	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	699378160	933	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	699378160	1020	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	699378160	118832	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	699378160	904	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	699378160	71	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	699378160	1435	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	699378160	1195	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	699064235	698994223	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	699378160	699206548	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	699378160	3710	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	699378160	174273	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	699378160	395890985	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	699378160	312	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	699378160	503	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	699378160	17	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	699378160	253	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	699066942	325243468	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	699378160	581	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	699378160	573	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	699378160	564	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	699378160	551	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	699378160	1214	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	699378160	127111	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	699378160	1127	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	699378160	69	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	699378160	1477	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	699378160	1237	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	699064235	698994223	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	699378160	699206548	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	699378160	5944	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	699378160	155677	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	699378160	441308089	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	699378160	284	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	699378160	495	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	699378160	21	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	699378160	223	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	699066942	333326047	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	699378160	563	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	699378160	554	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	699378160	547	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	699378160	536	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	699378160	1321	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	699378160	147712	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	699378160	1244	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	699378160	55	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	699378160	1452	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	699378160	1212	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	699064235	698994223	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	699378160	699206548	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	699378160	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	699378160	1608	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	699378160	198636	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	699378160	406665481	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	699378160	250	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	699378160	529	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	699378160	16	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	699378160	260	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	699066942	309387879	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	699378160	598	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	699378160	590	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	699378160	575	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	699378160	563	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	699378160	830	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	699378160	104697	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	699378160	754	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	699378160	60	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	699378160	1379	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	699378160	1139	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	699064235	698994223	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	699378160	699206548	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	724964780	131606262	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	724964780	724300428	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	724964780	724300428	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	724964780	197967167	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	724964780	724300428	0	0
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