Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	71	1			T27	1		T43	2		T75	1
class_index[0x1]	69	1			T25	1		T26	1		T28	1
class_index[0x2]	55	1			T27	1		T69	3		T74	1
class_index[0x3]	60	1			T1	1		T22	2		T25	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	94	1			T25	1		T26	1		T27	2
intr_timeout_cnt[1]	58	1			T43	2		T79	1		T39	2
intr_timeout_cnt[2]	27	1			T22	1		T67	1		T45	1
intr_timeout_cnt[3]	18	1			T43	1		T63	1		T105	3
intr_timeout_cnt[4]	15	1			T28	1		T78	1		T105	1
intr_timeout_cnt[5]	14	1			T104	2		T246	1		T112	1
intr_timeout_cnt[6]	9	1			T25	1		T45	1		T246	1
intr_timeout_cnt[7]	11	1			T1	1		T22	1		T75	1
intr_timeout_cnt[8]	5	1			T28	1		T53	1		T235	1
intr_timeout_cnt[9]	4	1			T34	1		T80	1		T247	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	22	1			T27	1		T77	1		T39	1
class_index[0x0]	intr_timeout_cnt[1]	21	1			T43	2		T79	1		T97	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T78	1		T81	1		T234	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T248	1		T249	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	7	1			T112	1		T250	1		T251	5
class_index[0x0]	intr_timeout_cnt[6]	4	1			T246	1		T252	1		T103	1
class_index[0x0]	intr_timeout_cnt[7]	6	1			T75	1		T55	1		T103	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T253	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T80	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	34	1			T25	1		T26	1		T63	2
class_index[0x1]	intr_timeout_cnt[1]	13	1			T246	1		T254	1		T234	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T67	1		T45	1		T31	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T255	1		T256	1		T257	1
class_index[0x1]	intr_timeout_cnt[4]	7	1			T28	1		T78	1		T246	1
class_index[0x1]	intr_timeout_cnt[5]	1	1			T258	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T55	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T34	1		T29	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	19	1			T27	1		T69	3		T74	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T39	1		T259	1		T96	1
class_index[0x2]	intr_timeout_cnt[2]	6	1			T33	1		T80	1		T81	1
class_index[0x2]	intr_timeout_cnt[3]	7	1			T105	3		T260	1		T261	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T249	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	4	1			T104	2		T262	1		T263	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T264	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T235	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	19	1			T105	2		T24	1		T259	1
class_index[0x3]	intr_timeout_cnt[1]	10	1			T39	1		T246	1		T234	2
class_index[0x3]	intr_timeout_cnt[2]	7	1			T22	1		T78	1		T39	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T43	1		T63	1		T247	1
class_index[0x3]	intr_timeout_cnt[4]	6	1			T105	1		T265	3		T266	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T246	1		T256	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	3	1			T25	1		T45	1		T247	1
class_index[0x3]	intr_timeout_cnt[7]	4	1			T1	1		T22	1		T252	1
class_index[0x3]	intr_timeout_cnt[8]	3	1			T28	1		T53	1		T29	1
class_index[0x3]	intr_timeout_cnt[9]	1	1			T247	1		-	-		-	-