Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	354623	1			T1	19		T2	35		T3	27
all_values[1]	354623	1			T1	19		T2	35		T3	27
all_values[2]	354623	1			T1	19		T2	35		T3	27
all_values[3]	354623	1			T1	19		T2	35		T3	27

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

705933

1

T1

38

T2

63

T3

46

auto[1]

712559

1

T1

38

T2

77

T3

62

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

839120

1

T1

13

T2

123

T3

97

auto[1]

579372

1

T1

63

T2

17

T3

11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99588	1			T2	6		T3	11		T4	257
all_values[0]	auto[0]	auto[1]	77119	1			T1	8		T2	6		T3	6
all_values[0]	auto[1]	auto[0]	100542	1			T1	2		T2	12		T3	5
all_values[0]	auto[1]	auto[1]	77374	1			T1	9		T2	11		T3	5
all_values[1]	auto[0]	auto[0]	105893	1			T2	19		T3	14		T4	254
all_values[1]	auto[0]	auto[1]	69749	1			T1	10		T4	239		T6	260
all_values[1]	auto[1]	auto[0]	108265	1			T1	2		T2	16		T3	13
all_values[1]	auto[1]	auto[1]	70716	1			T1	7		T4	265		T6	227
all_values[2]	auto[0]	auto[0]	105516	1			T1	2		T2	14		T3	6
all_values[2]	auto[0]	auto[1]	70977	1			T1	7		T4	263		T6	222
all_values[2]	auto[1]	auto[0]	107217	1			T1	1		T2	21		T3	21
all_values[2]	auto[1]	auto[1]	70913	1			T1	9		T4	250		T6	237
all_values[3]	auto[0]	auto[0]	105697	1			T1	4		T2	18		T3	9
all_values[3]	auto[0]	auto[1]	71394	1			T1	7		T4	242		T6	203
all_values[3]	auto[1]	auto[0]	106402	1			T1	2		T2	17		T3	18
all_values[3]	auto[1]	auto[1]	71130	1			T1	6		T4	270		T6	215