Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	354623	1			T1	19		T2	35		T3	27
all_pins[1]	354623	1			T1	19		T2	35		T3	27
all_pins[2]	354623	1			T1	19		T2	35		T3	27
all_pins[3]	354623	1			T1	19		T2	35		T3	27

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1128359	1			T1	45		T2	129		T3	103
values[0x1]	290133	1			T1	31		T2	11		T3	5
transitions[0x0=>0x1]	192791	1			T1	18		T2	10		T3	5
transitions[0x1=>0x0]	193045	1			T1	19		T2	11		T3	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	277249	1			T1	10		T2	24		T3	22
all_pins[0]	values[0x1]	77374	1			T1	9		T2	11		T3	5
all_pins[0]	transitions[0x0=>0x1]	76784	1			T1	7		T2	10		T3	5
all_pins[0]	transitions[0x1=>0x0]	70794	1			T1	5		T4	270		T6	215
all_pins[1]	values[0x0]	283907	1			T1	12		T2	35		T3	27
all_pins[1]	values[0x1]	70716	1			T1	7		T4	265		T6	227
all_pins[1]	transitions[0x0=>0x1]	37835	1			T1	3		T4	137		T6	116
all_pins[1]	transitions[0x1=>0x0]	44493	1			T1	5		T2	11		T3	5
all_pins[2]	values[0x0]	283710	1			T1	10		T2	35		T3	27
all_pins[2]	values[0x1]	70913	1			T1	9		T4	250		T6	237
all_pins[2]	transitions[0x0=>0x1]	38948	1			T1	5		T4	127		T6	127
all_pins[2]	transitions[0x1=>0x0]	38751	1			T1	3		T4	142		T6	117
all_pins[3]	values[0x0]	283493	1			T1	13		T2	35		T3	27
all_pins[3]	values[0x1]	71130	1			T1	6		T4	270		T6	215
all_pins[3]	transitions[0x0=>0x1]	39224	1			T1	3		T4	131		T6	116
all_pins[3]	transitions[0x1=>0x0]	39007	1			T1	6		T4	111		T6	138