Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1			T158	4		T159	4		T160	4
all_values[1]	266	1			T158	4		T159	4		T160	4
all_values[2]	266	1			T158	4		T159	4		T160	4
all_values[3]	266	1			T158	4		T159	4		T160	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

586

1

T158

12

T159

11

T160

12

auto[1]

478

1

T158

4

T159

5

T160

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

439

1

T158

13

T159

6

T160

11

auto[1]

625

1

T158

3

T159

10

T160

5

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

660

1

T158

13

T159

10

T160

13

auto[1]

404

1

T158

3

T159

6

T160

3

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

62

1

T158

2

T160

1

T244

2

all_values[0]

auto[0]

auto[0]

auto[1]

25

1

T159

1

T160

1

T244

1

all_values[0]

auto[0]

auto[1]

auto[0]

56

1

T158

2

T160

1

T232

3

all_values[0]

auto[0]

auto[1]

auto[1]

25

1

T159

2

T325

1

T326

1

all_values[0]

auto[1]

auto[0]

auto[1]

49

1

T159

1

T160

1

T232

3

all_values[0]

auto[1]

auto[1]

auto[1]

49

1

T232

1

T325

1

T326

2

all_values[1]

auto[0]

auto[0]

auto[0]

44

1

T158

1

T159

1

T160

3

all_values[1]

auto[0]

auto[0]

auto[1]

42

1

T159

1

T244

1

T327

2

all_values[1]

auto[0]

auto[1]

auto[0]

58

1

T158

2

T159

1

T160

1

all_values[1]

auto[0]

auto[1]

auto[1]

20

1

T232

1

T244

1

T326

1

all_values[1]

auto[1]

auto[0]

auto[1]

58

1

T158

1

T159

1

T232

2

all_values[1]

auto[1]

auto[1]

auto[1]

44

1

T232

1

T244

2

T327

1

all_values[2]

auto[0]

auto[0]

auto[0]

65

1

T158

3

T159

3

T232

2

all_values[2]

auto[0]

auto[0]

auto[1]

28

1

T160

1

T232

1

T244

1

all_values[2]

auto[0]

auto[1]

auto[0]

46

1

T160

2

T328

1

T329

2

all_values[2]

auto[0]

auto[1]

auto[1]

27

1

T232

1

T330

1

T331

1

all_values[2]

auto[1]

auto[0]

auto[1]

63

1

T158

1

T159

1

T160

1

all_values[2]

auto[1]

auto[1]

auto[1]

37

1

T232

2

T326

3

T332

2

all_values[3]

auto[0]

auto[0]

auto[0]

69

1

T158

3

T159

1

T160

3

all_values[3]

auto[0]

auto[0]

auto[1]

31

1

T244

1

T332

1

T333

1

all_values[3]

auto[0]

auto[1]

auto[0]

39

1

T232

2

T244

1

T327

1

all_values[3]

auto[0]

auto[1]

auto[1]

23

1

T327

1

T325

1

T330

1

all_values[3]

auto[1]

auto[0]

auto[1]

50

1

T158

1

T159

1

T160

1

all_values[3]

auto[1]

auto[1]

auto[1]

54

1

T159

2

T232

1

T327

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal