Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87249	1			T4	169		T6	268		T22	191
accum_cnt_1000	223623	1			T4	1244		T6	287		T22	152
accum_cnt_100	27354	1			T1	8		T2	11		T4	75
accum_cnt_50	64269	1			T1	14		T2	9		T4	51
accum_cnt_10	189984	1			T1	39		T2	6		T3	18
accum_cnt_0	409647	1			T1	51		T2	78		T3	58

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	261917	1			T1	28		T2	26		T3	19
class_index[0x1]	261917	1			T1	28		T2	26		T3	19
class_index[0x2]	261917	1			T1	28		T2	26		T3	19
class_index[0x3]	261917	1			T1	28		T2	26		T3	19

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	27634	1			T22	191		T8	418		T10	3
class_index[0x0]	accum_cnt_1000	67365	1			T22	152		T8	773		T10	799
class_index[0x0]	accum_cnt_100	9782	1			T1	8		T2	11		T17	13
class_index[0x0]	accum_cnt_50	21873	1			T1	9		T2	9		T17	12
class_index[0x0]	accum_cnt_10	42575	1			T1	11		T2	6		T3	18
class_index[0x0]	accum_cnt_0	77391	1			T3	1		T4	1		T18	7
class_index[0x1]	accum_cnt_2000	19362	1			T6	268		T8	567		T70	482
class_index[0x1]	accum_cnt_1000	55187	1			T4	694		T6	287		T8	508
class_index[0x1]	accum_cnt_100	5634	1			T4	41		T6	12		T8	33
class_index[0x1]	accum_cnt_50	12630	1			T4	28		T6	13		T21	16
class_index[0x1]	accum_cnt_10	52557	1			T1	5		T4	15		T6	8
class_index[0x1]	accum_cnt_0	106242	1			T1	23		T2	26		T3	19
class_index[0x2]	accum_cnt_2000	19961	1			T14	435		T27	531		T70	693
class_index[0x2]	accum_cnt_1000	53042	1			T14	391		T16	627		T27	535
class_index[0x2]	accum_cnt_100	6787	1			T14	21		T16	136		T27	81
class_index[0x2]	accum_cnt_50	15996	1			T22	7		T14	21		T26	20
class_index[0x2]	accum_cnt_10	41135	1			T4	782		T6	1		T21	37
class_index[0x2]	accum_cnt_0	117419	1			T1	28		T2	26		T3	19
class_index[0x3]	accum_cnt_2000	20292	1			T4	169		T27	578		T62	635
class_index[0x3]	accum_cnt_1000	48029	1			T4	550		T15	673		T27	623
class_index[0x3]	accum_cnt_100	5151	1			T4	34		T25	8		T15	84
class_index[0x3]	accum_cnt_50	13770	1			T1	5		T4	23		T6	720
class_index[0x3]	accum_cnt_10	53717	1			T1	23		T4	6		T6	5
class_index[0x3]	accum_cnt_0	108595	1			T2	26		T3	19		T4	2