Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4050	1			T85	1		T35	122		T63	107
alert[0x1]	4031	1			T7	1		T9	1		T11	1
alert[0x2]	8152	1			T27	1		T84	1		T85	1
alert[0x3]	5965	1			T9	1		T10	1		T27	2
alert[0x4]	23287	1			T10	1		T11	1		T75	1884
alert[0x5]	5826	1			T62	2		T85	1		T28	196
alert[0x6]	9085	1			T6	16		T27	1		T73	6
alert[0x7]	2733	1			T7	1		T11	1		T27	3
alert[0x8]	14221	1			T15	2		T73	2		T35	16
alert[0x9]	4624	1			T28	39		T35	5		T63	185
alert[0xa]	10636	1			T15	1		T11	1		T35	23
alert[0xb]	5925	1			T28	790		T35	18		T43	1
alert[0xc]	21267	1			T11	1		T73	1		T28	433
alert[0xd]	5705	1			T9	1		T85	1		T63	170
alert[0xe]	8537	1			T84	1		T64	1		T67	47
alert[0xf]	8964	1			T11	1		T35	11		T63	107
alert[0x10]	4578	1			T27	1		T85	1		T67	19
alert[0x11]	8842	1			T85	1		T63	158		T67	13
alert[0x12]	5919	1			T63	597		T183	1		T95	11
alert[0x13]	5194	1			T27	3		T28	99		T43	10
alert[0x14]	4252	1			T84	1		T35	380		T44	862
alert[0x15]	5354	1			T63	213		T31	4		T295	51
alert[0x16]	6067	1			T36	13		T84	1		T35	14
alert[0x17]	14155	1			T63	42		T67	4		T75	9
alert[0x18]	8195	1			T35	10		T63	184		T75	1
alert[0x19]	5896	1			T63	122		T45	25		T31	32
alert[0x1a]	4423	1			T11	1		T85	1		T35	17
alert[0x1b]	4437	1			T84	2		T85	2		T64	1
alert[0x1c]	3656	1			T28	33		T75	59		T45	3
alert[0x1d]	7469	1			T35	15		T75	93		T45	35
alert[0x1e]	5355	1			T27	22		T84	1		T43	12
alert[0x1f]	3778	1			T15	1		T27	10		T84	2
alert[0x20]	2583	1			T27	11		T84	1		T67	3
alert[0x21]	4412	1			T27	2		T28	359		T35	822
alert[0x22]	8746	1			T22	2		T85	1		T75	634
alert[0x23]	9523	1			T6	15		T22	7		T63	99
alert[0x24]	5439	1			T22	1		T84	1		T85	2
alert[0x25]	9280	1			T64	1		T75	314		T31	7
alert[0x26]	7750	1			T6	37		T35	3		T63	1907
alert[0x27]	7078	1			T28	160		T63	1045		T64	1
alert[0x28]	11849	1			T85	1		T28	339		T35	5
alert[0x29]	7320	1			T11	2		T28	141		T215	1
alert[0x2a]	8737	1			T7	1		T215	1		T45	433
alert[0x2b]	5919	1			T84	1		T28	1420		T215	1
alert[0x2c]	9680	1			T84	2		T85	1		T67	1
alert[0x2d]	9591	1			T28	8		T63	102		T67	1
alert[0x2e]	6749	1			T22	2		T11	1		T27	1
alert[0x2f]	9950	1			T9	1		T27	20		T28	1572
alert[0x30]	10553	1			T27	2		T28	10		T35	19
alert[0x31]	4541	1			T9	1		T27	6		T28	108
alert[0x32]	4187	1			T28	290		T35	88		T31	18
alert[0x33]	9886	1			T9	1		T35	47		T63	22
alert[0x34]	8641	1			T27	2		T35	14		T63	108
alert[0x35]	7740	1			T22	1		T27	8		T35	29
alert[0x36]	2054	1			T22	2		T64	2		T75	46
alert[0x37]	24460	1			T11	1		T35	293		T75	132
alert[0x38]	4245	1			T22	3		T28	72		T35	23
alert[0x39]	10458	1			T7	1		T27	1		T63	14
alert[0x3a]	7472	1			T11	1		T84	3		T85	1
alert[0x3b]	10742	1			T27	2		T36	11		T85	1
alert[0x3c]	5531	1			T63	76		T75	286		T215	1
alert[0x3d]	4971	1			T84	1		T85	1		T28	493
alert[0x3e]	9558	1			T84	1		T44	607		T215	1
alert[0x3f]	5516	1			T6	3		T75	1		T44	133
alert[0x40]	2359	1			T28	155		T35	56		T44	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	126751	1			T6	15		T22	2		T7	1
class_i[0x1]	151466	1			T7	1		T9	1		T11	1
class_i[0x2]	67982	1			T6	56		T22	16		T7	2
class_i[0x3]	151899	1			T9	2		T11	11		T27	11

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

497388

1

T6

71

T22

18

T27

98

alert_ping_fail

710

1

T7

4

T9

6

T10

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4041	1			T35	122		T63	107		T75	8
alert_integrity_fail	alert[0x1]	4018	1			T28	330		T35	5		T43	9
alert_integrity_fail	alert[0x2]	8139	1			T27	1		T28	13		T35	1
alert_integrity_fail	alert[0x3]	5954	1			T27	2		T75	477		T45	82
alert_integrity_fail	alert[0x4]	23273	1			T75	1884		T31	650		T296	16
alert_integrity_fail	alert[0x5]	5802	1			T28	196		T35	181		T63	462
alert_integrity_fail	alert[0x6]	9075	1			T6	16		T27	1		T73	6
alert_integrity_fail	alert[0x7]	2718	1			T27	3		T31	1		T295	21
alert_integrity_fail	alert[0x8]	14204	1			T73	2		T35	16		T63	227
alert_integrity_fail	alert[0x9]	4619	1			T28	39		T35	5		T63	185
alert_integrity_fail	alert[0xa]	10618	1			T35	23		T75	41		T31	90
alert_integrity_fail	alert[0xb]	5917	1			T28	790		T35	18		T43	1
alert_integrity_fail	alert[0xc]	21259	1			T73	1		T28	433		T35	294
alert_integrity_fail	alert[0xd]	5695	1			T63	170		T75	162		T44	2
alert_integrity_fail	alert[0xe]	8530	1			T67	47		T75	205		T44	66
alert_integrity_fail	alert[0xf]	8951	1			T35	11		T63	107		T44	1
alert_integrity_fail	alert[0x10]	4565	1			T27	1		T67	19		T75	359
alert_integrity_fail	alert[0x11]	8831	1			T63	158		T67	13		T44	203
alert_integrity_fail	alert[0x12]	5914	1			T63	597		T95	11		T295	1
alert_integrity_fail	alert[0x13]	5185	1			T27	3		T28	99		T43	10
alert_integrity_fail	alert[0x14]	4240	1			T35	380		T44	862		T45	216
alert_integrity_fail	alert[0x15]	5343	1			T63	213		T31	4		T295	51
alert_integrity_fail	alert[0x16]	6054	1			T36	13		T35	14		T67	71
alert_integrity_fail	alert[0x17]	14150	1			T63	42		T67	4		T75	9
alert_integrity_fail	alert[0x18]	8189	1			T35	10		T63	184		T75	1
alert_integrity_fail	alert[0x19]	5888	1			T63	122		T45	25		T31	32
alert_integrity_fail	alert[0x1a]	4411	1			T35	17		T45	3		T31	310
alert_integrity_fail	alert[0x1b]	4429	1			T44	30		T45	1		T33	1
alert_integrity_fail	alert[0x1c]	3642	1			T28	33		T75	59		T45	3
alert_integrity_fail	alert[0x1d]	7455	1			T35	15		T75	93		T45	35
alert_integrity_fail	alert[0x1e]	5343	1			T27	22		T43	12		T75	23
alert_integrity_fail	alert[0x1f]	3759	1			T27	10		T28	176		T63	22
alert_integrity_fail	alert[0x20]	2572	1			T27	11		T67	3		T78	3
alert_integrity_fail	alert[0x21]	4402	1			T27	2		T28	359		T35	822
alert_integrity_fail	alert[0x22]	8736	1			T22	2		T75	634		T31	12
alert_integrity_fail	alert[0x23]	9515	1			T6	15		T22	7		T63	99
alert_integrity_fail	alert[0x24]	5429	1			T22	1		T63	266		T297	16
alert_integrity_fail	alert[0x25]	9268	1			T75	314		T31	7		T33	2
alert_integrity_fail	alert[0x26]	7737	1			T6	37		T35	3		T63	1907
alert_integrity_fail	alert[0x27]	7067	1			T28	160		T63	1045		T44	34
alert_integrity_fail	alert[0x28]	11834	1			T28	339		T35	5		T43	5
alert_integrity_fail	alert[0x29]	7310	1			T28	141		T45	344		T95	22
alert_integrity_fail	alert[0x2a]	8721	1			T45	433		T31	10		T33	4
alert_integrity_fail	alert[0x2b]	5910	1			T28	1420		T45	324		T31	32
alert_integrity_fail	alert[0x2c]	9662	1			T67	1		T44	377		T33	5
alert_integrity_fail	alert[0x2d]	9583	1			T28	8		T63	102		T67	1
alert_integrity_fail	alert[0x2e]	6735	1			T22	2		T27	1		T35	14
alert_integrity_fail	alert[0x2f]	9938	1			T27	20		T28	1572		T35	650
alert_integrity_fail	alert[0x30]	10539	1			T27	2		T28	10		T35	19
alert_integrity_fail	alert[0x31]	4523	1			T27	6		T28	108		T75	5
alert_integrity_fail	alert[0x32]	4180	1			T28	290		T35	88		T31	18
alert_integrity_fail	alert[0x33]	9878	1			T35	47		T63	22		T45	16
alert_integrity_fail	alert[0x34]	8635	1			T27	2		T35	14		T63	108
alert_integrity_fail	alert[0x35]	7729	1			T22	1		T27	8		T35	29
alert_integrity_fail	alert[0x36]	2045	1			T22	2		T75	46		T80	47
alert_integrity_fail	alert[0x37]	24451	1			T35	293		T75	132		T44	2
alert_integrity_fail	alert[0x38]	4236	1			T22	3		T28	72		T35	23
alert_integrity_fail	alert[0x39]	10447	1			T27	1		T63	14		T67	2
alert_integrity_fail	alert[0x3a]	7461	1			T28	160		T35	23		T63	32
alert_integrity_fail	alert[0x3b]	10729	1			T27	2		T36	11		T28	100
alert_integrity_fail	alert[0x3c]	5520	1			T63	76		T75	286		T295	22
alert_integrity_fail	alert[0x3d]	4962	1			T28	493		T43	1		T75	268
alert_integrity_fail	alert[0x3e]	9552	1			T44	607		T45	87		T33	98
alert_integrity_fail	alert[0x3f]	5513	1			T6	3		T75	1		T44	133
alert_integrity_fail	alert[0x40]	2358	1			T28	155		T35	56		T44	1
alert_ping_fail	alert[0x0]	9	1			T85	1		T298	1		T222	2
alert_ping_fail	alert[0x1]	13	1			T7	1		T9	1		T11	1
alert_ping_fail	alert[0x2]	13	1			T84	1		T85	1		T215	1
alert_ping_fail	alert[0x3]	11	1			T9	1		T10	1		T240	1
alert_ping_fail	alert[0x4]	14	1			T10	1		T11	1		T216	1
alert_ping_fail	alert[0x5]	24	1			T62	2		T85	1		T215	2
alert_ping_fail	alert[0x6]	10	1			T111	1		T240	1		T299	1
alert_ping_fail	alert[0x7]	15	1			T7	1		T11	1		T183	1
alert_ping_fail	alert[0x8]	17	1			T15	2		T183	1		T238	1
alert_ping_fail	alert[0x9]	5	1			T215	1		T183	1		T300	1
alert_ping_fail	alert[0xa]	18	1			T15	1		T11	1		T238	1
alert_ping_fail	alert[0xb]	8	1			T301	1		T216	1		T279	1
alert_ping_fail	alert[0xc]	8	1			T11	1		T302	1		T303	1
alert_ping_fail	alert[0xd]	10	1			T9	1		T85	1		T304	1
alert_ping_fail	alert[0xe]	7	1			T84	1		T64	1		T305	1
alert_ping_fail	alert[0xf]	13	1			T11	1		T238	1		T298	1
alert_ping_fail	alert[0x10]	13	1			T85	1		T298	1		T304	1
alert_ping_fail	alert[0x11]	11	1			T85	1		T111	1		T240	1
alert_ping_fail	alert[0x12]	5	1			T183	1		T304	1		T302	1
alert_ping_fail	alert[0x13]	9	1			T111	1		T238	1		T306	1
alert_ping_fail	alert[0x14]	12	1			T84	1		T183	1		T32	1
alert_ping_fail	alert[0x15]	11	1			T307	1		T223	1		T279	1
alert_ping_fail	alert[0x16]	13	1			T84	1		T215	1		T291	1
alert_ping_fail	alert[0x17]	5	1			T303	1		T226	1		T279	1
alert_ping_fail	alert[0x18]	6	1			T238	1		T301	1		T303	1
alert_ping_fail	alert[0x19]	8	1			T238	1		T302	1		T305	1
alert_ping_fail	alert[0x1a]	12	1			T11	1		T85	1		T298	1
alert_ping_fail	alert[0x1b]	8	1			T84	2		T85	2		T64	1
alert_ping_fail	alert[0x1c]	14	1			T240	1		T298	1		T308	1
alert_ping_fail	alert[0x1d]	14	1			T111	2		T304	1		T303	1
alert_ping_fail	alert[0x1e]	12	1			T84	1		T215	1		T183	1
alert_ping_fail	alert[0x1f]	19	1			T15	1		T84	2		T294	1
alert_ping_fail	alert[0x20]	11	1			T84	1		T215	1		T309	1
alert_ping_fail	alert[0x21]	10	1			T238	1		T302	1		T303	1
alert_ping_fail	alert[0x22]	10	1			T85	1		T111	1		T238	1
alert_ping_fail	alert[0x23]	8	1			T298	1		T302	1		T310	2
alert_ping_fail	alert[0x24]	10	1			T84	1		T85	2		T111	1
alert_ping_fail	alert[0x25]	12	1			T64	1		T238	1		T305	2
alert_ping_fail	alert[0x26]	13	1			T111	1		T183	1		T304	1
alert_ping_fail	alert[0x27]	11	1			T64	1		T238	1		T304	1
alert_ping_fail	alert[0x28]	15	1			T85	1		T240	1		T304	1
alert_ping_fail	alert[0x29]	10	1			T11	2		T215	1		T311	1
alert_ping_fail	alert[0x2a]	16	1			T7	1		T215	1		T111	1
alert_ping_fail	alert[0x2b]	9	1			T84	1		T215	1		T183	1
alert_ping_fail	alert[0x2c]	18	1			T84	2		T85	1		T215	1
alert_ping_fail	alert[0x2d]	8	1			T183	1		T298	1		T302	1
alert_ping_fail	alert[0x2e]	14	1			T11	1		T238	1		T312	1
alert_ping_fail	alert[0x2f]	12	1			T9	1		T240	1		T290	1
alert_ping_fail	alert[0x30]	14	1			T64	1		T313	1		T216	1
alert_ping_fail	alert[0x31]	18	1			T9	1		T215	1		T240	1
alert_ping_fail	alert[0x32]	7	1			T302	1		T226	1		T311	2
alert_ping_fail	alert[0x33]	8	1			T9	1		T215	1		T111	1
alert_ping_fail	alert[0x34]	6	1			T64	2		T183	1		T240	1
alert_ping_fail	alert[0x35]	11	1			T64	1		T302	1		T305	1
alert_ping_fail	alert[0x36]	9	1			T64	2		T302	1		T303	1
alert_ping_fail	alert[0x37]	9	1			T11	1		T215	1		T314	1
alert_ping_fail	alert[0x38]	9	1			T64	1		T111	1		T240	1
alert_ping_fail	alert[0x39]	11	1			T7	1		T240	1		T305	1
alert_ping_fail	alert[0x3a]	11	1			T11	1		T84	3		T85	1
alert_ping_fail	alert[0x3b]	13	1			T85	1		T215	1		T111	2
alert_ping_fail	alert[0x3c]	11	1			T215	1		T183	1		T302	1
alert_ping_fail	alert[0x3d]	9	1			T84	1		T85	1		T64	2
alert_ping_fail	alert[0x3e]	6	1			T84	1		T215	1		T183	1
alert_ping_fail	alert[0x3f]	3	1			T111	1		T315	1		T316	1
alert_ping_fail	alert[0x40]	1	1			T300	1		-	-		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	126569	1			T6	15		T22	2		T27	9
alert_integrity_fail	class_i[0x1]	151232	1			T27	78		T28	34		T43	7
alert_integrity_fail	class_i[0x2]	67861	1			T6	56		T22	16		T28	4630
alert_integrity_fail	class_i[0x3]	151726	1			T27	11		T73	9		T28	13
alert_ping_fail	class_i[0x0]	182	1			T7	1		T9	2		T10	2
alert_ping_fail	class_i[0x1]	234	1			T7	1		T9	1		T11	1
alert_ping_fail	class_i[0x2]	121	1			T7	2		T9	1		T15	4
alert_ping_fail	class_i[0x3]	173	1			T9	2		T11	11		T85	17