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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.99 98.74 100.00 100.00 100.00 99.38 99.32


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T773 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1679955472 Jul 16 05:38:05 PM PDT 24 Jul 16 05:38:16 PM PDT 24 596408871 ps
T774 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1771740659 Jul 16 05:38:08 PM PDT 24 Jul 16 05:38:21 PM PDT 24 166911481 ps
T775 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2115632031 Jul 16 05:37:30 PM PDT 24 Jul 16 05:37:53 PM PDT 24 173892546 ps
T776 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1913780804 Jul 16 05:38:19 PM PDT 24 Jul 16 05:38:22 PM PDT 24 10118791 ps
T148 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.576606716 Jul 16 05:38:06 PM PDT 24 Jul 16 05:56:42 PM PDT 24 12204942971 ps
T137 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.926030603 Jul 16 05:37:49 PM PDT 24 Jul 16 05:39:53 PM PDT 24 1554496677 ps
T133 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3464691125 Jul 16 05:37:45 PM PDT 24 Jul 16 05:41:42 PM PDT 24 1749949956 ps
T777 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3139602907 Jul 16 05:38:14 PM PDT 24 Jul 16 05:38:16 PM PDT 24 11443648 ps
T778 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.874153600 Jul 16 05:37:33 PM PDT 24 Jul 16 05:37:45 PM PDT 24 686527637 ps
T779 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3305682660 Jul 16 05:37:37 PM PDT 24 Jul 16 05:37:43 PM PDT 24 83997211 ps
T780 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1342025540 Jul 16 05:38:17 PM PDT 24 Jul 16 05:38:20 PM PDT 24 7346006 ps
T781 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2373981104 Jul 16 05:37:23 PM PDT 24 Jul 16 05:37:30 PM PDT 24 73822927 ps
T782 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1167214095 Jul 16 05:37:50 PM PDT 24 Jul 16 05:38:08 PM PDT 24 126938196 ps
T783 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3105263794 Jul 16 05:37:46 PM PDT 24 Jul 16 05:38:04 PM PDT 24 154041243 ps
T784 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3667072608 Jul 16 05:38:06 PM PDT 24 Jul 16 05:38:08 PM PDT 24 23764612 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1002603418 Jul 16 05:37:36 PM PDT 24 Jul 16 05:37:42 PM PDT 24 64203252 ps
T786 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1501925830 Jul 16 05:37:28 PM PDT 24 Jul 16 05:37:30 PM PDT 24 16962284 ps
T787 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1580090122 Jul 16 05:37:36 PM PDT 24 Jul 16 05:37:59 PM PDT 24 1250682493 ps
T149 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1272872533 Jul 16 05:37:59 PM PDT 24 Jul 16 05:55:49 PM PDT 24 57408597154 ps
T788 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1998215006 Jul 16 05:37:49 PM PDT 24 Jul 16 05:38:25 PM PDT 24 376209863 ps
T789 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1767585152 Jul 16 05:38:17 PM PDT 24 Jul 16 05:38:20 PM PDT 24 6446242 ps
T790 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4272684652 Jul 16 05:37:52 PM PDT 24 Jul 16 05:38:11 PM PDT 24 141986232 ps
T147 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2149349400 Jul 16 05:37:53 PM PDT 24 Jul 16 05:46:30 PM PDT 24 30829249010 ps
T791 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.4155458515 Jul 16 05:38:14 PM PDT 24 Jul 16 05:38:16 PM PDT 24 12504443 ps
T792 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3646584520 Jul 16 05:38:02 PM PDT 24 Jul 16 05:38:09 PM PDT 24 234996487 ps
T141 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2113412157 Jul 16 05:37:30 PM PDT 24 Jul 16 05:40:37 PM PDT 24 2783686903 ps
T793 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3736721447 Jul 16 05:38:08 PM PDT 24 Jul 16 05:38:31 PM PDT 24 357238329 ps
T794 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1706683467 Jul 16 05:37:52 PM PDT 24 Jul 16 05:38:01 PM PDT 24 6384877 ps
T162 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1784421704 Jul 16 05:37:36 PM PDT 24 Jul 16 05:37:41 PM PDT 24 103836874 ps
T142 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1547424094 Jul 16 05:37:56 PM PDT 24 Jul 16 05:47:10 PM PDT 24 83574136859 ps
T795 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1090809496 Jul 16 05:37:30 PM PDT 24 Jul 16 05:37:35 PM PDT 24 40539701 ps
T796 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.831687329 Jul 16 05:37:53 PM PDT 24 Jul 16 05:38:04 PM PDT 24 124625672 ps
T797 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1455748177 Jul 16 05:37:46 PM PDT 24 Jul 16 05:38:00 PM PDT 24 23258425 ps
T798 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3642803136 Jul 16 05:37:49 PM PDT 24 Jul 16 05:41:35 PM PDT 24 1724854223 ps
T799 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1768396707 Jul 16 05:38:19 PM PDT 24 Jul 16 05:38:22 PM PDT 24 20682459 ps
T150 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.919388774 Jul 16 05:38:00 PM PDT 24 Jul 16 05:40:50 PM PDT 24 2986057706 ps
T800 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.662296533 Jul 16 05:37:46 PM PDT 24 Jul 16 05:38:49 PM PDT 24 2785946500 ps
T801 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.414426246 Jul 16 05:37:49 PM PDT 24 Jul 16 05:38:07 PM PDT 24 110942465 ps
T145 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2221572489 Jul 16 05:37:37 PM PDT 24 Jul 16 05:47:46 PM PDT 24 4304292645 ps
T802 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2607936720 Jul 16 05:38:15 PM PDT 24 Jul 16 05:38:18 PM PDT 24 13346192 ps
T803 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2781144296 Jul 16 05:38:04 PM PDT 24 Jul 16 05:38:25 PM PDT 24 636090300 ps
T151 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3792383532 Jul 16 05:37:34 PM PDT 24 Jul 16 05:40:32 PM PDT 24 9845689947 ps
T804 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1074997127 Jul 16 05:38:04 PM PDT 24 Jul 16 05:38:16 PM PDT 24 238549794 ps
T153 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3185009841 Jul 16 05:37:38 PM PDT 24 Jul 16 05:42:15 PM PDT 24 2136490360 ps
T805 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.366851548 Jul 16 05:37:37 PM PDT 24 Jul 16 05:37:43 PM PDT 24 52782398 ps
T125 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1602361610 Jul 16 05:37:31 PM PDT 24 Jul 16 05:42:40 PM PDT 24 30978907834 ps
T806 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.266995615 Jul 16 05:37:44 PM PDT 24 Jul 16 05:37:46 PM PDT 24 39033100 ps
T807 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3229699208 Jul 16 05:37:55 PM PDT 24 Jul 16 05:38:05 PM PDT 24 250214262 ps
T334 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1478179242 Jul 16 05:37:58 PM PDT 24 Jul 16 05:56:53 PM PDT 24 117156890457 ps
T808 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2380012890 Jul 16 05:37:33 PM PDT 24 Jul 16 05:37:39 PM PDT 24 70273132 ps
T171 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3074177354 Jul 16 05:37:56 PM PDT 24 Jul 16 05:38:20 PM PDT 24 1385965304 ps
T809 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1363842002 Jul 16 05:37:37 PM PDT 24 Jul 16 05:37:47 PM PDT 24 247869248 ps
T175 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2127710440 Jul 16 05:37:51 PM PDT 24 Jul 16 05:38:03 PM PDT 24 235371048 ps
T810 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2140706299 Jul 16 05:37:57 PM PDT 24 Jul 16 05:38:04 PM PDT 24 66327953 ps
T811 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1004538714 Jul 16 05:37:33 PM PDT 24 Jul 16 05:37:35 PM PDT 24 7920986 ps
T812 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1398859783 Jul 16 05:38:15 PM PDT 24 Jul 16 05:38:18 PM PDT 24 11182455 ps
T813 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3260689998 Jul 16 05:38:07 PM PDT 24 Jul 16 05:38:09 PM PDT 24 15931618 ps
T814 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1078676239 Jul 16 05:37:53 PM PDT 24 Jul 16 05:38:07 PM PDT 24 542913562 ps
T815 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1155193315 Jul 16 05:38:03 PM PDT 24 Jul 16 05:38:15 PM PDT 24 359908680 ps
T816 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1999543446 Jul 16 05:38:14 PM PDT 24 Jul 16 05:38:16 PM PDT 24 12195496 ps
T166 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4185716396 Jul 16 05:37:35 PM PDT 24 Jul 16 05:38:14 PM PDT 24 2068725244 ps
T817 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1266668926 Jul 16 05:38:15 PM PDT 24 Jul 16 05:38:18 PM PDT 24 6264300 ps
T818 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.222729571 Jul 16 05:38:16 PM PDT 24 Jul 16 05:38:28 PM PDT 24 408165841 ps
T819 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1717293267 Jul 16 05:37:36 PM PDT 24 Jul 16 05:39:05 PM PDT 24 6808557179 ps
T820 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.904645345 Jul 16 05:37:36 PM PDT 24 Jul 16 05:37:57 PM PDT 24 171117470 ps
T152 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3340729870 Jul 16 05:37:56 PM PDT 24 Jul 16 05:39:43 PM PDT 24 829708989 ps
T167 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2890184659 Jul 16 05:38:02 PM PDT 24 Jul 16 05:38:06 PM PDT 24 43977238 ps
T821 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2199338897 Jul 16 05:38:13 PM PDT 24 Jul 16 05:38:15 PM PDT 24 50211741 ps
T154 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.227268530 Jul 16 05:37:46 PM PDT 24 Jul 16 05:43:05 PM PDT 24 2698034152 ps
T822 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2101832622 Jul 16 05:37:56 PM PDT 24 Jul 16 05:38:06 PM PDT 24 45449673 ps
T164 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2535245040 Jul 16 05:37:46 PM PDT 24 Jul 16 05:38:02 PM PDT 24 167299319 ps
T823 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1129963894 Jul 16 05:37:46 PM PDT 24 Jul 16 05:38:07 PM PDT 24 55707129 ps
T824 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4190754565 Jul 16 05:37:44 PM PDT 24 Jul 16 05:37:56 PM PDT 24 166739851 ps
T825 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3583531137 Jul 16 05:37:48 PM PDT 24 Jul 16 05:38:02 PM PDT 24 35678819 ps
T826 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2596180045 Jul 16 05:37:58 PM PDT 24 Jul 16 05:38:12 PM PDT 24 401350649 ps
T827 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1230672053 Jul 16 05:37:35 PM PDT 24 Jul 16 05:43:27 PM PDT 24 95313449541 ps
T828 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.935145732 Jul 16 05:38:18 PM PDT 24 Jul 16 05:38:21 PM PDT 24 6606027 ps
T335 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3878414658 Jul 16 05:37:36 PM PDT 24 Jul 16 05:47:28 PM PDT 24 6033578070 ps
T829 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1096686436 Jul 16 05:38:04 PM PDT 24 Jul 16 05:38:18 PM PDT 24 404507143 ps
T830 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.200117134 Jul 16 05:37:57 PM PDT 24 Jul 16 05:38:05 PM PDT 24 31087343 ps
T831 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.569320160 Jul 16 05:37:45 PM PDT 24 Jul 16 05:37:58 PM PDT 24 11899225 ps

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2376479382
Short name T4
Test name
Test status
Simulation time 20048860909 ps
CPU time 1566.76 seconds
Started Jul 16 05:39:10 PM PDT 24
Finished Jul 16 06:05:18 PM PDT 24
Peak memory 273960 kb
Host smart-b2772033-c8b7-4a91-ace0-6059175417c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376479382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2376479382
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.881591241
Short name T28
Test name
Test status
Simulation time 47914797445 ps
CPU time 4440.4 seconds
Started Jul 16 05:40:34 PM PDT 24
Finished Jul 16 06:54:36 PM PDT 24
Peak memory 338844 kb
Host smart-e0e35bb2-f3b5-4b17-89d1-fab21dcc2d13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881591241 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.881591241
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1518576153
Short name T27
Test name
Test status
Simulation time 1092643990031 ps
CPU time 3490.87 seconds
Started Jul 16 05:40:15 PM PDT 24
Finished Jul 16 06:38:27 PM PDT 24
Peak memory 290168 kb
Host smart-5ea6c274-f12e-4bba-bd5b-ca37db494b6a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518576153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1518576153
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1420758277
Short name T12
Test name
Test status
Simulation time 843348210 ps
CPU time 23.87 seconds
Started Jul 16 05:39:10 PM PDT 24
Finished Jul 16 05:39:35 PM PDT 24
Peak memory 277148 kb
Host smart-cdbca5dd-6540-43d9-8a9a-dd753585958a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1420758277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1420758277
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2386450817
Short name T155
Test name
Test status
Simulation time 2141424480 ps
CPU time 44.7 seconds
Started Jul 16 05:38:09 PM PDT 24
Finished Jul 16 05:38:54 PM PDT 24
Peak memory 240416 kb
Host smart-c3543136-9dd2-49b1-873b-8440a2d5e523
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2386450817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2386450817
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1228619240
Short name T22
Test name
Test status
Simulation time 37209694698 ps
CPU time 2185.35 seconds
Started Jul 16 05:39:25 PM PDT 24
Finished Jul 16 06:15:53 PM PDT 24
Peak memory 284996 kb
Host smart-96f550d2-9ed1-4e44-bc34-f4f238854cb1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228619240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1228619240
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3389758645
Short name T117
Test name
Test status
Simulation time 4914526592 ps
CPU time 309.61 seconds
Started Jul 16 05:38:05 PM PDT 24
Finished Jul 16 05:43:15 PM PDT 24
Peak memory 265464 kb
Host smart-f03c3a2f-814d-4375-80a3-f60d9be29ca8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3389758645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3389758645
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3541219821
Short name T34
Test name
Test status
Simulation time 293120948457 ps
CPU time 6998.66 seconds
Started Jul 16 05:39:17 PM PDT 24
Finished Jul 16 07:35:57 PM PDT 24
Peak memory 371912 kb
Host smart-10087e11-7ec5-4d53-ba06-a1cfbcb5edf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541219821 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3541219821
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2553217185
Short name T15
Test name
Test status
Simulation time 53158466913 ps
CPU time 1771.5 seconds
Started Jul 16 05:39:38 PM PDT 24
Finished Jul 16 06:09:12 PM PDT 24
Peak memory 273864 kb
Host smart-b7efddd9-5d73-4163-a233-02a6690c1c49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553217185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2553217185
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.439933125
Short name T96
Test name
Test status
Simulation time 49385222006 ps
CPU time 5021.3 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 07:02:55 PM PDT 24
Peak memory 339452 kb
Host smart-6643d2ef-c152-4b16-9380-3c4ee846fd14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439933125 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.439933125
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.997718047
Short name T126
Test name
Test status
Simulation time 122097641951 ps
CPU time 1016.54 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:54:34 PM PDT 24
Peak memory 265396 kb
Host smart-2ce8c987-89b8-420e-9e0e-5b187cf2d525
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997718047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.997718047
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.119231901
Short name T63
Test name
Test status
Simulation time 82632107593 ps
CPU time 2527.77 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 06:23:01 PM PDT 24
Peak memory 289704 kb
Host smart-909219a1-7c6f-4513-a0ec-29f069174f6a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119231901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.119231901
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2444581090
Short name T131
Test name
Test status
Simulation time 15562423737 ps
CPU time 207.08 seconds
Started Jul 16 05:38:05 PM PDT 24
Finished Jul 16 05:41:33 PM PDT 24
Peak memory 265520 kb
Host smart-f7306219-fdf0-4565-8d87-6fcab1f26c7f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2444581090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2444581090
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.796787852
Short name T324
Test name
Test status
Simulation time 100620721175 ps
CPU time 2916.68 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 06:28:14 PM PDT 24
Peak memory 290364 kb
Host smart-d68a0c08-851d-4a60-b176-3021bbcae18f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796787852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.796787852
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2213940446
Short name T33
Test name
Test status
Simulation time 99315815855 ps
CPU time 732.17 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 05:51:40 PM PDT 24
Peak memory 283144 kb
Host smart-5066791c-82b8-40fd-834a-732f6d134969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213940446 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2213940446
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2362942358
Short name T251
Test name
Test status
Simulation time 4276453544 ps
CPU time 65.21 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 05:41:31 PM PDT 24
Peak memory 256924 kb
Host smart-805aded9-34be-48c0-beb7-2b9b0afef422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23629
42358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2362942358
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1157900313
Short name T122
Test name
Test status
Simulation time 14089503502 ps
CPU time 1051.88 seconds
Started Jul 16 05:37:44 PM PDT 24
Finished Jul 16 05:55:16 PM PDT 24
Peak memory 272272 kb
Host smart-a9a1276a-0ef8-4922-aef6-c544efcf1da8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157900313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1157900313
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2198446901
Short name T84
Test name
Test status
Simulation time 12103039200 ps
CPU time 505.79 seconds
Started Jul 16 05:40:33 PM PDT 24
Finished Jul 16 05:49:00 PM PDT 24
Peak memory 256248 kb
Host smart-9bce93de-fb3b-4c0d-890b-7ac9250817d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198446901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2198446901
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3044147562
Short name T121
Test name
Test status
Simulation time 6339523198 ps
CPU time 212.33 seconds
Started Jul 16 05:37:37 PM PDT 24
Finished Jul 16 05:41:10 PM PDT 24
Peak memory 266468 kb
Host smart-487c6bf0-429b-4fd0-8c8b-a702fa6d769d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3044147562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3044147562
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1230856429
Short name T92
Test name
Test status
Simulation time 46391355703 ps
CPU time 1577.53 seconds
Started Jul 16 05:41:11 PM PDT 24
Finished Jul 16 06:07:30 PM PDT 24
Peak memory 272180 kb
Host smart-df9c0daf-2632-4518-bcd1-4bd2cedb1c35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230856429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1230856429
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1695579137
Short name T326
Test name
Test status
Simulation time 13575145 ps
CPU time 1.46 seconds
Started Jul 16 05:37:57 PM PDT 24
Finished Jul 16 05:38:02 PM PDT 24
Peak memory 237516 kb
Host smart-d86bd075-0ecb-44db-8cb3-f0de042c9c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1695579137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1695579137
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1012412326
Short name T75
Test name
Test status
Simulation time 236142065228 ps
CPU time 2022.84 seconds
Started Jul 16 05:40:35 PM PDT 24
Finished Jul 16 06:14:19 PM PDT 24
Peak memory 286516 kb
Host smart-206a2d16-fe7a-4927-92bf-c41818347d04
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012412326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1012412326
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2518013663
Short name T302
Test name
Test status
Simulation time 13354918671 ps
CPU time 538.29 seconds
Started Jul 16 05:40:02 PM PDT 24
Finished Jul 16 05:49:02 PM PDT 24
Peak memory 248236 kb
Host smart-cae077cd-b9e3-4105-a538-645dfbb34abe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518013663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2518013663
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1181292454
Short name T138
Test name
Test status
Simulation time 17489157038 ps
CPU time 623.9 seconds
Started Jul 16 05:37:29 PM PDT 24
Finished Jul 16 05:47:54 PM PDT 24
Peak memory 265440 kb
Host smart-9fb63cb8-ad05-4367-b8a7-80c9b75046da
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181292454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1181292454
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1872791251
Short name T227
Test name
Test status
Simulation time 217318367579 ps
CPU time 3117.98 seconds
Started Jul 16 05:39:52 PM PDT 24
Finished Jul 16 06:31:52 PM PDT 24
Peak memory 287600 kb
Host smart-6283a0bd-7428-4660-9e98-a3ed2b3ece2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872791251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1872791251
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2247340167
Short name T8
Test name
Test status
Simulation time 170179124500 ps
CPU time 1287.72 seconds
Started Jul 16 05:39:42 PM PDT 24
Finished Jul 16 06:01:12 PM PDT 24
Peak memory 282184 kb
Host smart-c52caee0-7725-4b38-bbf3-62d73beaf66c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247340167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2247340167
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1993584061
Short name T240
Test name
Test status
Simulation time 42367724625 ps
CPU time 441.04 seconds
Started Jul 16 05:40:02 PM PDT 24
Finished Jul 16 05:47:24 PM PDT 24
Peak memory 249348 kb
Host smart-dd5d8ee8-6d81-4c4e-9b23-ac35fe4eb481
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993584061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1993584061
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.926495533
Short name T124
Test name
Test status
Simulation time 4325937053 ps
CPU time 314.7 seconds
Started Jul 16 05:38:09 PM PDT 24
Finished Jul 16 05:43:24 PM PDT 24
Peak memory 266340 kb
Host smart-4f1e3ad7-6f01-48f9-ba35-700f14b365ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=926495533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.926495533
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1831958141
Short name T62
Test name
Test status
Simulation time 57143170556 ps
CPU time 3060.09 seconds
Started Jul 16 05:40:56 PM PDT 24
Finished Jul 16 06:31:57 PM PDT 24
Peak memory 290316 kb
Host smart-f7a41375-f845-4300-96bd-65ac619dee71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831958141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1831958141
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1156919311
Short name T136
Test name
Test status
Simulation time 16607182039 ps
CPU time 1306.64 seconds
Started Jul 16 05:37:43 PM PDT 24
Finished Jul 16 05:59:31 PM PDT 24
Peak memory 265528 kb
Host smart-16f54838-5dfb-477b-9b0c-40283865ac86
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156919311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1156919311
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3792383532
Short name T151
Test name
Test status
Simulation time 9845689947 ps
CPU time 176.54 seconds
Started Jul 16 05:37:34 PM PDT 24
Finished Jul 16 05:40:32 PM PDT 24
Peak memory 268820 kb
Host smart-e68c1a60-6499-45fb-9653-0104c78f5347
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3792383532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3792383532
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3634021640
Short name T300
Test name
Test status
Simulation time 13179221336 ps
CPU time 516.27 seconds
Started Jul 16 05:41:18 PM PDT 24
Finished Jul 16 05:49:57 PM PDT 24
Peak memory 249392 kb
Host smart-85bd397e-aa9e-4012-8443-6d6a9a606521
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634021640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3634021640
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1789289945
Short name T318
Test name
Test status
Simulation time 101401654058 ps
CPU time 1365.8 seconds
Started Jul 16 05:39:16 PM PDT 24
Finished Jul 16 06:02:03 PM PDT 24
Peak memory 272684 kb
Host smart-b4ea345e-cdac-4d72-808d-785f13622362
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789289945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1789289945
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.936696447
Short name T238
Test name
Test status
Simulation time 7361613532 ps
CPU time 311.68 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:45:07 PM PDT 24
Peak memory 249148 kb
Host smart-a22f08c4-0682-4798-a7b7-b7150b815b47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936696447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.936696447
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.576606716
Short name T148
Test name
Test status
Simulation time 12204942971 ps
CPU time 1114.38 seconds
Started Jul 16 05:38:06 PM PDT 24
Finished Jul 16 05:56:42 PM PDT 24
Peak memory 273060 kb
Host smart-4c4edbaf-9969-4e6e-a2c3-8475b510b5f6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576606716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.576606716
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.4120051446
Short name T45
Test name
Test status
Simulation time 75984375657 ps
CPU time 2130.71 seconds
Started Jul 16 05:40:47 PM PDT 24
Finished Jul 16 06:16:20 PM PDT 24
Peak memory 303284 kb
Host smart-2c658fae-0548-4447-9377-58b296c77e4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120051446 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.4120051446
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.4157557044
Short name T262
Test name
Test status
Simulation time 148120661228 ps
CPU time 3135.74 seconds
Started Jul 16 05:41:11 PM PDT 24
Finished Jul 16 06:33:29 PM PDT 24
Peak memory 300036 kb
Host smart-47e82bd8-c678-4b5d-831a-bc8cb5a9cb13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157557044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.4157557044
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1547424094
Short name T142
Test name
Test status
Simulation time 83574136859 ps
CPU time 549.81 seconds
Started Jul 16 05:37:56 PM PDT 24
Finished Jul 16 05:47:10 PM PDT 24
Peak memory 265364 kb
Host smart-26f5d1df-9bb1-484c-b4c5-b34b3572df0f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547424094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1547424094
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.975798379
Short name T332
Test name
Test status
Simulation time 15183476 ps
CPU time 1.6 seconds
Started Jul 16 05:38:05 PM PDT 24
Finished Jul 16 05:38:07 PM PDT 24
Peak memory 237560 kb
Host smart-be1c5821-5c19-44e4-a23e-69d57d4937b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=975798379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.975798379
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2411833779
Short name T292
Test name
Test status
Simulation time 177152867874 ps
CPU time 2723.75 seconds
Started Jul 16 05:40:30 PM PDT 24
Finished Jul 16 06:25:54 PM PDT 24
Peak memory 289996 kb
Host smart-c3373278-2813-4201-9e0b-8b41f693552b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411833779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2411833779
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.458452791
Short name T215
Test name
Test status
Simulation time 43811717991 ps
CPU time 553.61 seconds
Started Jul 16 05:40:36 PM PDT 24
Finished Jul 16 05:49:51 PM PDT 24
Peak memory 249120 kb
Host smart-2a1dc09a-5d8c-417e-a185-9e4052f7c211
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458452791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.458452791
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2589532244
Short name T279
Test name
Test status
Simulation time 13174898797 ps
CPU time 475.33 seconds
Started Jul 16 05:39:10 PM PDT 24
Finished Jul 16 05:47:07 PM PDT 24
Peak memory 249404 kb
Host smart-e9905cc6-1277-4ed4-813b-38341ac21886
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589532244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2589532244
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3148920839
Short name T53
Test name
Test status
Simulation time 141428911377 ps
CPU time 7672.87 seconds
Started Jul 16 05:40:46 PM PDT 24
Finished Jul 16 07:48:41 PM PDT 24
Peak memory 394840 kb
Host smart-8568a281-44fc-4106-9d7c-77fe94ea0b21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148920839 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3148920839
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3543813363
Short name T246
Test name
Test status
Simulation time 67555126564 ps
CPU time 2569.87 seconds
Started Jul 16 05:39:22 PM PDT 24
Finished Jul 16 06:22:13 PM PDT 24
Peak memory 284892 kb
Host smart-8c5e9ece-e6c9-4215-8ee7-b7a60a1f955f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543813363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3543813363
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.955073480
Short name T128
Test name
Test status
Simulation time 47250821262 ps
CPU time 287.75 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:42:24 PM PDT 24
Peak memory 265476 kb
Host smart-7f8e0fe6-e424-4ed9-9831-931e67e89813
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=955073480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.955073480
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.494093955
Short name T161
Test name
Test status
Simulation time 52942775 ps
CPU time 3.91 seconds
Started Jul 16 05:37:55 PM PDT 24
Finished Jul 16 05:38:03 PM PDT 24
Peak memory 237648 kb
Host smart-101d3220-3371-460f-bacc-6459ef4a9c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=494093955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.494093955
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1385093036
Short name T66
Test name
Test status
Simulation time 41830457 ps
CPU time 2.31 seconds
Started Jul 16 05:39:00 PM PDT 24
Finished Jul 16 05:39:03 PM PDT 24
Peak memory 249480 kb
Host smart-6e4515c8-b482-4168-8169-ac30c480aebf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1385093036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1385093036
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2080507878
Short name T207
Test name
Test status
Simulation time 52433347 ps
CPU time 3.85 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 05:39:33 PM PDT 24
Peak memory 249608 kb
Host smart-f80c8909-c345-4b58-8c9b-b799b92f42a1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2080507878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2080507878
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2057640073
Short name T198
Test name
Test status
Simulation time 55354624 ps
CPU time 3.14 seconds
Started Jul 16 05:39:19 PM PDT 24
Finished Jul 16 05:39:22 PM PDT 24
Peak memory 249544 kb
Host smart-a24752fb-26cf-416a-8fea-9b7e4674961f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2057640073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2057640073
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3434548994
Short name T196
Test name
Test status
Simulation time 218563880 ps
CPU time 4.83 seconds
Started Jul 16 05:39:30 PM PDT 24
Finished Jul 16 05:39:36 PM PDT 24
Peak memory 249492 kb
Host smart-39024150-a40e-48a5-9c29-4658140d7bd7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3434548994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3434548994
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1602361610
Short name T125
Test name
Test status
Simulation time 30978907834 ps
CPU time 307.41 seconds
Started Jul 16 05:37:31 PM PDT 24
Finished Jul 16 05:42:40 PM PDT 24
Peak memory 265276 kb
Host smart-d5213271-1380-42de-90ab-663196c8ca62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1602361610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1602361610
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1780151337
Short name T755
Test name
Test status
Simulation time 21705925 ps
CPU time 1.45 seconds
Started Jul 16 05:37:28 PM PDT 24
Finished Jul 16 05:37:30 PM PDT 24
Peak memory 237472 kb
Host smart-f970b82f-5074-4fe2-8b4e-8f505891619e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1780151337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1780151337
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3666214404
Short name T78
Test name
Test status
Simulation time 6591350460 ps
CPU time 41.2 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 05:40:09 PM PDT 24
Peak memory 249396 kb
Host smart-cc1bc219-6cf8-42ed-8a01-72c23e01458d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36662
14404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3666214404
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3954009456
Short name T80
Test name
Test status
Simulation time 89279154796 ps
CPU time 2711.19 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 06:25:08 PM PDT 24
Peak memory 290384 kb
Host smart-6e3fad71-1dcb-4417-a6c5-620501edcfde
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954009456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3954009456
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3058164519
Short name T320
Test name
Test status
Simulation time 247421349361 ps
CPU time 2279.89 seconds
Started Jul 16 05:40:01 PM PDT 24
Finished Jul 16 06:18:03 PM PDT 24
Peak memory 273852 kb
Host smart-d45d92af-1bae-4164-8123-db13abc503ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058164519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3058164519
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1523336906
Short name T249
Test name
Test status
Simulation time 52987498938 ps
CPU time 1272.13 seconds
Started Jul 16 05:40:07 PM PDT 24
Finished Jul 16 06:01:20 PM PDT 24
Peak memory 285840 kb
Host smart-cf5f626c-c1c8-4c9b-8d98-2f0638565587
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523336906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1523336906
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1672796300
Short name T316
Test name
Test status
Simulation time 53911577784 ps
CPU time 432.79 seconds
Started Jul 16 05:40:13 PM PDT 24
Finished Jul 16 05:47:27 PM PDT 24
Peak memory 248132 kb
Host smart-ab34cbbd-45e6-4940-bd58-6443091f26da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672796300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1672796300
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.167692092
Short name T105
Test name
Test status
Simulation time 45986247866 ps
CPU time 1123.17 seconds
Started Jul 16 05:40:46 PM PDT 24
Finished Jul 16 05:59:32 PM PDT 24
Peak memory 289200 kb
Host smart-6ba1c911-a726-436d-a4af-795f020c2b92
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167692092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.167692092
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.926030603
Short name T137
Test name
Test status
Simulation time 1554496677 ps
CPU time 114.15 seconds
Started Jul 16 05:37:49 PM PDT 24
Finished Jul 16 05:39:53 PM PDT 24
Peak memory 257044 kb
Host smart-6ad823be-2548-4be0-ad3c-8feb6402bc8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=926030603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.926030603
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3483133313
Short name T10
Test name
Test status
Simulation time 53498273384 ps
CPU time 1160.35 seconds
Started Jul 16 05:39:27 PM PDT 24
Finished Jul 16 05:58:49 PM PDT 24
Peak memory 273704 kb
Host smart-8cde6ecc-6521-457b-8e1c-9a80c131c7ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483133313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3483133313
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3641213562
Short name T330
Test name
Test status
Simulation time 9599620 ps
CPU time 1.39 seconds
Started Jul 16 05:37:53 PM PDT 24
Finished Jul 16 05:38:01 PM PDT 24
Peak memory 237604 kb
Host smart-360ce4f9-7428-493e-80dc-db8d75f5edf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3641213562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3641213562
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2221572489
Short name T145
Test name
Test status
Simulation time 4304292645 ps
CPU time 608.45 seconds
Started Jul 16 05:37:37 PM PDT 24
Finished Jul 16 05:47:46 PM PDT 24
Peak memory 265288 kb
Host smart-353dd81e-ca2f-4e85-9f40-a715e9370324
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221572489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2221572489
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1728544103
Short name T219
Test name
Test status
Simulation time 82516173929 ps
CPU time 1135.71 seconds
Started Jul 16 05:39:00 PM PDT 24
Finished Jul 16 05:57:57 PM PDT 24
Peak memory 273208 kb
Host smart-6a52c5bd-9c96-401e-a025-254af7cd6785
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728544103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1728544103
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3778842110
Short name T90
Test name
Test status
Simulation time 8107170104 ps
CPU time 775.97 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 05:52:24 PM PDT 24
Peak memory 273160 kb
Host smart-5fc89e3c-fa71-4b44-88e4-a61ee60d9da3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778842110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3778842110
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.139267478
Short name T235
Test name
Test status
Simulation time 16664562029 ps
CPU time 920.64 seconds
Started Jul 16 05:39:37 PM PDT 24
Finished Jul 16 05:55:00 PM PDT 24
Peak memory 274008 kb
Host smart-13ef9c28-5136-4d7c-a7ad-fc4d4607a57f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139267478 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.139267478
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3269729915
Short name T55
Test name
Test status
Simulation time 67131837982 ps
CPU time 1555 seconds
Started Jul 16 05:39:46 PM PDT 24
Finished Jul 16 06:05:43 PM PDT 24
Peak memory 290300 kb
Host smart-ffccf840-f2da-4c21-ad38-b0031dde01a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269729915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3269729915
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2894810586
Short name T82
Test name
Test status
Simulation time 2182488626 ps
CPU time 230.58 seconds
Started Jul 16 05:39:44 PM PDT 24
Finished Jul 16 05:43:36 PM PDT 24
Peak memory 254392 kb
Host smart-4745c9f2-b051-4bca-b415-9985785f41b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894810586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2894810586
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3213814773
Short name T258
Test name
Test status
Simulation time 809002387 ps
CPU time 55.31 seconds
Started Jul 16 05:40:30 PM PDT 24
Finished Jul 16 05:41:26 PM PDT 24
Peak memory 256852 kb
Host smart-8271094d-332e-466a-b2d9-e19cb16438f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32138
14773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3213814773
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1184483829
Short name T264
Test name
Test status
Simulation time 1758519105 ps
CPU time 55.05 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 05:41:20 PM PDT 24
Peak memory 257408 kb
Host smart-98497786-bdea-4a9c-9bb0-5999d10a070f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11844
83829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1184483829
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3333686737
Short name T273
Test name
Test status
Simulation time 383596437 ps
CPU time 30.7 seconds
Started Jul 16 05:40:34 PM PDT 24
Finished Jul 16 05:41:06 PM PDT 24
Peak memory 248596 kb
Host smart-31467eb9-38ea-43e8-ac43-6d750ee8d2b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33336
86737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3333686737
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1320838169
Short name T100
Test name
Test status
Simulation time 32553300866 ps
CPU time 2076.09 seconds
Started Jul 16 05:41:06 PM PDT 24
Finished Jul 16 06:15:43 PM PDT 24
Peak memory 287340 kb
Host smart-9e7e2425-3c69-4828-8a97-7939ccda472f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320838169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1320838169
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2565626713
Short name T247
Test name
Test status
Simulation time 227073597154 ps
CPU time 3813.16 seconds
Started Jul 16 05:41:07 PM PDT 24
Finished Jul 16 06:44:42 PM PDT 24
Peak memory 283460 kb
Host smart-a66d693b-380a-45e4-8647-f7f3b3f68043
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565626713 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2565626713
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.198535528
Short name T253
Test name
Test status
Simulation time 8271804408 ps
CPU time 327.72 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 05:44:53 PM PDT 24
Peak memory 257592 kb
Host smart-deee4b97-5d3b-42f9-9d0a-8573ff390438
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198535528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.198535528
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3188988912
Short name T29
Test name
Test status
Simulation time 60626351382 ps
CPU time 3764.49 seconds
Started Jul 16 05:39:38 PM PDT 24
Finished Jul 16 06:42:25 PM PDT 24
Peak memory 289976 kb
Host smart-10485447-fc1d-46c0-9045-318f7b381569
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188988912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3188988912
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3510214055
Short name T127
Test name
Test status
Simulation time 1485588355 ps
CPU time 119.68 seconds
Started Jul 16 05:37:56 PM PDT 24
Finished Jul 16 05:39:59 PM PDT 24
Peak memory 265508 kb
Host smart-400c9d82-95ea-4ee7-b6bd-55429f4d21e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3510214055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3510214055
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2433772405
Short name T165
Test name
Test status
Simulation time 3701290900 ps
CPU time 73.63 seconds
Started Jul 16 05:37:54 PM PDT 24
Finished Jul 16 05:39:13 PM PDT 24
Peak memory 240596 kb
Host smart-48ac6ad2-31a1-4184-ae07-9d9bf0bc3f46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2433772405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2433772405
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.785269145
Short name T163
Test name
Test status
Simulation time 31379541 ps
CPU time 2.81 seconds
Started Jul 16 05:37:29 PM PDT 24
Finished Jul 16 05:37:32 PM PDT 24
Peak memory 238572 kb
Host smart-abdd19b8-690e-4b69-a73e-ff6b834b6022
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=785269145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.785269145
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2489296417
Short name T132
Test name
Test status
Simulation time 3888345860 ps
CPU time 406.93 seconds
Started Jul 16 05:37:57 PM PDT 24
Finished Jul 16 05:44:47 PM PDT 24
Peak memory 265444 kb
Host smart-244745e3-6d71-4202-837a-cd4dd03459c8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489296417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2489296417
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2535245040
Short name T164
Test name
Test status
Simulation time 167299319 ps
CPU time 3.67 seconds
Started Jul 16 05:37:46 PM PDT 24
Finished Jul 16 05:38:02 PM PDT 24
Peak memory 237084 kb
Host smart-c6dc1d9b-3fa7-4169-8967-708d9d9d6e0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2535245040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2535245040
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1100954289
Short name T169
Test name
Test status
Simulation time 62846121 ps
CPU time 4.46 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:37:42 PM PDT 24
Peak memory 236628 kb
Host smart-f180844b-a74a-441f-9333-e472410366e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1100954289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1100954289
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.991723443
Short name T168
Test name
Test status
Simulation time 458566936 ps
CPU time 35.86 seconds
Started Jul 16 05:37:46 PM PDT 24
Finished Jul 16 05:38:34 PM PDT 24
Peak memory 244760 kb
Host smart-faa7fedb-b625-4688-9286-d89ba29c6d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=991723443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.991723443
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1784421704
Short name T162
Test name
Test status
Simulation time 103836874 ps
CPU time 3.86 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:37:41 PM PDT 24
Peak memory 237596 kb
Host smart-a6548932-ea31-4246-9d9e-4a800c2c02be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1784421704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1784421704
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3074177354
Short name T171
Test name
Test status
Simulation time 1385965304 ps
CPU time 20.4 seconds
Started Jul 16 05:37:56 PM PDT 24
Finished Jul 16 05:38:20 PM PDT 24
Peak memory 240460 kb
Host smart-1a57dd53-7ce0-4b4c-8c95-8c6053cf7e02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3074177354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3074177354
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3297063155
Short name T140
Test name
Test status
Simulation time 3939268006 ps
CPU time 140.25 seconds
Started Jul 16 05:38:04 PM PDT 24
Finished Jul 16 05:40:25 PM PDT 24
Peak memory 265468 kb
Host smart-32239e19-d3f1-4e85-93dc-bd4b7f3d2722
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3297063155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3297063155
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1093374989
Short name T157
Test name
Test status
Simulation time 204954352 ps
CPU time 22.32 seconds
Started Jul 16 05:37:45 PM PDT 24
Finished Jul 16 05:38:19 PM PDT 24
Peak memory 240512 kb
Host smart-b88dbe98-255f-4b81-b33d-b4c466f3a2b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1093374989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1093374989
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2983836121
Short name T173
Test name
Test status
Simulation time 61800797 ps
CPU time 3.13 seconds
Started Jul 16 05:37:45 PM PDT 24
Finished Jul 16 05:37:52 PM PDT 24
Peak memory 236652 kb
Host smart-3c1a77b4-dc7e-4e6c-97fd-9706106c4359
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2983836121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2983836121
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1177408932
Short name T23
Test name
Test status
Simulation time 159851463 ps
CPU time 16.64 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 05:39:53 PM PDT 24
Peak memory 257324 kb
Host smart-d68d85db-b4aa-4177-84b2-94f77d26bc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11774
08932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1177408932
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3420923549
Short name T156
Test name
Test status
Simulation time 162421195 ps
CPU time 22.31 seconds
Started Jul 16 05:37:29 PM PDT 24
Finished Jul 16 05:37:52 PM PDT 24
Peak memory 240444 kb
Host smart-7f6065e8-3869-4889-9adf-2dde67abf262
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3420923549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3420923549
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1524664690
Short name T174
Test name
Test status
Simulation time 160520733 ps
CPU time 21.78 seconds
Started Jul 16 05:37:57 PM PDT 24
Finished Jul 16 05:38:22 PM PDT 24
Peak memory 240492 kb
Host smart-b5aa6a9f-e87a-4582-83aa-ff3e84912a98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1524664690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1524664690
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2127710440
Short name T175
Test name
Test status
Simulation time 235371048 ps
CPU time 3.86 seconds
Started Jul 16 05:37:51 PM PDT 24
Finished Jul 16 05:38:03 PM PDT 24
Peak memory 237824 kb
Host smart-90757f7d-d215-4ee9-8af7-6528c4eb7d51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2127710440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2127710440
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3847894919
Short name T170
Test name
Test status
Simulation time 355932984 ps
CPU time 2.51 seconds
Started Jul 16 05:38:06 PM PDT 24
Finished Jul 16 05:38:10 PM PDT 24
Peak memory 237964 kb
Host smart-bd948f2e-f1cd-4759-afca-328c5e149b19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3847894919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3847894919
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1892863116
Short name T172
Test name
Test status
Simulation time 311922927 ps
CPU time 23.17 seconds
Started Jul 16 05:38:05 PM PDT 24
Finished Jul 16 05:38:29 PM PDT 24
Peak memory 237696 kb
Host smart-cc2fe72d-0888-4df8-bb90-46c041867145
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1892863116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1892863116
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2890184659
Short name T167
Test name
Test status
Simulation time 43977238 ps
CPU time 3.86 seconds
Started Jul 16 05:38:02 PM PDT 24
Finished Jul 16 05:38:06 PM PDT 24
Peak memory 237564 kb
Host smart-7f372aa7-46f0-4621-bcb2-01434d2c2865
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2890184659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2890184659
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4185716396
Short name T166
Test name
Test status
Simulation time 2068725244 ps
CPU time 37.59 seconds
Started Jul 16 05:37:35 PM PDT 24
Finished Jul 16 05:38:14 PM PDT 24
Peak memory 237648 kb
Host smart-ba8ae4ec-e088-4be9-a2ce-f8ccd1507d95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4185716396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.4185716396
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1792746320
Short name T24
Test name
Test status
Simulation time 111926149598 ps
CPU time 2117.24 seconds
Started Jul 16 05:39:08 PM PDT 24
Finished Jul 16 06:14:27 PM PDT 24
Peak memory 288572 kb
Host smart-805382fe-c5c4-427f-9f6c-f0270ca1b806
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792746320 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1792746320
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.4002891349
Short name T191
Test name
Test status
Simulation time 1825414971 ps
CPU time 113.05 seconds
Started Jul 16 05:37:30 PM PDT 24
Finished Jul 16 05:39:25 PM PDT 24
Peak memory 240492 kb
Host smart-9ba7c889-f080-41d4-aaac-d88f0007c544
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4002891349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.4002891349
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1717293267
Short name T819
Test name
Test status
Simulation time 6808557179 ps
CPU time 88 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:39:05 PM PDT 24
Peak memory 240596 kb
Host smart-6601cf7f-ccc7-4d70-9a88-cc7c363cc945
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1717293267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1717293267
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2373981104
Short name T781
Test name
Test status
Simulation time 73822927 ps
CPU time 5.85 seconds
Started Jul 16 05:37:23 PM PDT 24
Finished Jul 16 05:37:30 PM PDT 24
Peak memory 240492 kb
Host smart-24e091d3-5cbb-400b-8fec-0a5cffdeed70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2373981104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2373981104
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2380012890
Short name T808
Test name
Test status
Simulation time 70273132 ps
CPU time 5.32 seconds
Started Jul 16 05:37:33 PM PDT 24
Finished Jul 16 05:37:39 PM PDT 24
Peak memory 239608 kb
Host smart-3e3258e4-f5b4-47b9-9747-c609345c15b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380012890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2380012890
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1444978698
Short name T734
Test name
Test status
Simulation time 95572982 ps
CPU time 4.8 seconds
Started Jul 16 05:37:31 PM PDT 24
Finished Jul 16 05:37:37 PM PDT 24
Peak memory 237608 kb
Host smart-d197c832-ef89-4077-9d61-3b59d0c3ae97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1444978698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1444978698
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1501925830
Short name T786
Test name
Test status
Simulation time 16962284 ps
CPU time 1.29 seconds
Started Jul 16 05:37:28 PM PDT 24
Finished Jul 16 05:37:30 PM PDT 24
Peak memory 237472 kb
Host smart-123f8c14-b44d-4985-8011-d0586a1fc93e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1501925830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1501925830
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2115632031
Short name T775
Test name
Test status
Simulation time 173892546 ps
CPU time 21.69 seconds
Started Jul 16 05:37:30 PM PDT 24
Finished Jul 16 05:37:53 PM PDT 24
Peak memory 248664 kb
Host smart-a9c78764-70e5-4ae0-8374-6f5d22f8cc01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2115632031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2115632031
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1010286534
Short name T135
Test name
Test status
Simulation time 6875470626 ps
CPU time 131.18 seconds
Started Jul 16 05:37:26 PM PDT 24
Finished Jul 16 05:39:38 PM PDT 24
Peak memory 265344 kb
Host smart-66cb2e89-a6d0-4b99-9766-dde2d358d74f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1010286534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1010286534
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2770758268
Short name T742
Test name
Test status
Simulation time 83978843 ps
CPU time 12.66 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:37:50 PM PDT 24
Peak memory 248836 kb
Host smart-7770239d-0128-4fa3-962b-e4d2f7b6a742
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2770758268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2770758268
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.308314286
Short name T760
Test name
Test status
Simulation time 517616546 ps
CPU time 67.34 seconds
Started Jul 16 05:37:38 PM PDT 24
Finished Jul 16 05:38:46 PM PDT 24
Peak memory 237600 kb
Host smart-71c0b4fd-afef-415b-aa89-0944eacd01a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=308314286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.308314286
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2954011835
Short name T751
Test name
Test status
Simulation time 1638006518 ps
CPU time 102.45 seconds
Started Jul 16 05:37:39 PM PDT 24
Finished Jul 16 05:39:22 PM PDT 24
Peak memory 240552 kb
Host smart-05318e60-1d36-49e0-857d-cbcf374543f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2954011835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2954011835
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.499332088
Short name T762
Test name
Test status
Simulation time 71430157 ps
CPU time 5.89 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:37:43 PM PDT 24
Peak memory 240528 kb
Host smart-58adfed2-2cd4-4bb1-98e1-4d7f99866b93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=499332088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.499332088
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1090809496
Short name T795
Test name
Test status
Simulation time 40539701 ps
CPU time 3.22 seconds
Started Jul 16 05:37:30 PM PDT 24
Finished Jul 16 05:37:35 PM PDT 24
Peak memory 239648 kb
Host smart-b0f714db-62fc-4a52-9cb5-fc277371da9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090809496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1090809496
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2304805241
Short name T739
Test name
Test status
Simulation time 35438510 ps
CPU time 5.51 seconds
Started Jul 16 05:37:31 PM PDT 24
Finished Jul 16 05:37:38 PM PDT 24
Peak memory 237456 kb
Host smart-3335795d-6ad8-4b8b-ba61-3b3c85ec48bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2304805241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2304805241
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1580090122
Short name T787
Test name
Test status
Simulation time 1250682493 ps
CPU time 21.45 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:37:59 PM PDT 24
Peak memory 240540 kb
Host smart-d5e8d80d-cb65-4cf7-ae5c-97b383c2fa09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1580090122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1580090122
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2113412157
Short name T141
Test name
Test status
Simulation time 2783686903 ps
CPU time 185.22 seconds
Started Jul 16 05:37:30 PM PDT 24
Finished Jul 16 05:40:37 PM PDT 24
Peak memory 267608 kb
Host smart-18652a2c-4aa0-450f-9920-ae7d807f63de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2113412157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2113412157
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.802550536
Short name T732
Test name
Test status
Simulation time 512417070 ps
CPU time 19.83 seconds
Started Jul 16 05:37:26 PM PDT 24
Finished Jul 16 05:37:46 PM PDT 24
Peak memory 254592 kb
Host smart-e5598eeb-71d4-4951-a1f3-38568f76a4a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=802550536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.802550536
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.831687329
Short name T796
Test name
Test status
Simulation time 124625672 ps
CPU time 5.21 seconds
Started Jul 16 05:37:53 PM PDT 24
Finished Jul 16 05:38:04 PM PDT 24
Peak memory 248752 kb
Host smart-5b72cdcb-70ef-429a-be16-128fab0eae22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831687329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.831687329
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2101832622
Short name T822
Test name
Test status
Simulation time 45449673 ps
CPU time 6.08 seconds
Started Jul 16 05:37:56 PM PDT 24
Finished Jul 16 05:38:06 PM PDT 24
Peak memory 237592 kb
Host smart-529c011f-ec9a-4081-aad7-a87f01d648bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2101832622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2101832622
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3803808645
Short name T763
Test name
Test status
Simulation time 1077876976 ps
CPU time 23.35 seconds
Started Jul 16 05:37:57 PM PDT 24
Finished Jul 16 05:38:24 PM PDT 24
Peak memory 245612 kb
Host smart-15d3b4d3-42ed-4162-bd1b-ef7ebdf47a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3803808645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3803808645
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4206362815
Short name T143
Test name
Test status
Simulation time 3446004460 ps
CPU time 135.65 seconds
Started Jul 16 05:37:56 PM PDT 24
Finished Jul 16 05:40:16 PM PDT 24
Peak memory 265408 kb
Host smart-488249a9-ef24-49dd-8107-54ee0512e1ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4206362815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.4206362815
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3371573737
Short name T772
Test name
Test status
Simulation time 180126436 ps
CPU time 13.16 seconds
Started Jul 16 05:37:54 PM PDT 24
Finished Jul 16 05:38:12 PM PDT 24
Peak memory 248808 kb
Host smart-3c076bdc-3ae5-481d-9498-b8d46e8fd5f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3371573737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3371573737
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3229699208
Short name T807
Test name
Test status
Simulation time 250214262 ps
CPU time 5.82 seconds
Started Jul 16 05:37:55 PM PDT 24
Finished Jul 16 05:38:05 PM PDT 24
Peak memory 240396 kb
Host smart-95d8468a-d73c-4878-bedd-acf16647b2d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229699208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3229699208
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1601522556
Short name T193
Test name
Test status
Simulation time 248551022 ps
CPU time 10.5 seconds
Started Jul 16 05:37:55 PM PDT 24
Finished Jul 16 05:38:10 PM PDT 24
Peak memory 237596 kb
Host smart-ae32ee77-3c11-45d4-ba08-b46882a6a959
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1601522556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1601522556
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1706683467
Short name T794
Test name
Test status
Simulation time 6384877 ps
CPU time 1.39 seconds
Started Jul 16 05:37:52 PM PDT 24
Finished Jul 16 05:38:01 PM PDT 24
Peak memory 237620 kb
Host smart-fa902e27-531e-4142-bf66-e1c49714bf4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1706683467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1706683467
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3009027416
Short name T752
Test name
Test status
Simulation time 1033792193 ps
CPU time 19.84 seconds
Started Jul 16 05:38:01 PM PDT 24
Finished Jul 16 05:38:21 PM PDT 24
Peak memory 245808 kb
Host smart-cf6c52ea-d34e-4129-89f3-69ba6e277dcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3009027416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3009027416
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1272872533
Short name T149
Test name
Test status
Simulation time 57408597154 ps
CPU time 1067.67 seconds
Started Jul 16 05:37:59 PM PDT 24
Finished Jul 16 05:55:49 PM PDT 24
Peak memory 265292 kb
Host smart-e9be8659-bd9f-4191-9f68-34838f65d017
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272872533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1272872533
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2621482191
Short name T767
Test name
Test status
Simulation time 379241023 ps
CPU time 13.16 seconds
Started Jul 16 05:37:54 PM PDT 24
Finished Jul 16 05:38:12 PM PDT 24
Peak memory 248708 kb
Host smart-a9a3efc4-e564-47fb-9aa5-51a50c8d9e70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2621482191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2621482191
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3228835886
Short name T756
Test name
Test status
Simulation time 189505424 ps
CPU time 8.65 seconds
Started Jul 16 05:37:53 PM PDT 24
Finished Jul 16 05:38:08 PM PDT 24
Peak memory 240296 kb
Host smart-632baca6-87e7-4653-afd4-78f7d4ae2b36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228835886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3228835886
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2140706299
Short name T810
Test name
Test status
Simulation time 66327953 ps
CPU time 3.9 seconds
Started Jul 16 05:37:57 PM PDT 24
Finished Jul 16 05:38:04 PM PDT 24
Peak memory 237572 kb
Host smart-22e3a59f-714b-4288-854f-490b168a8871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2140706299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2140706299
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2741897401
Short name T333
Test name
Test status
Simulation time 12987330 ps
CPU time 1.43 seconds
Started Jul 16 05:37:57 PM PDT 24
Finished Jul 16 05:38:02 PM PDT 24
Peak memory 236636 kb
Host smart-276cc85a-f823-421f-acb9-885c0eae25cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2741897401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2741897401
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.119136640
Short name T186
Test name
Test status
Simulation time 984283971 ps
CPU time 20.46 seconds
Started Jul 16 05:37:59 PM PDT 24
Finished Jul 16 05:38:21 PM PDT 24
Peak memory 245816 kb
Host smart-b76bf89c-5678-424e-9ac9-6aaa041db5db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=119136640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.119136640
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3340729870
Short name T152
Test name
Test status
Simulation time 829708989 ps
CPU time 102.84 seconds
Started Jul 16 05:37:56 PM PDT 24
Finished Jul 16 05:39:43 PM PDT 24
Peak memory 265220 kb
Host smart-807371f7-135a-4de2-a277-c904bbc3591b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3340729870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3340729870
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2149349400
Short name T147
Test name
Test status
Simulation time 30829249010 ps
CPU time 510.85 seconds
Started Jul 16 05:37:53 PM PDT 24
Finished Jul 16 05:46:30 PM PDT 24
Peak memory 265396 kb
Host smart-939ff9fe-fa94-4488-b79c-8f7cced6ec37
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149349400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2149349400
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.4272684652
Short name T790
Test name
Test status
Simulation time 141986232 ps
CPU time 11.75 seconds
Started Jul 16 05:37:52 PM PDT 24
Finished Jul 16 05:38:11 PM PDT 24
Peak memory 254740 kb
Host smart-4babf66a-0483-43f6-a6ff-f63db3029933
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4272684652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.4272684652
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.200117134
Short name T830
Test name
Test status
Simulation time 31087343 ps
CPU time 4.61 seconds
Started Jul 16 05:37:57 PM PDT 24
Finished Jul 16 05:38:05 PM PDT 24
Peak memory 241384 kb
Host smart-7301d0c9-a4a2-4b57-b7f9-0778c16d11de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200117134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.200117134
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1078676239
Short name T814
Test name
Test status
Simulation time 542913562 ps
CPU time 7.37 seconds
Started Jul 16 05:37:53 PM PDT 24
Finished Jul 16 05:38:07 PM PDT 24
Peak memory 237608 kb
Host smart-8f93a516-7e5b-42cf-b395-5c995ebedabe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1078676239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1078676239
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2606702400
Short name T188
Test name
Test status
Simulation time 372946911 ps
CPU time 19.69 seconds
Started Jul 16 05:37:53 PM PDT 24
Finished Jul 16 05:38:19 PM PDT 24
Peak memory 240516 kb
Host smart-d7a8aa90-371f-468e-ae1e-b2d6977c76bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2606702400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2606702400
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1141627620
Short name T123
Test name
Test status
Simulation time 42093581420 ps
CPU time 350.41 seconds
Started Jul 16 05:37:52 PM PDT 24
Finished Jul 16 05:43:50 PM PDT 24
Peak memory 265540 kb
Host smart-feaf0c04-fd78-4d24-899c-e05de66963c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1141627620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1141627620
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2802442390
Short name T748
Test name
Test status
Simulation time 117026744 ps
CPU time 8.82 seconds
Started Jul 16 05:38:00 PM PDT 24
Finished Jul 16 05:38:10 PM PDT 24
Peak memory 247448 kb
Host smart-488e88a7-3d03-49eb-aa84-cfb6bf6bc5cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2802442390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2802442390
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3670150539
Short name T718
Test name
Test status
Simulation time 56145681 ps
CPU time 8.64 seconds
Started Jul 16 05:38:01 PM PDT 24
Finished Jul 16 05:38:11 PM PDT 24
Peak memory 255168 kb
Host smart-4d611401-832a-459d-9f72-33cf9e86d02e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670150539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3670150539
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2116673773
Short name T728
Test name
Test status
Simulation time 185162365 ps
CPU time 3.29 seconds
Started Jul 16 05:38:05 PM PDT 24
Finished Jul 16 05:38:09 PM PDT 24
Peak memory 236484 kb
Host smart-760cd354-fe19-4840-b88a-b10edeb97df2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2116673773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2116673773
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3667072608
Short name T784
Test name
Test status
Simulation time 23764612 ps
CPU time 1.49 seconds
Started Jul 16 05:38:06 PM PDT 24
Finished Jul 16 05:38:08 PM PDT 24
Peak memory 237148 kb
Host smart-dea12123-7d20-4477-8ecd-c7e675dc6474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3667072608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3667072608
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4256672673
Short name T192
Test name
Test status
Simulation time 523632277 ps
CPU time 21.67 seconds
Started Jul 16 05:38:03 PM PDT 24
Finished Jul 16 05:38:26 PM PDT 24
Peak memory 248744 kb
Host smart-b3d57e83-65a6-45d8-8c2c-847c537c3bac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4256672673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.4256672673
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.919388774
Short name T150
Test name
Test status
Simulation time 2986057706 ps
CPU time 168.38 seconds
Started Jul 16 05:38:00 PM PDT 24
Finished Jul 16 05:40:50 PM PDT 24
Peak memory 265336 kb
Host smart-5e922b7c-c05a-49e5-b837-fe1bdafe992d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=919388774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.919388774
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1478179242
Short name T334
Test name
Test status
Simulation time 117156890457 ps
CPU time 1131.96 seconds
Started Jul 16 05:37:58 PM PDT 24
Finished Jul 16 05:56:53 PM PDT 24
Peak memory 265408 kb
Host smart-9b6044ee-3ded-4c3c-b538-75302c9350c8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478179242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1478179242
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2596180045
Short name T826
Test name
Test status
Simulation time 401350649 ps
CPU time 11.77 seconds
Started Jul 16 05:37:58 PM PDT 24
Finished Jul 16 05:38:12 PM PDT 24
Peak memory 248820 kb
Host smart-69ab538e-f04f-46c0-9dfb-6154c1ed861d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2596180045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2596180045
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1679955472
Short name T773
Test name
Test status
Simulation time 596408871 ps
CPU time 10 seconds
Started Jul 16 05:38:05 PM PDT 24
Finished Jul 16 05:38:16 PM PDT 24
Peak memory 240528 kb
Host smart-15f44655-3601-4087-9617-41af87a057a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679955472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1679955472
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3480241227
Short name T716
Test name
Test status
Simulation time 91971822 ps
CPU time 4.97 seconds
Started Jul 16 05:38:04 PM PDT 24
Finished Jul 16 05:38:10 PM PDT 24
Peak memory 240556 kb
Host smart-3852e55f-31cb-4b8e-9601-f27a722fbf7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3480241227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3480241227
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3736721447
Short name T793
Test name
Test status
Simulation time 357238329 ps
CPU time 23.14 seconds
Started Jul 16 05:38:08 PM PDT 24
Finished Jul 16 05:38:31 PM PDT 24
Peak memory 240472 kb
Host smart-d64348ab-964d-451c-8aff-58ebce197269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3736721447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3736721447
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.800152698
Short name T119
Test name
Test status
Simulation time 35691299145 ps
CPU time 683.6 seconds
Started Jul 16 05:38:03 PM PDT 24
Finished Jul 16 05:49:27 PM PDT 24
Peak memory 265428 kb
Host smart-49ff86c3-0356-47f6-8669-fedd4ec8a430
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800152698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.800152698
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1096686436
Short name T829
Test name
Test status
Simulation time 404507143 ps
CPU time 14.08 seconds
Started Jul 16 05:38:04 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 248692 kb
Host smart-6aaa7929-56c6-4ca4-8d4f-ee9fca528ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1096686436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1096686436
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3646584520
Short name T792
Test name
Test status
Simulation time 234996487 ps
CPU time 5.9 seconds
Started Jul 16 05:38:02 PM PDT 24
Finished Jul 16 05:38:09 PM PDT 24
Peak memory 240672 kb
Host smart-87042441-7242-492c-be48-d57eb8232d34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646584520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3646584520
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3900851574
Short name T754
Test name
Test status
Simulation time 116054741 ps
CPU time 5.19 seconds
Started Jul 16 05:38:09 PM PDT 24
Finished Jul 16 05:38:15 PM PDT 24
Peak memory 240416 kb
Host smart-92d2e589-8538-4464-8fca-116c448f112e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3900851574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3900851574
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3221894599
Short name T726
Test name
Test status
Simulation time 8533396 ps
CPU time 1.43 seconds
Started Jul 16 05:38:06 PM PDT 24
Finished Jul 16 05:38:09 PM PDT 24
Peak memory 237624 kb
Host smart-909d08b8-459d-4700-a377-15093368abac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3221894599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3221894599
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2014957647
Short name T190
Test name
Test status
Simulation time 90972567 ps
CPU time 13.23 seconds
Started Jul 16 05:38:06 PM PDT 24
Finished Jul 16 05:38:20 PM PDT 24
Peak memory 245768 kb
Host smart-67674f2a-8d67-41be-9511-6c1404f0d246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2014957647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2014957647
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.428118912
Short name T146
Test name
Test status
Simulation time 8973628672 ps
CPU time 713.01 seconds
Started Jul 16 05:38:02 PM PDT 24
Finished Jul 16 05:49:56 PM PDT 24
Peak memory 270260 kb
Host smart-c7f1c40f-9e31-402e-8350-1ded3a41306e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428118912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.428118912
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3445352363
Short name T766
Test name
Test status
Simulation time 84807566 ps
CPU time 6.14 seconds
Started Jul 16 05:38:06 PM PDT 24
Finished Jul 16 05:38:13 PM PDT 24
Peak memory 252072 kb
Host smart-ab530461-aedc-44de-8f17-aa7a94de8c73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3445352363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3445352363
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1771740659
Short name T774
Test name
Test status
Simulation time 166911481 ps
CPU time 11.54 seconds
Started Jul 16 05:38:08 PM PDT 24
Finished Jul 16 05:38:21 PM PDT 24
Peak memory 250832 kb
Host smart-b4b6cbf8-9e1b-4e2b-a8c5-dc25ac826f66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771740659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1771740659
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3346049922
Short name T714
Test name
Test status
Simulation time 19919580 ps
CPU time 3.61 seconds
Started Jul 16 05:38:05 PM PDT 24
Finished Jul 16 05:38:10 PM PDT 24
Peak memory 237564 kb
Host smart-d818a4f5-bf52-4f46-bccc-9bfe5e6c61db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3346049922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3346049922
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3260689998
Short name T813
Test name
Test status
Simulation time 15931618 ps
CPU time 1.32 seconds
Started Jul 16 05:38:07 PM PDT 24
Finished Jul 16 05:38:09 PM PDT 24
Peak memory 235620 kb
Host smart-92962a76-0126-4a66-9dda-d797a705ade3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3260689998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3260689998
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3566532347
Short name T723
Test name
Test status
Simulation time 1333298774 ps
CPU time 26.15 seconds
Started Jul 16 05:38:06 PM PDT 24
Finished Jul 16 05:38:33 PM PDT 24
Peak memory 245416 kb
Host smart-83ef11c5-a3d6-4a40-a90a-2fef0ed67312
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3566532347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3566532347
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2344336008
Short name T129
Test name
Test status
Simulation time 21467984809 ps
CPU time 171.73 seconds
Started Jul 16 05:38:06 PM PDT 24
Finished Jul 16 05:40:59 PM PDT 24
Peak memory 265424 kb
Host smart-a65e62b0-05c4-45e9-ae9a-d7e238a4bac5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2344336008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2344336008
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1155193315
Short name T815
Test name
Test status
Simulation time 359908680 ps
CPU time 11.25 seconds
Started Jul 16 05:38:03 PM PDT 24
Finished Jul 16 05:38:15 PM PDT 24
Peak memory 247792 kb
Host smart-4fbe9c81-41c4-4bf0-a549-59c0a179a56b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1155193315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1155193315
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1074997127
Short name T804
Test name
Test status
Simulation time 238549794 ps
CPU time 11.43 seconds
Started Jul 16 05:38:04 PM PDT 24
Finished Jul 16 05:38:16 PM PDT 24
Peak memory 254368 kb
Host smart-30b9e61e-23fa-4c71-8d64-a06a93dab87e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074997127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1074997127
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2096508629
Short name T719
Test name
Test status
Simulation time 62169274 ps
CPU time 5.34 seconds
Started Jul 16 05:38:04 PM PDT 24
Finished Jul 16 05:38:10 PM PDT 24
Peak memory 236632 kb
Host smart-02dfc333-b16e-4adb-a472-f8e994be1dd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2096508629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2096508629
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3783643572
Short name T738
Test name
Test status
Simulation time 38525871 ps
CPU time 1.39 seconds
Started Jul 16 05:38:02 PM PDT 24
Finished Jul 16 05:38:05 PM PDT 24
Peak memory 236576 kb
Host smart-9740d22a-717d-4729-8489-eb05406704dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3783643572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3783643572
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3003766397
Short name T725
Test name
Test status
Simulation time 983813905 ps
CPU time 23.16 seconds
Started Jul 16 05:38:08 PM PDT 24
Finished Jul 16 05:38:32 PM PDT 24
Peak memory 245644 kb
Host smart-c25534dd-4252-428d-bf1a-684925f24b11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3003766397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3003766397
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2445700877
Short name T134
Test name
Test status
Simulation time 13881672197 ps
CPU time 952 seconds
Started Jul 16 05:38:02 PM PDT 24
Finished Jul 16 05:53:55 PM PDT 24
Peak memory 272636 kb
Host smart-7f35be95-b2d8-4943-be0e-771b6e84eb72
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445700877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2445700877
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.430149015
Short name T747
Test name
Test status
Simulation time 94296143 ps
CPU time 12.4 seconds
Started Jul 16 05:38:04 PM PDT 24
Finished Jul 16 05:38:17 PM PDT 24
Peak memory 248120 kb
Host smart-3e0e8018-597f-42b8-992a-5a6b69a313b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=430149015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.430149015
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2781144296
Short name T803
Test name
Test status
Simulation time 636090300 ps
CPU time 19.8 seconds
Started Jul 16 05:38:04 PM PDT 24
Finished Jul 16 05:38:25 PM PDT 24
Peak memory 240432 kb
Host smart-4422cf35-8b96-4c14-b377-abf39c1ecdb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2781144296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2781144296
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2108945623
Short name T336
Test name
Test status
Simulation time 1251048647 ps
CPU time 9.59 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:26 PM PDT 24
Peak memory 240588 kb
Host smart-68976500-10c7-428a-88f2-ccb76a3a1e83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108945623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2108945623
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.222729571
Short name T818
Test name
Test status
Simulation time 408165841 ps
CPU time 10.39 seconds
Started Jul 16 05:38:16 PM PDT 24
Finished Jul 16 05:38:28 PM PDT 24
Peak memory 237616 kb
Host smart-d75c8b88-d7c6-46f1-9e66-8ac3dc5fa244
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=222729571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.222729571
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2199338897
Short name T821
Test name
Test status
Simulation time 50211741 ps
CPU time 1.4 seconds
Started Jul 16 05:38:13 PM PDT 24
Finished Jul 16 05:38:15 PM PDT 24
Peak memory 236624 kb
Host smart-0615c5ad-33b5-4798-b2b4-a81b79ee847f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2199338897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2199338897
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1046114675
Short name T727
Test name
Test status
Simulation time 719415554 ps
CPU time 49.47 seconds
Started Jul 16 05:38:18 PM PDT 24
Finished Jul 16 05:39:09 PM PDT 24
Peak memory 248692 kb
Host smart-22015588-1022-4e8c-8adc-465a4c752d2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1046114675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1046114675
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.648103292
Short name T130
Test name
Test status
Simulation time 2317800398 ps
CPU time 356.22 seconds
Started Jul 16 05:38:06 PM PDT 24
Finished Jul 16 05:44:03 PM PDT 24
Peak memory 265360 kb
Host smart-81c0a527-1b35-4887-914b-dd4cf55b22ab
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648103292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.648103292
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2098848465
Short name T712
Test name
Test status
Simulation time 456722855 ps
CPU time 8.82 seconds
Started Jul 16 05:38:04 PM PDT 24
Finished Jul 16 05:38:13 PM PDT 24
Peak memory 248780 kb
Host smart-e8d4d746-f60e-4794-be7e-fa3fad0d4fd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2098848465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2098848465
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1343912402
Short name T753
Test name
Test status
Simulation time 2159225666 ps
CPU time 128.18 seconds
Started Jul 16 05:37:39 PM PDT 24
Finished Jul 16 05:39:47 PM PDT 24
Peak memory 237552 kb
Host smart-5f83f432-cbfc-42fc-8b08-2839385d8757
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1343912402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1343912402
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2762303049
Short name T185
Test name
Test status
Simulation time 95137775696 ps
CPU time 352.02 seconds
Started Jul 16 05:37:45 PM PDT 24
Finished Jul 16 05:43:49 PM PDT 24
Peak memory 240584 kb
Host smart-2c7d3b8d-0d10-4ba8-a3fd-208de672798d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2762303049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2762303049
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.764005888
Short name T750
Test name
Test status
Simulation time 75905203 ps
CPU time 4.14 seconds
Started Jul 16 05:37:37 PM PDT 24
Finished Jul 16 05:37:42 PM PDT 24
Peak memory 248708 kb
Host smart-48397f76-7021-4753-8129-9e2f7d55af8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=764005888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.764005888
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.342411138
Short name T757
Test name
Test status
Simulation time 925579333 ps
CPU time 11.78 seconds
Started Jul 16 05:37:39 PM PDT 24
Finished Jul 16 05:37:51 PM PDT 24
Peak memory 243684 kb
Host smart-b9530893-4af9-461d-b468-32a73949ca2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342411138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.342411138
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.810432837
Short name T194
Test name
Test status
Simulation time 644089613 ps
CPU time 7.79 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:37:45 PM PDT 24
Peak memory 237612 kb
Host smart-960121b4-72b1-4d16-8996-9634e7523ee8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=810432837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.810432837
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2428490993
Short name T733
Test name
Test status
Simulation time 7911518 ps
CPU time 1.28 seconds
Started Jul 16 05:37:45 PM PDT 24
Finished Jul 16 05:37:58 PM PDT 24
Peak memory 237584 kb
Host smart-94a9785d-5718-430f-9037-5e935f95d375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2428490993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2428490993
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2265875578
Short name T724
Test name
Test status
Simulation time 2801628803 ps
CPU time 21.95 seconds
Started Jul 16 05:37:38 PM PDT 24
Finished Jul 16 05:38:01 PM PDT 24
Peak memory 240512 kb
Host smart-9b161fc5-20f0-4d1a-bcaf-fcf493868af2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2265875578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2265875578
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1190722197
Short name T139
Test name
Test status
Simulation time 42767044854 ps
CPU time 432.93 seconds
Started Jul 16 05:37:29 PM PDT 24
Finished Jul 16 05:44:43 PM PDT 24
Peak memory 265372 kb
Host smart-1b33c262-91d9-406e-8c75-f3c7ae4b92b6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190722197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1190722197
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1763932378
Short name T759
Test name
Test status
Simulation time 182049264 ps
CPU time 7.95 seconds
Started Jul 16 05:37:27 PM PDT 24
Finished Jul 16 05:37:36 PM PDT 24
Peak memory 249792 kb
Host smart-0f85d3cf-4336-4291-8327-e1bbdaf6adb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1763932378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1763932378
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3139602907
Short name T777
Test name
Test status
Simulation time 11443648 ps
CPU time 1.38 seconds
Started Jul 16 05:38:14 PM PDT 24
Finished Jul 16 05:38:16 PM PDT 24
Peak memory 237504 kb
Host smart-1ec248e2-2b72-460a-86fe-a816221afe3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3139602907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3139602907
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2607936720
Short name T802
Test name
Test status
Simulation time 13346192 ps
CPU time 1.73 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 235600 kb
Host smart-98d29caa-e458-46b6-a7b4-992b5e98f210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2607936720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2607936720
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4172040525
Short name T232
Test name
Test status
Simulation time 11764500 ps
CPU time 1.67 seconds
Started Jul 16 05:38:20 PM PDT 24
Finished Jul 16 05:38:23 PM PDT 24
Peak memory 236656 kb
Host smart-33651638-af58-4831-bd71-2c01ec33b34f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4172040525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4172040525
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3525246540
Short name T749
Test name
Test status
Simulation time 9691031 ps
CPU time 1.36 seconds
Started Jul 16 05:38:19 PM PDT 24
Finished Jul 16 05:38:22 PM PDT 24
Peak memory 236600 kb
Host smart-e3a80992-b311-4d29-9c15-4bdf741e100d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3525246540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3525246540
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1677445857
Short name T743
Test name
Test status
Simulation time 24303914 ps
CPU time 1.33 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 237436 kb
Host smart-489a172c-5f42-4b18-979f-4c384f3a8435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1677445857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1677445857
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1342025540
Short name T780
Test name
Test status
Simulation time 7346006 ps
CPU time 1.44 seconds
Started Jul 16 05:38:17 PM PDT 24
Finished Jul 16 05:38:20 PM PDT 24
Peak memory 235604 kb
Host smart-b62ac1f0-4059-4a3c-9afa-496ea84b95f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1342025540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1342025540
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1806446536
Short name T158
Test name
Test status
Simulation time 6144059 ps
CPU time 1.39 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 236560 kb
Host smart-b0cfd2fc-958a-4d7e-a90b-77f7db5c09a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1806446536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1806446536
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2298193080
Short name T745
Test name
Test status
Simulation time 6265606 ps
CPU time 1.49 seconds
Started Jul 16 05:38:20 PM PDT 24
Finished Jul 16 05:38:23 PM PDT 24
Peak memory 236644 kb
Host smart-3aed5020-f95e-4691-bd81-11db1360d7e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2298193080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2298193080
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.4155458515
Short name T791
Test name
Test status
Simulation time 12504443 ps
CPU time 1.67 seconds
Started Jul 16 05:38:14 PM PDT 24
Finished Jul 16 05:38:16 PM PDT 24
Peak memory 237552 kb
Host smart-74734a84-31c2-4804-ba2f-28bc532ee35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4155458515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.4155458515
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1762305643
Short name T159
Test name
Test status
Simulation time 10493953 ps
CPU time 1.37 seconds
Started Jul 16 05:38:14 PM PDT 24
Finished Jul 16 05:38:17 PM PDT 24
Peak memory 236672 kb
Host smart-a3f1f5a1-5c02-4b34-bf67-9f434df710c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1762305643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1762305643
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2957579563
Short name T761
Test name
Test status
Simulation time 13679634542 ps
CPU time 248.5 seconds
Started Jul 16 05:37:35 PM PDT 24
Finished Jul 16 05:41:44 PM PDT 24
Peak memory 240612 kb
Host smart-8858133d-5457-4972-a00e-211a2893a2b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2957579563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2957579563
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1230672053
Short name T827
Test name
Test status
Simulation time 95313449541 ps
CPU time 350.82 seconds
Started Jul 16 05:37:35 PM PDT 24
Finished Jul 16 05:43:27 PM PDT 24
Peak memory 240576 kb
Host smart-10b5a66f-0b0f-4024-8f09-7cc6f0fd0695
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1230672053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1230672053
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3872815636
Short name T736
Test name
Test status
Simulation time 155029334 ps
CPU time 5.59 seconds
Started Jul 16 05:37:34 PM PDT 24
Finished Jul 16 05:37:41 PM PDT 24
Peak memory 248724 kb
Host smart-2768ab93-53de-4e9a-b3e5-773719cba602
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3872815636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3872815636
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.366851548
Short name T805
Test name
Test status
Simulation time 52782398 ps
CPU time 5.31 seconds
Started Jul 16 05:37:37 PM PDT 24
Finished Jul 16 05:37:43 PM PDT 24
Peak memory 240532 kb
Host smart-aa2b651f-c7b1-45a9-8072-c33f6984377c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366851548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.366851548
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.201879061
Short name T731
Test name
Test status
Simulation time 70546676 ps
CPU time 5.46 seconds
Started Jul 16 05:37:49 PM PDT 24
Finished Jul 16 05:38:04 PM PDT 24
Peak memory 236528 kb
Host smart-4d2828ab-7e96-4a73-bc07-4d27d10047ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=201879061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.201879061
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2179125093
Short name T328
Test name
Test status
Simulation time 15654741 ps
CPU time 1.19 seconds
Started Jul 16 05:37:49 PM PDT 24
Finished Jul 16 05:38:00 PM PDT 24
Peak memory 237480 kb
Host smart-bc9f9778-4bb7-4231-89cb-3d713447dc09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2179125093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2179125093
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.904645345
Short name T820
Test name
Test status
Simulation time 171117470 ps
CPU time 20.31 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:37:57 PM PDT 24
Peak memory 244816 kb
Host smart-382a3107-b855-4754-b2e1-f95cd31a8997
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=904645345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.904645345
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2774868621
Short name T737
Test name
Test status
Simulation time 221740669 ps
CPU time 16.13 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:37:53 PM PDT 24
Peak memory 248816 kb
Host smart-f62e76d2-9703-4496-a13f-91a53d5fc278
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2774868621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2774868621
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1750999575
Short name T329
Test name
Test status
Simulation time 27607806 ps
CPU time 1.41 seconds
Started Jul 16 05:38:19 PM PDT 24
Finished Jul 16 05:38:22 PM PDT 24
Peak memory 237572 kb
Host smart-e5745fac-8a45-4550-9bd1-899915b104df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1750999575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1750999575
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2552178226
Short name T325
Test name
Test status
Simulation time 9113342 ps
CPU time 1.38 seconds
Started Jul 16 05:38:20 PM PDT 24
Finished Jul 16 05:38:23 PM PDT 24
Peak memory 235708 kb
Host smart-e00b6279-49b7-42cb-9a1a-7e13e040ffdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2552178226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2552178226
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1741358597
Short name T730
Test name
Test status
Simulation time 45879343 ps
CPU time 1.41 seconds
Started Jul 16 05:38:16 PM PDT 24
Finished Jul 16 05:38:19 PM PDT 24
Peak memory 237364 kb
Host smart-68f06eba-2f07-48f1-ba3e-9288d35cdbf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1741358597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1741358597
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1895165488
Short name T327
Test name
Test status
Simulation time 15369531 ps
CPU time 1.32 seconds
Started Jul 16 05:38:20 PM PDT 24
Finished Jul 16 05:38:23 PM PDT 24
Peak memory 235624 kb
Host smart-6dae1169-232e-4b56-9d59-200d21420575
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1895165488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1895165488
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1623972794
Short name T735
Test name
Test status
Simulation time 8431595 ps
CPU time 1.59 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 237612 kb
Host smart-10e3a7ba-2687-4a5f-b9c6-2be44cdecdd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1623972794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1623972794
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1798580706
Short name T769
Test name
Test status
Simulation time 9963647 ps
CPU time 1.36 seconds
Started Jul 16 05:38:17 PM PDT 24
Finished Jul 16 05:38:20 PM PDT 24
Peak memory 237556 kb
Host smart-4e438edb-57d9-425b-a17f-f088268c23a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1798580706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1798580706
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3867230538
Short name T331
Test name
Test status
Simulation time 11061585 ps
CPU time 1.31 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 236660 kb
Host smart-92b262f1-7027-4179-a9ca-a5ab41fce9d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3867230538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3867230538
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1913780804
Short name T776
Test name
Test status
Simulation time 10118791 ps
CPU time 1.63 seconds
Started Jul 16 05:38:19 PM PDT 24
Finished Jul 16 05:38:22 PM PDT 24
Peak memory 237572 kb
Host smart-16bb1b1a-2a33-4914-aacd-01cb59e916eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1913780804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1913780804
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1398859783
Short name T812
Test name
Test status
Simulation time 11182455 ps
CPU time 1.28 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 237572 kb
Host smart-6ce283f5-5618-45ef-a2c4-edb5f54539b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1398859783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1398859783
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1266668926
Short name T817
Test name
Test status
Simulation time 6264300 ps
CPU time 1.36 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 236576 kb
Host smart-4364517c-d6e8-46e9-9d5f-aafc2934981d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1266668926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1266668926
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3166821897
Short name T721
Test name
Test status
Simulation time 3223310208 ps
CPU time 103.89 seconds
Started Jul 16 05:37:45 PM PDT 24
Finished Jul 16 05:39:41 PM PDT 24
Peak memory 240584 kb
Host smart-6b41b9fa-8b66-48c5-8043-8438e29a514a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3166821897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3166821897
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3642803136
Short name T798
Test name
Test status
Simulation time 1724854223 ps
CPU time 216.15 seconds
Started Jul 16 05:37:49 PM PDT 24
Finished Jul 16 05:41:35 PM PDT 24
Peak memory 237472 kb
Host smart-00921358-5563-45fb-8216-122f2e348710
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3642803136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3642803136
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.414426246
Short name T801
Test name
Test status
Simulation time 110942465 ps
CPU time 8.55 seconds
Started Jul 16 05:37:49 PM PDT 24
Finished Jul 16 05:38:07 PM PDT 24
Peak memory 248620 kb
Host smart-a4383959-20fa-4ffc-ace0-1befe0dc4038
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=414426246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.414426246
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1363842002
Short name T809
Test name
Test status
Simulation time 247869248 ps
CPU time 9.36 seconds
Started Jul 16 05:37:37 PM PDT 24
Finished Jul 16 05:37:47 PM PDT 24
Peak memory 256608 kb
Host smart-e0814807-97e9-4cb5-86b3-021de6255be0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363842002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1363842002
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1002603418
Short name T785
Test name
Test status
Simulation time 64203252 ps
CPU time 4.8 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:37:42 PM PDT 24
Peak memory 240524 kb
Host smart-9e9759de-70d6-40ac-8a54-8aa02ce82027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1002603418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1002603418
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1004538714
Short name T811
Test name
Test status
Simulation time 7920986 ps
CPU time 1.45 seconds
Started Jul 16 05:37:33 PM PDT 24
Finished Jul 16 05:37:35 PM PDT 24
Peak memory 237612 kb
Host smart-d42daa40-ba05-4756-ba47-4ab7ba2b65a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1004538714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1004538714
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3064901235
Short name T722
Test name
Test status
Simulation time 499018609 ps
CPU time 17.85 seconds
Started Jul 16 05:37:37 PM PDT 24
Finished Jul 16 05:37:56 PM PDT 24
Peak memory 245796 kb
Host smart-e31ebb88-8307-487d-ba18-78aef7693f8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3064901235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3064901235
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3878414658
Short name T335
Test name
Test status
Simulation time 6033578070 ps
CPU time 591.72 seconds
Started Jul 16 05:37:36 PM PDT 24
Finished Jul 16 05:47:28 PM PDT 24
Peak memory 265476 kb
Host smart-43001863-5a4d-49ce-93ab-173a2de16e7c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878414658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3878414658
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1770454994
Short name T713
Test name
Test status
Simulation time 118460948 ps
CPU time 14.13 seconds
Started Jul 16 05:37:37 PM PDT 24
Finished Jul 16 05:37:52 PM PDT 24
Peak memory 254360 kb
Host smart-888ad4bf-49c7-49af-be8b-2b295b24eec7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1770454994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1770454994
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.526600181
Short name T764
Test name
Test status
Simulation time 29297522 ps
CPU time 1.35 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 237620 kb
Host smart-939de523-245b-4a37-b009-5d5e663653da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=526600181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.526600181
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3642733574
Short name T768
Test name
Test status
Simulation time 13820336 ps
CPU time 1.5 seconds
Started Jul 16 05:38:16 PM PDT 24
Finished Jul 16 05:38:19 PM PDT 24
Peak memory 237576 kb
Host smart-d9c4da3b-ab93-49ab-8652-e0d6b671aac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3642733574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3642733574
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1999543446
Short name T816
Test name
Test status
Simulation time 12195496 ps
CPU time 1.45 seconds
Started Jul 16 05:38:14 PM PDT 24
Finished Jul 16 05:38:16 PM PDT 24
Peak memory 236644 kb
Host smart-f5e15e3a-3e2d-4239-b4fb-28ac226ea334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1999543446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1999543446
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1469396533
Short name T729
Test name
Test status
Simulation time 7526538 ps
CPU time 1.51 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 237584 kb
Host smart-4c1d2352-9a06-4cb9-98e2-78c3a2e52f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1469396533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1469396533
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.935145732
Short name T828
Test name
Test status
Simulation time 6606027 ps
CPU time 1.52 seconds
Started Jul 16 05:38:18 PM PDT 24
Finished Jul 16 05:38:21 PM PDT 24
Peak memory 237624 kb
Host smart-63965d46-2f44-4aa2-a9c9-a55c7aa1201a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=935145732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.935145732
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1768396707
Short name T799
Test name
Test status
Simulation time 20682459 ps
CPU time 1.44 seconds
Started Jul 16 05:38:19 PM PDT 24
Finished Jul 16 05:38:22 PM PDT 24
Peak memory 236616 kb
Host smart-04e54001-5328-4c4f-95e2-8df49afe6e05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1768396707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1768396707
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1369323756
Short name T770
Test name
Test status
Simulation time 16337344 ps
CPU time 1.33 seconds
Started Jul 16 05:38:13 PM PDT 24
Finished Jul 16 05:38:15 PM PDT 24
Peak memory 237604 kb
Host smart-4c503c5e-3250-44ab-84c4-03232d9ff690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1369323756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1369323756
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1767585152
Short name T789
Test name
Test status
Simulation time 6446242 ps
CPU time 1.6 seconds
Started Jul 16 05:38:17 PM PDT 24
Finished Jul 16 05:38:20 PM PDT 24
Peak memory 236576 kb
Host smart-1605b76a-60ec-4c48-8b74-aeb5654f03a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1767585152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1767585152
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2926515927
Short name T244
Test name
Test status
Simulation time 23277459 ps
CPU time 1.93 seconds
Started Jul 16 05:38:15 PM PDT 24
Finished Jul 16 05:38:19 PM PDT 24
Peak memory 237620 kb
Host smart-626948c6-1792-4295-8ec6-4ba2bbe2d96d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2926515927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2926515927
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2095530664
Short name T717
Test name
Test status
Simulation time 16680078 ps
CPU time 1.33 seconds
Started Jul 16 05:38:14 PM PDT 24
Finished Jul 16 05:38:18 PM PDT 24
Peak memory 235564 kb
Host smart-a3f95206-4647-47c0-bc43-182cc3ba94d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2095530664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2095530664
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3305682660
Short name T779
Test name
Test status
Simulation time 83997211 ps
CPU time 5.34 seconds
Started Jul 16 05:37:37 PM PDT 24
Finished Jul 16 05:37:43 PM PDT 24
Peak memory 240372 kb
Host smart-64993f8e-1bfa-4faf-9729-c717929e5dae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305682660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3305682660
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.255310205
Short name T189
Test name
Test status
Simulation time 58339636 ps
CPU time 3.4 seconds
Started Jul 16 05:37:49 PM PDT 24
Finished Jul 16 05:38:02 PM PDT 24
Peak memory 240244 kb
Host smart-23d7f268-4848-4b92-bbc8-5e28dc71ade0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=255310205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.255310205
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3467689395
Short name T160
Test name
Test status
Simulation time 14785501 ps
CPU time 1.38 seconds
Started Jul 16 05:37:46 PM PDT 24
Finished Jul 16 05:38:00 PM PDT 24
Peak memory 236624 kb
Host smart-be3a9477-bf1c-4d64-b2f4-88754bba8bf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3467689395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3467689395
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1998215006
Short name T788
Test name
Test status
Simulation time 376209863 ps
CPU time 26.33 seconds
Started Jul 16 05:37:49 PM PDT 24
Finished Jul 16 05:38:25 PM PDT 24
Peak memory 245504 kb
Host smart-d0020b81-7129-4d05-88ed-fc4ec0bb0488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1998215006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1998215006
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1993308414
Short name T243
Test name
Test status
Simulation time 1095335438 ps
CPU time 18.57 seconds
Started Jul 16 05:37:46 PM PDT 24
Finished Jul 16 05:38:17 PM PDT 24
Peak memory 254816 kb
Host smart-0f2bc89b-6cbd-4a10-8585-912c7221b3fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1993308414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1993308414
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2506831182
Short name T744
Test name
Test status
Simulation time 80320721 ps
CPU time 6.31 seconds
Started Jul 16 05:37:48 PM PDT 24
Finished Jul 16 05:38:05 PM PDT 24
Peak memory 240060 kb
Host smart-c74be638-5f00-4cb6-9fc7-7ce918660e25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506831182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2506831182
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3105263794
Short name T783
Test name
Test status
Simulation time 154041243 ps
CPU time 5.08 seconds
Started Jul 16 05:37:46 PM PDT 24
Finished Jul 16 05:38:04 PM PDT 24
Peak memory 239504 kb
Host smart-1614d3e0-bf5c-44c6-b731-2eeace48bb3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3105263794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3105263794
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1455748177
Short name T797
Test name
Test status
Simulation time 23258425 ps
CPU time 1.55 seconds
Started Jul 16 05:37:46 PM PDT 24
Finished Jul 16 05:38:00 PM PDT 24
Peak memory 236612 kb
Host smart-401723fb-7d3b-429e-99f3-dc1f34edc50a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1455748177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1455748177
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2713258524
Short name T741
Test name
Test status
Simulation time 2675057531 ps
CPU time 45.46 seconds
Started Jul 16 05:37:45 PM PDT 24
Finished Jul 16 05:38:42 PM PDT 24
Peak memory 245880 kb
Host smart-0310c813-4402-434c-b6f7-0447e00cd628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2713258524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2713258524
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3185009841
Short name T153
Test name
Test status
Simulation time 2136490360 ps
CPU time 276.2 seconds
Started Jul 16 05:37:38 PM PDT 24
Finished Jul 16 05:42:15 PM PDT 24
Peak memory 265244 kb
Host smart-13babb38-50d1-4c00-9381-1ba23350dada
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185009841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3185009841
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.874153600
Short name T778
Test name
Test status
Simulation time 686527637 ps
CPU time 11.36 seconds
Started Jul 16 05:37:33 PM PDT 24
Finished Jul 16 05:37:45 PM PDT 24
Peak memory 251536 kb
Host smart-bb269136-4309-4644-8262-dfca23b02667
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=874153600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.874153600
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1129963894
Short name T823
Test name
Test status
Simulation time 55707129 ps
CPU time 8.31 seconds
Started Jul 16 05:37:46 PM PDT 24
Finished Jul 16 05:38:07 PM PDT 24
Peak memory 256692 kb
Host smart-0c4eaca7-2a18-433e-a72c-907bdb246b34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129963894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1129963894
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1167214095
Short name T782
Test name
Test status
Simulation time 126938196 ps
CPU time 8.96 seconds
Started Jul 16 05:37:50 PM PDT 24
Finished Jul 16 05:38:08 PM PDT 24
Peak memory 240504 kb
Host smart-9c5d4a21-745d-4f8c-b2da-03ef19e8fc5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1167214095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1167214095
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.569320160
Short name T831
Test name
Test status
Simulation time 11899225 ps
CPU time 1.31 seconds
Started Jul 16 05:37:45 PM PDT 24
Finished Jul 16 05:37:58 PM PDT 24
Peak memory 237616 kb
Host smart-13008360-c4f1-46e7-8b7b-409ba959e5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=569320160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.569320160
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1215270998
Short name T187
Test name
Test status
Simulation time 610017455 ps
CPU time 42.09 seconds
Started Jul 16 05:37:50 PM PDT 24
Finished Jul 16 05:38:41 PM PDT 24
Peak memory 244852 kb
Host smart-15da80bc-9489-4d49-9d7e-c6e56c8d8ae8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1215270998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1215270998
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3913718529
Short name T118
Test name
Test status
Simulation time 4606853577 ps
CPU time 291.67 seconds
Started Jul 16 05:37:45 PM PDT 24
Finished Jul 16 05:42:50 PM PDT 24
Peak memory 272908 kb
Host smart-c3d6921e-38fd-4f7f-993a-d9b23312901f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3913718529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3913718529
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.227268530
Short name T154
Test name
Test status
Simulation time 2698034152 ps
CPU time 306.19 seconds
Started Jul 16 05:37:46 PM PDT 24
Finished Jul 16 05:43:05 PM PDT 24
Peak memory 269880 kb
Host smart-eae1278c-6f91-4b5f-b93a-f2fdb1cde48c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227268530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.227268530
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4190754565
Short name T824
Test name
Test status
Simulation time 166739851 ps
CPU time 11.27 seconds
Started Jul 16 05:37:44 PM PDT 24
Finished Jul 16 05:37:56 PM PDT 24
Peak memory 248820 kb
Host smart-7824137e-d5b4-4dd2-81d0-8972205a2264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4190754565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.4190754565
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2641364766
Short name T746
Test name
Test status
Simulation time 866418248 ps
CPU time 5.76 seconds
Started Jul 16 05:37:45 PM PDT 24
Finished Jul 16 05:38:01 PM PDT 24
Peak memory 240604 kb
Host smart-31fb5339-f24b-453f-8505-ec412777e917
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641364766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2641364766
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3583531137
Short name T825
Test name
Test status
Simulation time 35678819 ps
CPU time 3.23 seconds
Started Jul 16 05:37:48 PM PDT 24
Finished Jul 16 05:38:02 PM PDT 24
Peak memory 240464 kb
Host smart-02dd3be6-5b11-4a4a-bd8f-9d043055d677
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3583531137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3583531137
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.266995615
Short name T806
Test name
Test status
Simulation time 39033100 ps
CPU time 1.44 seconds
Started Jul 16 05:37:44 PM PDT 24
Finished Jul 16 05:37:46 PM PDT 24
Peak memory 237504 kb
Host smart-13d09491-536a-4515-a0d6-2bebc484d48f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=266995615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.266995615
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.662296533
Short name T800
Test name
Test status
Simulation time 2785946500 ps
CPU time 50.08 seconds
Started Jul 16 05:37:46 PM PDT 24
Finished Jul 16 05:38:49 PM PDT 24
Peak memory 245940 kb
Host smart-7c5dc0c4-6b80-4a54-8213-a3f00244c965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=662296533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.662296533
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2288526819
Short name T120
Test name
Test status
Simulation time 42047392465 ps
CPU time 397.82 seconds
Started Jul 16 05:37:49 PM PDT 24
Finished Jul 16 05:44:37 PM PDT 24
Peak memory 265468 kb
Host smart-6831edc1-6474-482f-808d-a449ed842b49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2288526819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2288526819
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.281749865
Short name T771
Test name
Test status
Simulation time 220656850 ps
CPU time 4.81 seconds
Started Jul 16 05:37:45 PM PDT 24
Finished Jul 16 05:38:03 PM PDT 24
Peak memory 251796 kb
Host smart-2382382e-29b4-4292-a93d-f482b9775604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=281749865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.281749865
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.956092870
Short name T715
Test name
Test status
Simulation time 131551790 ps
CPU time 9.2 seconds
Started Jul 16 05:37:52 PM PDT 24
Finished Jul 16 05:38:08 PM PDT 24
Peak memory 253176 kb
Host smart-98c25e86-596a-49fa-85cb-adfcf4931274
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956092870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.956092870
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.907221291
Short name T765
Test name
Test status
Simulation time 53321348 ps
CPU time 4.53 seconds
Started Jul 16 05:37:47 PM PDT 24
Finished Jul 16 05:38:03 PM PDT 24
Peak memory 237596 kb
Host smart-f8946342-b9d6-4faf-b310-b8c10ecad75a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=907221291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.907221291
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3667025751
Short name T758
Test name
Test status
Simulation time 14682032 ps
CPU time 1.69 seconds
Started Jul 16 05:37:50 PM PDT 24
Finished Jul 16 05:38:01 PM PDT 24
Peak memory 236536 kb
Host smart-bb0c7e62-b09d-43cf-bb02-79d009f0e8b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3667025751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3667025751
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3616601600
Short name T720
Test name
Test status
Simulation time 162861901 ps
CPU time 20.47 seconds
Started Jul 16 05:37:54 PM PDT 24
Finished Jul 16 05:38:20 PM PDT 24
Peak memory 248712 kb
Host smart-a868e643-61c2-476a-bd44-fd2b9c52c63a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3616601600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3616601600
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3464691125
Short name T133
Test name
Test status
Simulation time 1749949956 ps
CPU time 227.65 seconds
Started Jul 16 05:37:45 PM PDT 24
Finished Jul 16 05:41:42 PM PDT 24
Peak memory 265372 kb
Host smart-b0869d9e-46fa-4c93-99fd-003ce128912f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3464691125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3464691125
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1949107494
Short name T144
Test name
Test status
Simulation time 18320601204 ps
CPU time 504.26 seconds
Started Jul 16 05:37:49 PM PDT 24
Finished Jul 16 05:46:23 PM PDT 24
Peak memory 270616 kb
Host smart-6c64fba3-cbee-4d25-a9d0-ef15592f3e65
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949107494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1949107494
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1818581146
Short name T740
Test name
Test status
Simulation time 587103306 ps
CPU time 9.5 seconds
Started Jul 16 05:37:49 PM PDT 24
Finished Jul 16 05:38:09 PM PDT 24
Peak memory 248828 kb
Host smart-3427f539-ca68-416b-aba4-1c6c3d18a221
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1818581146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1818581146
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2254047649
Short name T195
Test name
Test status
Simulation time 143893976 ps
CPU time 2.27 seconds
Started Jul 16 05:37:47 PM PDT 24
Finished Jul 16 05:38:01 PM PDT 24
Peak memory 237456 kb
Host smart-2f09efa8-6a16-4c44-b3a4-45ee36a6f4d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2254047649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2254047649
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1890296979
Short name T116
Test name
Test status
Simulation time 30906839164 ps
CPU time 1814.89 seconds
Started Jul 16 05:38:58 PM PDT 24
Finished Jul 16 06:09:14 PM PDT 24
Peak memory 273940 kb
Host smart-3c84592a-f539-4929-999c-c280f1f27885
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890296979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1890296979
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2757774455
Short name T552
Test name
Test status
Simulation time 937981240 ps
CPU time 12.83 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 05:39:28 PM PDT 24
Peak memory 249220 kb
Host smart-3f6ffb67-bfcb-4781-bab3-9620ad638d99
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2757774455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2757774455
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.395601020
Short name T688
Test name
Test status
Simulation time 6094435955 ps
CPU time 146.03 seconds
Started Jul 16 05:39:01 PM PDT 24
Finished Jul 16 05:41:28 PM PDT 24
Peak memory 257532 kb
Host smart-d913d258-5dba-486b-a5d5-05be8c92e777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39560
1020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.395601020
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3267582256
Short name T659
Test name
Test status
Simulation time 276179088 ps
CPU time 4.07 seconds
Started Jul 16 05:39:00 PM PDT 24
Finished Jul 16 05:39:05 PM PDT 24
Peak memory 249716 kb
Host smart-5fa33dea-0838-4491-875c-c4be913f1a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32675
82256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3267582256
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1098160316
Short name T436
Test name
Test status
Simulation time 30361313799 ps
CPU time 1454.4 seconds
Started Jul 16 05:39:04 PM PDT 24
Finished Jul 16 06:03:19 PM PDT 24
Peak memory 273328 kb
Host smart-586c694b-bedb-4dac-a4e1-bb28a214a8ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098160316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1098160316
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.348010255
Short name T562
Test name
Test status
Simulation time 25952290190 ps
CPU time 562.57 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 05:48:22 PM PDT 24
Peak memory 249360 kb
Host smart-b0a56227-45a4-40d3-8b19-b71fdf2e00d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348010255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.348010255
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.438959291
Short name T487
Test name
Test status
Simulation time 2561754658 ps
CPU time 44.45 seconds
Started Jul 16 05:39:10 PM PDT 24
Finished Jul 16 05:39:56 PM PDT 24
Peak memory 256964 kb
Host smart-8bc6db44-2d40-4420-aa74-1ffd138b7219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43895
9291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.438959291
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.4156523627
Short name T545
Test name
Test status
Simulation time 956024063 ps
CPU time 28.85 seconds
Started Jul 16 05:39:01 PM PDT 24
Finished Jul 16 05:39:30 PM PDT 24
Peak memory 255632 kb
Host smart-f9f27f8f-23bb-43af-a4c0-9ddcb8912e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41565
23627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4156523627
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.339738843
Short name T5
Test name
Test status
Simulation time 413404680 ps
CPU time 13.25 seconds
Started Jul 16 05:39:03 PM PDT 24
Finished Jul 16 05:39:17 PM PDT 24
Peak memory 267380 kb
Host smart-52160fea-877d-4b6f-8832-e6f9015778f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=339738843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.339738843
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1071828945
Short name T112
Test name
Test status
Simulation time 582122551 ps
CPU time 39.13 seconds
Started Jul 16 05:39:00 PM PDT 24
Finished Jul 16 05:39:40 PM PDT 24
Peak memory 248812 kb
Host smart-0630cd2a-a351-4612-9240-a75944c71bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10718
28945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1071828945
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3463015957
Short name T427
Test name
Test status
Simulation time 1220390487 ps
CPU time 43.9 seconds
Started Jul 16 05:39:00 PM PDT 24
Finished Jul 16 05:39:45 PM PDT 24
Peak memory 257444 kb
Host smart-10c649c2-d387-41ee-b02a-ccc16b5226d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34630
15957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3463015957
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3558991267
Short name T266
Test name
Test status
Simulation time 35623309809 ps
CPU time 872.84 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 05:53:33 PM PDT 24
Peak memory 270836 kb
Host smart-5439fcd9-e88f-4601-81dc-82ef1bcc2746
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558991267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3558991267
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2883033599
Short name T109
Test name
Test status
Simulation time 62807247054 ps
CPU time 1584.5 seconds
Started Jul 16 05:39:00 PM PDT 24
Finished Jul 16 06:05:26 PM PDT 24
Peak memory 290356 kb
Host smart-ee92cc95-899b-4bfe-92ad-fadc2d4ebca0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883033599 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2883033599
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3125002524
Short name T199
Test name
Test status
Simulation time 22546062 ps
CPU time 2.85 seconds
Started Jul 16 05:39:01 PM PDT 24
Finished Jul 16 05:39:04 PM PDT 24
Peak memory 249492 kb
Host smart-c454b811-3edc-4ac0-9660-8d483687bc21
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3125002524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3125002524
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.940167052
Short name T478
Test name
Test status
Simulation time 12153680533 ps
CPU time 1463.22 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 06:03:24 PM PDT 24
Peak memory 290020 kb
Host smart-7bf02587-31ec-45fe-9f00-827b43441a06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940167052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.940167052
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3947952478
Short name T355
Test name
Test status
Simulation time 5408254639 ps
CPU time 60.46 seconds
Started Jul 16 05:39:01 PM PDT 24
Finished Jul 16 05:40:02 PM PDT 24
Peak memory 249292 kb
Host smart-54794017-77ed-40ef-9946-688786e0b2bb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3947952478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3947952478
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1280985763
Short name T666
Test name
Test status
Simulation time 3570398803 ps
CPU time 71.2 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 05:40:11 PM PDT 24
Peak memory 256736 kb
Host smart-9c759cd0-114a-45b5-bca0-c6f2472cc603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12809
85763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1280985763
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3312511074
Short name T485
Test name
Test status
Simulation time 611382010 ps
CPU time 14.37 seconds
Started Jul 16 05:38:58 PM PDT 24
Finished Jul 16 05:39:13 PM PDT 24
Peak memory 249232 kb
Host smart-be8810a5-5d21-4400-a5a7-8219ad592343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33125
11074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3312511074
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.4062891013
Short name T309
Test name
Test status
Simulation time 39279819859 ps
CPU time 1340.35 seconds
Started Jul 16 05:39:00 PM PDT 24
Finished Jul 16 06:01:21 PM PDT 24
Peak memory 273876 kb
Host smart-b803ee17-a204-4e13-8ad1-686a468716be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062891013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.4062891013
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2538129487
Short name T424
Test name
Test status
Simulation time 50946159423 ps
CPU time 1171.13 seconds
Started Jul 16 05:38:58 PM PDT 24
Finished Jul 16 05:58:29 PM PDT 24
Peak memory 273840 kb
Host smart-f3b42c0c-5e53-495a-b5d0-24d3bfc7f390
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538129487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2538129487
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2266602050
Short name T308
Test name
Test status
Simulation time 17614928966 ps
CPU time 351.15 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 05:44:51 PM PDT 24
Peak memory 249292 kb
Host smart-1049d4c9-e8ee-42a5-9e1b-4f932c8b0220
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266602050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2266602050
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1714701110
Short name T695
Test name
Test status
Simulation time 129285318 ps
CPU time 4.79 seconds
Started Jul 16 05:39:04 PM PDT 24
Finished Jul 16 05:39:09 PM PDT 24
Peak memory 249276 kb
Host smart-4c567099-9ab0-4db8-bd9e-6f80480723fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17147
01110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1714701110
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3838657307
Short name T649
Test name
Test status
Simulation time 10869926986 ps
CPU time 40.55 seconds
Started Jul 16 05:38:56 PM PDT 24
Finished Jul 16 05:39:37 PM PDT 24
Peak memory 249048 kb
Host smart-b077e50e-3e18-48d9-b199-a7158a9c2833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38386
57307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3838657307
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3663791808
Short name T40
Test name
Test status
Simulation time 1720187679 ps
CPU time 25.29 seconds
Started Jul 16 05:38:57 PM PDT 24
Finished Jul 16 05:39:23 PM PDT 24
Peak memory 270536 kb
Host smart-4563a72b-51de-4d9e-bba1-26f78f5c062d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3663791808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3663791808
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1712057027
Short name T86
Test name
Test status
Simulation time 1872756538 ps
CPU time 37.76 seconds
Started Jul 16 05:39:06 PM PDT 24
Finished Jul 16 05:39:44 PM PDT 24
Peak memory 249836 kb
Host smart-9f0eefc7-25f3-415d-a5d1-7715e3d9c712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17120
57027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1712057027
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1384893975
Short name T634
Test name
Test status
Simulation time 2740589615 ps
CPU time 70.8 seconds
Started Jul 16 05:38:58 PM PDT 24
Finished Jul 16 05:40:10 PM PDT 24
Peak memory 257524 kb
Host smart-4e2cb334-8125-4d03-8b63-31a24a622641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13848
93975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1384893975
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.4212009031
Short name T575
Test name
Test status
Simulation time 118344293245 ps
CPU time 3405.35 seconds
Started Jul 16 05:38:59 PM PDT 24
Finished Jul 16 06:35:45 PM PDT 24
Peak memory 290316 kb
Host smart-22012431-ade2-4e31-90ba-4f069ad6faf1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212009031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.4212009031
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.2970662465
Short name T52
Test name
Test status
Simulation time 72783206289 ps
CPU time 1855.59 seconds
Started Jul 16 05:39:02 PM PDT 24
Finished Jul 16 06:09:59 PM PDT 24
Peak memory 287728 kb
Host smart-40a03ee3-779c-4feb-a801-9be0437fc7eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970662465 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2970662465
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.4280141599
Short name T381
Test name
Test status
Simulation time 45131123704 ps
CPU time 2624.92 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 06:23:14 PM PDT 24
Peak memory 289396 kb
Host smart-3b974f68-2711-414f-b3fa-af985f5bee71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280141599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.4280141599
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3811021331
Short name T367
Test name
Test status
Simulation time 498668158 ps
CPU time 12.25 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 05:39:41 PM PDT 24
Peak memory 249160 kb
Host smart-41105417-cb91-45b2-8ac2-5e9c84024a9f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3811021331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3811021331
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3077013776
Short name T242
Test name
Test status
Simulation time 5005565051 ps
CPU time 35.93 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 05:40:01 PM PDT 24
Peak memory 256976 kb
Host smart-954936e6-533c-4f34-a4f8-d4976904a0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30770
13776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3077013776
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.507248662
Short name T383
Test name
Test status
Simulation time 350958382 ps
CPU time 27.96 seconds
Started Jul 16 05:39:21 PM PDT 24
Finished Jul 16 05:39:50 PM PDT 24
Peak memory 256728 kb
Host smart-385b074f-0c74-42b8-821f-716434a5365f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50724
8662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.507248662
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.92609801
Short name T643
Test name
Test status
Simulation time 39822133466 ps
CPU time 2193.46 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 06:16:02 PM PDT 24
Peak memory 272996 kb
Host smart-6aaba2d2-75f2-43ba-9401-58864fd49255
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92609801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.92609801
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3481141705
Short name T539
Test name
Test status
Simulation time 12139541937 ps
CPU time 85.21 seconds
Started Jul 16 05:39:25 PM PDT 24
Finished Jul 16 05:40:52 PM PDT 24
Peak memory 255800 kb
Host smart-30443c21-62b8-48a2-8492-48938da6a9de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481141705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3481141705
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2378937338
Short name T526
Test name
Test status
Simulation time 94351780 ps
CPU time 5.16 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 05:39:30 PM PDT 24
Peak memory 249184 kb
Host smart-2683828b-88f2-4566-99ad-4c9add6c0538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23789
37338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2378937338
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2543225562
Short name T633
Test name
Test status
Simulation time 302607197 ps
CPU time 6.9 seconds
Started Jul 16 05:39:20 PM PDT 24
Finished Jul 16 05:39:29 PM PDT 24
Peak memory 248496 kb
Host smart-e9a23702-d971-4956-9837-0b59efee61fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25432
25562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2543225562
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3585173480
Short name T269
Test name
Test status
Simulation time 182633000 ps
CPU time 5.62 seconds
Started Jul 16 05:39:20 PM PDT 24
Finished Jul 16 05:39:27 PM PDT 24
Peak memory 249276 kb
Host smart-692baed1-8a5a-4e95-8907-e8a4d0db982a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35851
73480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3585173480
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3528197686
Short name T655
Test name
Test status
Simulation time 48997261 ps
CPU time 4.55 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 05:39:31 PM PDT 24
Peak memory 249260 kb
Host smart-ecc9d602-1645-4723-aa73-1ba6f106502e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35281
97686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3528197686
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1436412826
Short name T620
Test name
Test status
Simulation time 15241951095 ps
CPU time 1482.64 seconds
Started Jul 16 05:39:25 PM PDT 24
Finished Jul 16 06:04:10 PM PDT 24
Peak memory 290316 kb
Host smart-71cffbed-cb71-4fcf-8dd4-7fb582ed5dd3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436412826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1436412826
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3453093716
Short name T501
Test name
Test status
Simulation time 25111376283 ps
CPU time 1712.81 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 06:07:57 PM PDT 24
Peak memory 290048 kb
Host smart-8e103b38-df8a-4330-8a9f-8938154469f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453093716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3453093716
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3199809657
Short name T352
Test name
Test status
Simulation time 1438205220 ps
CPU time 14.37 seconds
Started Jul 16 05:39:30 PM PDT 24
Finished Jul 16 05:39:45 PM PDT 24
Peak memory 249168 kb
Host smart-d95c019d-7755-450b-a131-701c9804dcc3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3199809657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3199809657
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2460459890
Short name T388
Test name
Test status
Simulation time 745877811 ps
CPU time 18.15 seconds
Started Jul 16 05:39:21 PM PDT 24
Finished Jul 16 05:39:40 PM PDT 24
Peak memory 256608 kb
Host smart-1eb5bcf6-529b-4cd7-bf9d-d38f48d028a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24604
59890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2460459890
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3499875776
Short name T37
Test name
Test status
Simulation time 793800403 ps
CPU time 29.01 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 05:39:55 PM PDT 24
Peak memory 256704 kb
Host smart-0996b00a-6f54-4a5d-9cda-ca1cdb4a5e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34998
75776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3499875776
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2326162252
Short name T612
Test name
Test status
Simulation time 20605061450 ps
CPU time 1291.77 seconds
Started Jul 16 05:39:29 PM PDT 24
Finished Jul 16 06:01:02 PM PDT 24
Peak memory 273612 kb
Host smart-f80fee00-28ac-4447-b0be-fc9cbcd5d8dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326162252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2326162252
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.666930296
Short name T697
Test name
Test status
Simulation time 35033818866 ps
CPU time 354.44 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 05:45:22 PM PDT 24
Peak memory 249392 kb
Host smart-9af24d20-887a-4563-9225-60733e5022a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666930296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.666930296
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.332352119
Short name T359
Test name
Test status
Simulation time 817428625 ps
CPU time 49.05 seconds
Started Jul 16 05:39:25 PM PDT 24
Finished Jul 16 05:40:16 PM PDT 24
Peak memory 256836 kb
Host smart-9c3a2091-c6a5-4e3a-9bf9-22bcb2b4bcb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33235
2119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.332352119
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.347195931
Short name T546
Test name
Test status
Simulation time 1416029313 ps
CPU time 27.31 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 05:39:52 PM PDT 24
Peak memory 249272 kb
Host smart-3f34b700-94b6-4a03-b1b5-824dec2eb36d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34719
5931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.347195931
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.827020183
Short name T537
Test name
Test status
Simulation time 380922058 ps
CPU time 11.59 seconds
Started Jul 16 05:39:25 PM PDT 24
Finished Jul 16 05:39:39 PM PDT 24
Peak memory 248680 kb
Host smart-5c6568de-1780-4efd-b07f-821c90ca65e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82702
0183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.827020183
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3512550860
Short name T534
Test name
Test status
Simulation time 1502936813 ps
CPU time 35.12 seconds
Started Jul 16 05:39:25 PM PDT 24
Finished Jul 16 05:40:02 PM PDT 24
Peak memory 249256 kb
Host smart-04abfa7b-4d79-4078-982f-3f2554cc35b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35125
50860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3512550860
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3919094222
Short name T470
Test name
Test status
Simulation time 38709283376 ps
CPU time 1095.77 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 05:57:41 PM PDT 24
Peak memory 273292 kb
Host smart-12cee9d4-db72-42bf-85d5-5fb5be2d89ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919094222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3919094222
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3602556628
Short name T89
Test name
Test status
Simulation time 22987733065 ps
CPU time 2443.72 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 06:20:08 PM PDT 24
Peak memory 306480 kb
Host smart-e086d4a6-26b0-46a0-9768-c9373f8a2f8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602556628 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3602556628
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.681719944
Short name T462
Test name
Test status
Simulation time 87290693976 ps
CPU time 2145.15 seconds
Started Jul 16 05:39:25 PM PDT 24
Finished Jul 16 06:15:13 PM PDT 24
Peak memory 288896 kb
Host smart-7ffe0b20-b83c-44c6-b9d7-90877496d953
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681719944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.681719944
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1161603062
Short name T387
Test name
Test status
Simulation time 1204468169 ps
CPU time 48.74 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 05:40:16 PM PDT 24
Peak memory 249232 kb
Host smart-00aed34f-9ff4-4ac0-858e-1b1f5492a9d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1161603062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1161603062
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1779686441
Short name T390
Test name
Test status
Simulation time 4043138640 ps
CPU time 211.17 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 05:42:57 PM PDT 24
Peak memory 257128 kb
Host smart-76964fe4-4d1c-4261-b96b-d7f67801f33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17796
86441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1779686441
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1789125653
Short name T507
Test name
Test status
Simulation time 5611707260 ps
CPU time 37.28 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 05:40:05 PM PDT 24
Peak memory 249344 kb
Host smart-a87c57bd-4a34-46be-8041-526566618e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17891
25653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1789125653
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2533945846
Short name T622
Test name
Test status
Simulation time 88477410574 ps
CPU time 1429.18 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 06:03:16 PM PDT 24
Peak memory 273252 kb
Host smart-788bd1b3-d090-44d6-a48a-9844032347da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533945846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2533945846
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.4121233868
Short name T636
Test name
Test status
Simulation time 89502679078 ps
CPU time 2615.23 seconds
Started Jul 16 05:39:21 PM PDT 24
Finished Jul 16 06:22:57 PM PDT 24
Peak memory 285184 kb
Host smart-76aad5a2-3778-4fb8-b2db-fe293c268aea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121233868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.4121233868
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1165651657
Short name T315
Test name
Test status
Simulation time 11896314277 ps
CPU time 114.11 seconds
Started Jul 16 05:39:25 PM PDT 24
Finished Jul 16 05:41:22 PM PDT 24
Peak memory 248216 kb
Host smart-f9454f07-16a7-4911-9d41-1123730d57e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165651657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1165651657
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.866481557
Short name T283
Test name
Test status
Simulation time 4048740006 ps
CPU time 63.39 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 05:40:29 PM PDT 24
Peak memory 257552 kb
Host smart-85bb2b4f-2712-4440-ba06-e28666c1bedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86648
1557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.866481557
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.458413353
Short name T365
Test name
Test status
Simulation time 207794720 ps
CPU time 7.03 seconds
Started Jul 16 05:39:29 PM PDT 24
Finished Jul 16 05:39:37 PM PDT 24
Peak memory 248780 kb
Host smart-457a2436-21d0-4579-821c-32f02fefea5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45841
3353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.458413353
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.454668468
Short name T357
Test name
Test status
Simulation time 19123847 ps
CPU time 3.17 seconds
Started Jul 16 05:39:29 PM PDT 24
Finished Jul 16 05:39:34 PM PDT 24
Peak memory 249196 kb
Host smart-bf5be273-2af5-4a49-a96b-397b1e02ff04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45466
8468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.454668468
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1471104306
Short name T566
Test name
Test status
Simulation time 400960742 ps
CPU time 23.2 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 05:39:52 PM PDT 24
Peak memory 257480 kb
Host smart-9ebc891e-c48f-4eaf-af2a-23f2e7534d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14711
04306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1471104306
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.636891940
Short name T212
Test name
Test status
Simulation time 105694074 ps
CPU time 2.81 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 05:39:27 PM PDT 24
Peak memory 249584 kb
Host smart-77f5eff8-7977-404d-8cf1-0178d7c43067
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=636891940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.636891940
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1375700761
Short name T102
Test name
Test status
Simulation time 56890549149 ps
CPU time 1335.61 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 06:01:42 PM PDT 24
Peak memory 290148 kb
Host smart-42262d8a-9a37-4bbb-bccb-2ce4147d0241
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375700761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1375700761
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3916127448
Short name T434
Test name
Test status
Simulation time 2927878066 ps
CPU time 33.53 seconds
Started Jul 16 05:39:27 PM PDT 24
Finished Jul 16 05:40:02 PM PDT 24
Peak memory 249308 kb
Host smart-57505d7c-0447-465a-8ca2-39c61dfc1a0f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3916127448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3916127448
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1662331695
Short name T689
Test name
Test status
Simulation time 12735666657 ps
CPU time 168.31 seconds
Started Jul 16 05:39:21 PM PDT 24
Finished Jul 16 05:42:10 PM PDT 24
Peak memory 257496 kb
Host smart-49f63e70-1c8f-4165-acd5-5eb966b6606d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16623
31695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1662331695
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.496117606
Short name T386
Test name
Test status
Simulation time 46846652 ps
CPU time 5.83 seconds
Started Jul 16 05:39:27 PM PDT 24
Finished Jul 16 05:39:35 PM PDT 24
Peak memory 249196 kb
Host smart-b7af045f-a07e-4f96-b3e9-c64b7cc8858c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49611
7606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.496117606
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3720187236
Short name T509
Test name
Test status
Simulation time 571648570777 ps
CPU time 3011.8 seconds
Started Jul 16 05:39:22 PM PDT 24
Finished Jul 16 06:29:35 PM PDT 24
Peak memory 282144 kb
Host smart-c176f301-b926-4215-804c-2650a1df078e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720187236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3720187236
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2391389927
Short name T667
Test name
Test status
Simulation time 6463238377 ps
CPU time 145.38 seconds
Started Jul 16 05:39:22 PM PDT 24
Finished Jul 16 05:41:49 PM PDT 24
Peak memory 256032 kb
Host smart-b85faa30-f5f8-4816-87c1-9242adec4928
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391389927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2391389927
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.778320986
Short name T393
Test name
Test status
Simulation time 551693910 ps
CPU time 28.9 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 05:39:55 PM PDT 24
Peak memory 256184 kb
Host smart-2b131613-706c-4a59-93af-08a63becbe17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77832
0986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.778320986
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2467048201
Short name T225
Test name
Test status
Simulation time 147455490 ps
CPU time 14.5 seconds
Started Jul 16 05:39:22 PM PDT 24
Finished Jul 16 05:39:38 PM PDT 24
Peak memory 249320 kb
Host smart-25045835-f1c0-4283-9dda-f3dec32e5de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24670
48201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2467048201
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.5309051
Short name T3
Test name
Test status
Simulation time 1038441025 ps
CPU time 23.66 seconds
Started Jul 16 05:39:27 PM PDT 24
Finished Jul 16 05:39:53 PM PDT 24
Peak memory 257408 kb
Host smart-8a664fb3-7cab-4552-b221-59d72dc80bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53090
51 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.5309051
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.4181867200
Short name T430
Test name
Test status
Simulation time 49347081895 ps
CPU time 1799.79 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 06:09:26 PM PDT 24
Peak memory 290264 kb
Host smart-bd8a1020-377f-4596-82e4-6d790bfd3d4c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181867200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.4181867200
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3103488229
Short name T594
Test name
Test status
Simulation time 381947522604 ps
CPU time 6206.96 seconds
Started Jul 16 05:39:22 PM PDT 24
Finished Jul 16 07:22:51 PM PDT 24
Peak memory 355220 kb
Host smart-942bb97e-8a06-496b-af38-10439d23e2be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103488229 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3103488229
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.592057887
Short name T206
Test name
Test status
Simulation time 37278396 ps
CPU time 2.29 seconds
Started Jul 16 05:39:34 PM PDT 24
Finished Jul 16 05:39:38 PM PDT 24
Peak memory 249528 kb
Host smart-77edd50f-d49b-4b40-8a94-86731590e5b4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=592057887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.592057887
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.404293832
Short name T675
Test name
Test status
Simulation time 922622977550 ps
CPU time 2976.38 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 06:29:14 PM PDT 24
Peak memory 290552 kb
Host smart-3406a25c-3e50-4375-9ddd-4bc4814f6c6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404293832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.404293832
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3991646542
Short name T428
Test name
Test status
Simulation time 422227532 ps
CPU time 13.78 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 05:39:51 PM PDT 24
Peak memory 249220 kb
Host smart-e1e3cb43-11a3-4ddf-af5a-574acd518e95
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3991646542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3991646542
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1090607208
Short name T578
Test name
Test status
Simulation time 6088334286 ps
CPU time 321.73 seconds
Started Jul 16 05:39:39 PM PDT 24
Finished Jul 16 05:45:02 PM PDT 24
Peak memory 257548 kb
Host smart-aea196b0-caab-4b9d-8089-bad01d0c6e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10906
07208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1090607208
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3745845147
Short name T419
Test name
Test status
Simulation time 1369935959 ps
CPU time 21.2 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 05:39:58 PM PDT 24
Peak memory 257472 kb
Host smart-96a3bf86-d6f0-4adc-b107-6d6288897ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37458
45147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3745845147
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3524669433
Short name T445
Test name
Test status
Simulation time 36483992211 ps
CPU time 1080.35 seconds
Started Jul 16 05:39:36 PM PDT 24
Finished Jul 16 05:57:40 PM PDT 24
Peak memory 273888 kb
Host smart-8dc28a7d-87df-49cc-ab14-aa467022c4f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524669433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3524669433
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1954819551
Short name T285
Test name
Test status
Simulation time 112827231346 ps
CPU time 1480.14 seconds
Started Jul 16 05:39:34 PM PDT 24
Finished Jul 16 06:04:16 PM PDT 24
Peak memory 273948 kb
Host smart-3ca2d3ee-245d-4fe5-8c6b-ee5dd5b73a24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954819551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1954819551
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.804185452
Short name T528
Test name
Test status
Simulation time 69040930884 ps
CPU time 304.26 seconds
Started Jul 16 05:39:38 PM PDT 24
Finished Jul 16 05:44:45 PM PDT 24
Peak memory 249316 kb
Host smart-8b5ae8e8-439d-4016-974a-a7bfac2933c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804185452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.804185452
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.591020530
Short name T585
Test name
Test status
Simulation time 755002678 ps
CPU time 21.48 seconds
Started Jul 16 05:39:38 PM PDT 24
Finished Jul 16 05:40:02 PM PDT 24
Peak memory 249172 kb
Host smart-22e1becc-a52a-4ac5-8f2a-daf59f58c9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59102
0530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.591020530
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1368459526
Short name T114
Test name
Test status
Simulation time 809906067 ps
CPU time 48.84 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 05:40:27 PM PDT 24
Peak memory 248948 kb
Host smart-c8accedc-f559-4642-becd-0590dcdcfb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13684
59526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1368459526
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1774680803
Short name T703
Test name
Test status
Simulation time 336418946 ps
CPU time 10.11 seconds
Started Jul 16 05:39:33 PM PDT 24
Finished Jul 16 05:39:44 PM PDT 24
Peak memory 256968 kb
Host smart-7669402e-47fc-4448-a991-a24420f9ec79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17746
80803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1774680803
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2066701163
Short name T20
Test name
Test status
Simulation time 27160249 ps
CPU time 4.56 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 05:39:33 PM PDT 24
Peak memory 249200 kb
Host smart-15d31555-0887-4014-936c-c931f9d8aef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20667
01163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2066701163
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1232708773
Short name T97
Test name
Test status
Simulation time 98378163207 ps
CPU time 2693.09 seconds
Started Jul 16 05:39:37 PM PDT 24
Finished Jul 16 06:24:33 PM PDT 24
Peak memory 290008 kb
Host smart-ba1a8457-6dc4-43b4-80f4-0d7c9988a980
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232708773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1232708773
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2098662379
Short name T177
Test name
Test status
Simulation time 70566259168 ps
CPU time 6580.82 seconds
Started Jul 16 05:39:36 PM PDT 24
Finished Jul 16 07:29:20 PM PDT 24
Peak memory 347772 kb
Host smart-9eb9fff5-4c1b-435c-ac97-319e45c1bac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098662379 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2098662379
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3927552921
Short name T202
Test name
Test status
Simulation time 156953652 ps
CPU time 3.83 seconds
Started Jul 16 05:39:36 PM PDT 24
Finished Jul 16 05:39:43 PM PDT 24
Peak memory 249500 kb
Host smart-f725bb24-91a4-4e0c-94a6-2920fde7e170
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3927552921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3927552921
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3446891318
Short name T6
Test name
Test status
Simulation time 109813378762 ps
CPU time 1634.95 seconds
Started Jul 16 05:39:36 PM PDT 24
Finished Jul 16 06:06:53 PM PDT 24
Peak memory 273724 kb
Host smart-2daefdd9-4137-4ba1-a9cc-d6fbb6890298
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446891318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3446891318
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.379569678
Short name T178
Test name
Test status
Simulation time 1633462932 ps
CPU time 20.84 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 05:39:57 PM PDT 24
Peak memory 249188 kb
Host smart-91571a9c-367f-4f0b-b236-2cec570bd2dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=379569678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.379569678
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.613131242
Short name T275
Test name
Test status
Simulation time 5038271002 ps
CPU time 170.32 seconds
Started Jul 16 05:39:39 PM PDT 24
Finished Jul 16 05:42:32 PM PDT 24
Peak memory 256628 kb
Host smart-d2f03062-f1f0-43b0-97bb-2e84d301ab95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61313
1242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.613131242
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3502509149
Short name T707
Test name
Test status
Simulation time 1433400326 ps
CPU time 24.15 seconds
Started Jul 16 05:39:38 PM PDT 24
Finished Jul 16 05:40:04 PM PDT 24
Peak memory 255776 kb
Host smart-de795df0-f345-47e0-8f81-847ad2aa0dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35025
09149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3502509149
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3039709186
Short name T307
Test name
Test status
Simulation time 18095208585 ps
CPU time 1343.61 seconds
Started Jul 16 05:39:39 PM PDT 24
Finished Jul 16 06:02:05 PM PDT 24
Peak memory 273096 kb
Host smart-c23c78ca-62fd-4679-932c-902708dfd3c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039709186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3039709186
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.682755907
Short name T373
Test name
Test status
Simulation time 100466859558 ps
CPU time 1596.93 seconds
Started Jul 16 05:39:34 PM PDT 24
Finished Jul 16 06:06:12 PM PDT 24
Peak memory 265796 kb
Host smart-257fa10e-c265-4bb9-8c96-a49fe60d162d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682755907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.682755907
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3015696318
Short name T681
Test name
Test status
Simulation time 18425432594 ps
CPU time 386.5 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:46:22 PM PDT 24
Peak memory 255712 kb
Host smart-e163f200-c483-475b-9f54-e30b87cb78e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015696318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3015696318
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2931510973
Short name T221
Test name
Test status
Simulation time 12237839478 ps
CPU time 38.73 seconds
Started Jul 16 05:39:40 PM PDT 24
Finished Jul 16 05:40:21 PM PDT 24
Peak memory 249328 kb
Host smart-e3951cf6-b6e8-4c3b-b57d-cf8c67222a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29315
10973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2931510973
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3904800919
Short name T376
Test name
Test status
Simulation time 328898792 ps
CPU time 11.57 seconds
Started Jul 16 05:39:37 PM PDT 24
Finished Jul 16 05:39:51 PM PDT 24
Peak memory 249172 kb
Host smart-44281e6d-3b3f-4e86-b1ea-115c5cb5fdbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39048
00919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3904800919
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.57341530
Short name T608
Test name
Test status
Simulation time 280538416 ps
CPU time 24.24 seconds
Started Jul 16 05:39:44 PM PDT 24
Finished Jul 16 05:40:10 PM PDT 24
Peak memory 248608 kb
Host smart-2e783dbd-e828-444e-a82d-aec0d6f7f526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57341
530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.57341530
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.197440825
Short name T599
Test name
Test status
Simulation time 1435479143 ps
CPU time 24.29 seconds
Started Jul 16 05:39:32 PM PDT 24
Finished Jul 16 05:39:57 PM PDT 24
Peak memory 255696 kb
Host smart-5893e40b-2ab6-4ac1-aa30-3261c49551f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19744
0825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.197440825
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3208742014
Short name T372
Test name
Test status
Simulation time 44305714588 ps
CPU time 1042.52 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 05:56:59 PM PDT 24
Peak memory 285688 kb
Host smart-d6b48ef3-0187-493c-88de-33803720af6c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208742014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3208742014
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3173141799
Short name T108
Test name
Test status
Simulation time 126389711230 ps
CPU time 2706.82 seconds
Started Jul 16 05:39:33 PM PDT 24
Finished Jul 16 06:24:42 PM PDT 24
Peak memory 298384 kb
Host smart-a775ebaa-b64a-46c2-b90e-4953c6d1225f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173141799 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3173141799
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3720274950
Short name T208
Test name
Test status
Simulation time 158672532 ps
CPU time 3.5 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 05:39:41 PM PDT 24
Peak memory 249496 kb
Host smart-1b5e4053-3339-4b2a-a628-9d1969ad6820
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3720274950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3720274950
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.41628211
Short name T38
Test name
Test status
Simulation time 311087039726 ps
CPU time 2361.26 seconds
Started Jul 16 05:39:41 PM PDT 24
Finished Jul 16 06:19:04 PM PDT 24
Peak memory 289532 kb
Host smart-de4add05-2ba9-432a-b6f5-eab0723729a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41628211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.41628211
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3773944452
Short name T364
Test name
Test status
Simulation time 2864385783 ps
CPU time 59.48 seconds
Started Jul 16 05:39:37 PM PDT 24
Finished Jul 16 05:40:39 PM PDT 24
Peak memory 249312 kb
Host smart-4b8a7770-7287-44f5-ad95-ccfb90cf6717
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3773944452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3773944452
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1703376469
Short name T574
Test name
Test status
Simulation time 3572064375 ps
CPU time 191.38 seconds
Started Jul 16 05:39:38 PM PDT 24
Finished Jul 16 05:42:52 PM PDT 24
Peak memory 256972 kb
Host smart-78fc585d-8b64-4d14-abdc-08efee5da8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17033
76469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1703376469
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2398350883
Short name T401
Test name
Test status
Simulation time 240002427 ps
CPU time 19.25 seconds
Started Jul 16 05:39:36 PM PDT 24
Finished Jul 16 05:39:58 PM PDT 24
Peak memory 249276 kb
Host smart-abe5cdc0-b8cd-4c57-bc52-5df1f38a85ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23983
50883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2398350883
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3598011546
Short name T223
Test name
Test status
Simulation time 220836728380 ps
CPU time 2846.03 seconds
Started Jul 16 05:39:34 PM PDT 24
Finished Jul 16 06:27:02 PM PDT 24
Peak memory 287264 kb
Host smart-228aeb98-379e-42b4-8cfa-9a86918ecbc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598011546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3598011546
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.260349701
Short name T642
Test name
Test status
Simulation time 14298654206 ps
CPU time 1483.33 seconds
Started Jul 16 05:39:33 PM PDT 24
Finished Jul 16 06:04:18 PM PDT 24
Peak memory 288072 kb
Host smart-45dcccf6-a791-4d27-84c1-e06b00227771
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260349701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.260349701
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3369076418
Short name T314
Test name
Test status
Simulation time 5786621249 ps
CPU time 122.12 seconds
Started Jul 16 05:39:37 PM PDT 24
Finished Jul 16 05:41:42 PM PDT 24
Peak memory 248160 kb
Host smart-cbb2bb2a-8e23-4157-b8f3-0a2113082c85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369076418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3369076418
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.293431158
Short name T418
Test name
Test status
Simulation time 389267162 ps
CPU time 32.69 seconds
Started Jul 16 05:39:40 PM PDT 24
Finished Jul 16 05:40:15 PM PDT 24
Peak memory 256736 kb
Host smart-9fc041e6-b6a6-4b2c-b9c5-29e9c7767b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29343
1158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.293431158
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2863657783
Short name T83
Test name
Test status
Simulation time 775569429 ps
CPU time 37.18 seconds
Started Jul 16 05:39:32 PM PDT 24
Finished Jul 16 05:40:10 PM PDT 24
Peak memory 249240 kb
Host smart-4f2e3023-50ad-40ee-a528-4de9d6ba9e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28636
57783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2863657783
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.637004963
Short name T250
Test name
Test status
Simulation time 95203397 ps
CPU time 7.18 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 05:39:45 PM PDT 24
Peak memory 254220 kb
Host smart-ba2d18d8-5157-4849-a30b-efd472220be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63700
4963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.637004963
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.736787494
Short name T449
Test name
Test status
Simulation time 172581395963 ps
CPU time 2735.48 seconds
Started Jul 16 05:39:37 PM PDT 24
Finished Jul 16 06:25:15 PM PDT 24
Peak memory 282120 kb
Host smart-685b7a9d-764a-4994-a6ef-fe0cdf6f2d85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736787494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.736787494
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.674041846
Short name T176
Test name
Test status
Simulation time 290093158584 ps
CPU time 7117.64 seconds
Started Jul 16 05:39:38 PM PDT 24
Finished Jul 16 07:38:19 PM PDT 24
Peak memory 371536 kb
Host smart-7f759419-ae4b-436c-8559-67b50f9e077a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674041846 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.674041846
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3510641888
Short name T204
Test name
Test status
Simulation time 17502278 ps
CPU time 3.07 seconds
Started Jul 16 05:39:40 PM PDT 24
Finished Jul 16 05:39:45 PM PDT 24
Peak memory 249544 kb
Host smart-39dfe7f1-7829-4788-a2ef-66f77636da44
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3510641888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3510641888
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3387352250
Short name T379
Test name
Test status
Simulation time 43724563025 ps
CPU time 1389.29 seconds
Started Jul 16 05:39:41 PM PDT 24
Finished Jul 16 06:02:53 PM PDT 24
Peak memory 273920 kb
Host smart-a79248d6-cdea-4d74-96c1-eaec9ada6b43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387352250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3387352250
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.826670423
Short name T369
Test name
Test status
Simulation time 450348781 ps
CPU time 13.08 seconds
Started Jul 16 05:39:39 PM PDT 24
Finished Jul 16 05:39:54 PM PDT 24
Peak memory 249276 kb
Host smart-8a0d3e7e-6dc4-4c18-a543-b910c52fc2e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=826670423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.826670423
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2748648928
Short name T532
Test name
Test status
Simulation time 95811307 ps
CPU time 13.52 seconds
Started Jul 16 05:39:33 PM PDT 24
Finished Jul 16 05:39:48 PM PDT 24
Peak memory 254880 kb
Host smart-5bbfc827-7eef-4457-9a4f-c90c7e350419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27486
48928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2748648928
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1427905965
Short name T456
Test name
Test status
Simulation time 640966947 ps
CPU time 22.8 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 05:40:01 PM PDT 24
Peak memory 249316 kb
Host smart-8c028d27-1208-4957-8f4c-d506846a3fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14279
05965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1427905965
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2055250245
Short name T339
Test name
Test status
Simulation time 18905506041 ps
CPU time 1139.92 seconds
Started Jul 16 05:39:34 PM PDT 24
Finished Jul 16 05:58:36 PM PDT 24
Peak memory 267764 kb
Host smart-43e7ae63-edea-4fda-ac32-182e0aaecc70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055250245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2055250245
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1943668520
Short name T448
Test name
Test status
Simulation time 14540126035 ps
CPU time 153.69 seconds
Started Jul 16 05:39:36 PM PDT 24
Finished Jul 16 05:42:13 PM PDT 24
Peak memory 255576 kb
Host smart-76f9323a-32fc-45fd-b0f2-e2252bc7b0c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943668520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1943668520
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.530846337
Short name T497
Test name
Test status
Simulation time 132114738 ps
CPU time 7.4 seconds
Started Jul 16 05:39:33 PM PDT 24
Finished Jul 16 05:39:42 PM PDT 24
Peak memory 249140 kb
Host smart-68b438b4-b072-4e0e-a175-d3c848033a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53084
6337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.530846337
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1070355355
Short name T525
Test name
Test status
Simulation time 92804467 ps
CPU time 8.1 seconds
Started Jul 16 05:39:37 PM PDT 24
Finished Jul 16 05:39:47 PM PDT 24
Peak memory 248748 kb
Host smart-947032ac-74e3-4472-9433-c35b5f23d6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10703
55355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1070355355
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1312220728
Short name T653
Test name
Test status
Simulation time 482022082 ps
CPU time 10.8 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 05:39:48 PM PDT 24
Peak memory 253376 kb
Host smart-8439020a-0fc1-43e5-8603-1301c539d0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13122
20728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1312220728
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.550655057
Short name T107
Test name
Test status
Simulation time 300016790 ps
CPU time 11.41 seconds
Started Jul 16 05:39:36 PM PDT 24
Finished Jul 16 05:39:50 PM PDT 24
Peak memory 256352 kb
Host smart-e4ee788c-73c6-441c-9ea0-22c2b4d597b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55065
5057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.550655057
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1370400761
Short name T205
Test name
Test status
Simulation time 132379805 ps
CPU time 2.52 seconds
Started Jul 16 05:39:40 PM PDT 24
Finished Jul 16 05:39:45 PM PDT 24
Peak memory 249548 kb
Host smart-800957f7-5dca-4af3-a2e4-6f08a069352c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1370400761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1370400761
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.768902454
Short name T399
Test name
Test status
Simulation time 19342004665 ps
CPU time 2127.61 seconds
Started Jul 16 05:39:37 PM PDT 24
Finished Jul 16 06:15:07 PM PDT 24
Peak memory 290024 kb
Host smart-2c4c1546-a321-49a4-a34c-477d20bdb24b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768902454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.768902454
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3472216418
Short name T397
Test name
Test status
Simulation time 618384438 ps
CPU time 27.09 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:40:22 PM PDT 24
Peak memory 249096 kb
Host smart-778a98f9-9bbf-4b6d-8215-ceac05f7a289
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3472216418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3472216418
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1202685029
Short name T668
Test name
Test status
Simulation time 2783623377 ps
CPU time 168.59 seconds
Started Jul 16 05:39:40 PM PDT 24
Finished Jul 16 05:42:31 PM PDT 24
Peak memory 257108 kb
Host smart-8ac5b0b4-132e-4163-bded-dc7b1785101a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12026
85029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1202685029
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3130923622
Short name T437
Test name
Test status
Simulation time 2045420697 ps
CPU time 32.57 seconds
Started Jul 16 05:39:36 PM PDT 24
Finished Jul 16 05:40:11 PM PDT 24
Peak memory 249192 kb
Host smart-795e1daa-96be-4df6-b955-cc03b49de7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31309
23622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3130923622
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2262730101
Short name T312
Test name
Test status
Simulation time 13822922383 ps
CPU time 1388.34 seconds
Started Jul 16 05:39:40 PM PDT 24
Finished Jul 16 06:02:51 PM PDT 24
Peak memory 290032 kb
Host smart-cb939e0c-4335-425a-849c-5f219d26e1f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262730101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2262730101
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.345746975
Short name T542
Test name
Test status
Simulation time 74403190867 ps
CPU time 2423.97 seconds
Started Jul 16 05:39:40 PM PDT 24
Finished Jul 16 06:20:06 PM PDT 24
Peak memory 273904 kb
Host smart-64c3f055-9f40-4d78-82c7-6b737f140201
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345746975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.345746975
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2238360808
Short name T502
Test name
Test status
Simulation time 14852489295 ps
CPU time 588.25 seconds
Started Jul 16 05:39:40 PM PDT 24
Finished Jul 16 05:49:30 PM PDT 24
Peak memory 249292 kb
Host smart-dcefd639-5d81-4e82-88f3-b38e94bbf907
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238360808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2238360808
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3397954109
Short name T230
Test name
Test status
Simulation time 1628932879 ps
CPU time 34.05 seconds
Started Jul 16 05:39:39 PM PDT 24
Finished Jul 16 05:40:16 PM PDT 24
Peak memory 256492 kb
Host smart-3e546c36-4a70-4023-a6d6-ced088f1b007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33979
54109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3397954109
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3516705718
Short name T483
Test name
Test status
Simulation time 264212229 ps
CPU time 3.17 seconds
Started Jul 16 05:39:38 PM PDT 24
Finished Jul 16 05:39:43 PM PDT 24
Peak memory 240432 kb
Host smart-f78e23e1-6db7-4654-85be-b1b7a3474b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35167
05718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3516705718
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1426140768
Short name T79
Test name
Test status
Simulation time 206152826 ps
CPU time 19.23 seconds
Started Jul 16 05:39:35 PM PDT 24
Finished Jul 16 05:39:57 PM PDT 24
Peak memory 249400 kb
Host smart-aaef8b31-0ba5-495b-baea-50360aa4b094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14261
40768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1426140768
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1387161367
Short name T429
Test name
Test status
Simulation time 51982961 ps
CPU time 4.09 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:39:59 PM PDT 24
Peak memory 240976 kb
Host smart-03329933-5965-4c4d-9bdd-5bf99fa2b3eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13871
61367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1387161367
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1994491239
Short name T573
Test name
Test status
Simulation time 46124671612 ps
CPU time 1265.28 seconds
Started Jul 16 05:39:36 PM PDT 24
Finished Jul 16 06:00:44 PM PDT 24
Peak memory 273968 kb
Host smart-1f1bff0b-e234-42f8-a7f8-6c13eefff293
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994491239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1994491239
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.350124756
Short name T56
Test name
Test status
Simulation time 125980068226 ps
CPU time 1276.75 seconds
Started Jul 16 05:39:33 PM PDT 24
Finished Jul 16 06:00:52 PM PDT 24
Peak memory 290076 kb
Host smart-ff6520d7-af91-415f-ab6d-aa202d9e0245
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350124756 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.350124756
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1577212356
Short name T211
Test name
Test status
Simulation time 16585740 ps
CPU time 3.03 seconds
Started Jul 16 05:39:44 PM PDT 24
Finished Jul 16 05:39:48 PM PDT 24
Peak memory 249540 kb
Host smart-bd4583dd-81ec-41c6-87a5-5993eef5bbab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1577212356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1577212356
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1368900643
Short name T110
Test name
Test status
Simulation time 19804060182 ps
CPU time 1486.85 seconds
Started Jul 16 05:39:39 PM PDT 24
Finished Jul 16 06:04:28 PM PDT 24
Peak memory 273588 kb
Host smart-9e940701-f2b1-4745-8c0b-82c8a986855c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368900643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1368900643
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.438815626
Short name T338
Test name
Test status
Simulation time 1025440032 ps
CPU time 14.42 seconds
Started Jul 16 05:39:46 PM PDT 24
Finished Jul 16 05:40:02 PM PDT 24
Peak memory 249236 kb
Host smart-ebce8c02-ad75-43b7-a695-d9e9d20f0d20
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=438815626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.438815626
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2802021702
Short name T438
Test name
Test status
Simulation time 441419145 ps
CPU time 30.67 seconds
Started Jul 16 05:39:40 PM PDT 24
Finished Jul 16 05:40:12 PM PDT 24
Peak memory 256948 kb
Host smart-50672e4b-bf15-4731-9134-8335191d16f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28020
21702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2802021702
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2175689532
Short name T26
Test name
Test status
Simulation time 1575049131 ps
CPU time 49.92 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:40:45 PM PDT 24
Peak memory 256468 kb
Host smart-c4d6c533-b3f7-4aa5-9d28-18a7c325699b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21756
89532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2175689532
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.798190079
Short name T571
Test name
Test status
Simulation time 21897322339 ps
CPU time 1176.18 seconds
Started Jul 16 05:39:42 PM PDT 24
Finished Jul 16 05:59:20 PM PDT 24
Peak memory 289428 kb
Host smart-d9cf175c-f810-438e-a1be-7a31a3da76d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798190079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.798190079
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3432564755
Short name T216
Test name
Test status
Simulation time 13045981493 ps
CPU time 140.34 seconds
Started Jul 16 05:39:37 PM PDT 24
Finished Jul 16 05:42:00 PM PDT 24
Peak memory 249372 kb
Host smart-450b9899-ff3f-490a-88a5-fcc31f688893
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432564755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3432564755
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2767528619
Short name T60
Test name
Test status
Simulation time 441719237 ps
CPU time 45.83 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:40:40 PM PDT 24
Peak memory 249192 kb
Host smart-d1112501-de72-48e3-96cd-5f25235b03fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27675
28619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2767528619
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.184694173
Short name T514
Test name
Test status
Simulation time 2865365824 ps
CPU time 47.12 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:40:42 PM PDT 24
Peak memory 249416 kb
Host smart-20924b40-15d3-40ac-a48e-d2a187e9b270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18469
4173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.184694173
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.4137449318
Short name T480
Test name
Test status
Simulation time 519890780 ps
CPU time 17.04 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:40:12 PM PDT 24
Peak memory 256472 kb
Host smart-979627f8-fe73-42d6-88b2-4d3eb7476576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41374
49318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.4137449318
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.226549745
Short name T512
Test name
Test status
Simulation time 1832776136 ps
CPU time 39.81 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:40:35 PM PDT 24
Peak memory 257432 kb
Host smart-a2e2034d-f880-4156-a93e-e4f9a9449966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22654
9745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.226549745
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2848111893
Short name T197
Test name
Test status
Simulation time 250843038 ps
CPU time 3.89 seconds
Started Jul 16 05:39:18 PM PDT 24
Finished Jul 16 05:39:23 PM PDT 24
Peak memory 249460 kb
Host smart-99075f5d-ed56-45a1-b815-1d4ea4be5463
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2848111893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2848111893
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2126993796
Short name T35
Test name
Test status
Simulation time 114981040136 ps
CPU time 1765.01 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 06:08:39 PM PDT 24
Peak memory 273436 kb
Host smart-88ceba5e-1253-41c2-bb44-616499ed4470
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126993796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2126993796
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.460501446
Short name T661
Test name
Test status
Simulation time 126033215 ps
CPU time 8.54 seconds
Started Jul 16 05:39:10 PM PDT 24
Finished Jul 16 05:39:20 PM PDT 24
Peak memory 249260 kb
Host smart-d540da3f-2758-4cce-955f-5b9eea5cd74d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=460501446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.460501446
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2076710029
Short name T182
Test name
Test status
Simulation time 1784184128 ps
CPU time 106.42 seconds
Started Jul 16 05:39:08 PM PDT 24
Finished Jul 16 05:40:56 PM PDT 24
Peak memory 250296 kb
Host smart-95cdc564-5b9e-492f-9231-4d211b15ef73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20767
10029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2076710029
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2936417501
Short name T343
Test name
Test status
Simulation time 2454615161 ps
CPU time 31.5 seconds
Started Jul 16 05:39:12 PM PDT 24
Finished Jul 16 05:39:45 PM PDT 24
Peak memory 249168 kb
Host smart-88a80c39-3566-47b0-8f57-4354271a09c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29364
17501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2936417501
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1000176183
Short name T289
Test name
Test status
Simulation time 13933168536 ps
CPU time 1451.88 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 06:03:22 PM PDT 24
Peak memory 282084 kb
Host smart-31759707-7827-4c6b-9ff7-b0b6598f2cf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000176183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1000176183
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1449204814
Short name T619
Test name
Test status
Simulation time 23587050047 ps
CPU time 1044 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 05:56:39 PM PDT 24
Peak memory 273836 kb
Host smart-70471ba8-2b9a-495b-b0dc-2d6d0efa87d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449204814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1449204814
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1730606718
Short name T7
Test name
Test status
Simulation time 8060804112 ps
CPU time 89.3 seconds
Started Jul 16 05:39:19 PM PDT 24
Finished Jul 16 05:40:48 PM PDT 24
Peak memory 249300 kb
Host smart-79f4f064-6c6e-41de-84d6-62fb1da4d0f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730606718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1730606718
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2922984852
Short name T402
Test name
Test status
Simulation time 286244910 ps
CPU time 23.89 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 05:39:34 PM PDT 24
Peak memory 249172 kb
Host smart-a64e39b4-7dc2-45c5-83d5-1e42e164d386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29229
84852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2922984852
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2379716262
Short name T484
Test name
Test status
Simulation time 3963680405 ps
CPU time 32.54 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:39:45 PM PDT 24
Peak memory 257316 kb
Host smart-dcc59848-ee19-4dbe-9552-5489b576ded4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23797
16262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2379716262
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2821502117
Short name T41
Test name
Test status
Simulation time 1020873515 ps
CPU time 49.72 seconds
Started Jul 16 05:39:15 PM PDT 24
Finished Jul 16 05:40:06 PM PDT 24
Peak memory 270504 kb
Host smart-8957c375-d58b-4974-98c2-fc2f0fac2058
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2821502117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2821502117
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1077766079
Short name T518
Test name
Test status
Simulation time 384184415 ps
CPU time 10.39 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 05:39:25 PM PDT 24
Peak memory 249628 kb
Host smart-950fa3a1-e412-4ed8-aa60-f84d92583f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10777
66079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1077766079
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1212400027
Short name T482
Test name
Test status
Simulation time 310325570 ps
CPU time 32.06 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 05:39:43 PM PDT 24
Peak memory 256676 kb
Host smart-0b3c6f19-640e-4e92-a0de-28e979a34728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12124
00027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1212400027
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3884140158
Short name T665
Test name
Test status
Simulation time 317091616042 ps
CPU time 2324.36 seconds
Started Jul 16 05:39:10 PM PDT 24
Finished Jul 16 06:17:56 PM PDT 24
Peak memory 289404 kb
Host smart-040469d8-f176-4b0f-b8db-9f431c31d8af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884140158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3884140158
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2641548305
Short name T583
Test name
Test status
Simulation time 49913854101 ps
CPU time 3213.51 seconds
Started Jul 16 05:39:43 PM PDT 24
Finished Jul 16 06:33:18 PM PDT 24
Peak memory 289952 kb
Host smart-0c9152d5-7647-4637-9617-f7c642a74158
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641548305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2641548305
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3505435928
Short name T669
Test name
Test status
Simulation time 11723446636 ps
CPU time 179.84 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 05:42:57 PM PDT 24
Peak memory 257584 kb
Host smart-aad71089-ef9d-4af6-a936-6ad8956df75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35054
35928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3505435928
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2679174608
Short name T72
Test name
Test status
Simulation time 161601931 ps
CPU time 5.88 seconds
Started Jul 16 05:39:48 PM PDT 24
Finished Jul 16 05:39:54 PM PDT 24
Peak memory 249196 kb
Host smart-1ec111d4-21a4-4d09-be7a-1cdffbb57e1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26791
74608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2679174608
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1687625727
Short name T572
Test name
Test status
Simulation time 41529489429 ps
CPU time 1177.78 seconds
Started Jul 16 05:39:44 PM PDT 24
Finished Jul 16 05:59:23 PM PDT 24
Peak memory 273016 kb
Host smart-034a4ff8-1ab2-4fe0-9ad5-b3d9b7866744
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687625727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1687625727
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3781659090
Short name T439
Test name
Test status
Simulation time 14442129186 ps
CPU time 893.03 seconds
Started Jul 16 05:39:46 PM PDT 24
Finished Jul 16 05:54:40 PM PDT 24
Peak memory 273624 kb
Host smart-cb2e9ddf-03fc-4e90-aaa5-aafcf6a510f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781659090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3781659090
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2558517334
Short name T304
Test name
Test status
Simulation time 37894601134 ps
CPU time 416.04 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 05:46:54 PM PDT 24
Peak memory 249368 kb
Host smart-e8e032a1-8f25-4951-8362-4bcab1cdc4db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558517334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2558517334
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1712604248
Short name T616
Test name
Test status
Simulation time 3217127700 ps
CPU time 59.59 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:40:54 PM PDT 24
Peak memory 256912 kb
Host smart-d4cf74bf-c1d8-4f71-b195-354a788c7c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17126
04248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1712604248
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.252281281
Short name T425
Test name
Test status
Simulation time 153175368 ps
CPU time 14.96 seconds
Started Jul 16 05:39:46 PM PDT 24
Finished Jul 16 05:40:02 PM PDT 24
Peak memory 248928 kb
Host smart-d5751f42-87ef-478e-9963-65dd0dac8ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25228
1281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.252281281
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1493822642
Short name T614
Test name
Test status
Simulation time 2197904177 ps
CPU time 8.54 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 05:40:06 PM PDT 24
Peak memory 255192 kb
Host smart-f847636a-9c98-4a4e-a176-aab6e7702ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14938
22642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1493822642
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3313125930
Short name T559
Test name
Test status
Simulation time 647213118 ps
CPU time 41.11 seconds
Started Jul 16 05:39:42 PM PDT 24
Finished Jul 16 05:40:25 PM PDT 24
Peak memory 257352 kb
Host smart-a26b5c32-6a03-4b5c-8838-1bb16640e721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33131
25930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3313125930
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.883391656
Short name T465
Test name
Test status
Simulation time 89194694294 ps
CPU time 1507.02 seconds
Started Jul 16 05:39:42 PM PDT 24
Finished Jul 16 06:04:51 PM PDT 24
Peak memory 273816 kb
Host smart-79fa5bbd-3ba9-441b-b692-e4bfb9cf5701
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883391656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.883391656
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.27766559
Short name T541
Test name
Test status
Simulation time 6912343816 ps
CPU time 211.4 seconds
Started Jul 16 05:39:46 PM PDT 24
Finished Jul 16 05:43:18 PM PDT 24
Peak memory 257388 kb
Host smart-dc62a7ea-9cb0-4908-82b7-27934d3557c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27766
559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.27766559
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3951453096
Short name T581
Test name
Test status
Simulation time 469195435 ps
CPU time 28.38 seconds
Started Jul 16 05:39:43 PM PDT 24
Finished Jul 16 05:40:13 PM PDT 24
Peak memory 256992 kb
Host smart-f9a29064-2d0f-40b9-9a1c-cdc326bd457e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39514
53096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3951453096
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2520017928
Short name T627
Test name
Test status
Simulation time 111253809862 ps
CPU time 1463.45 seconds
Started Jul 16 05:39:43 PM PDT 24
Finished Jul 16 06:04:08 PM PDT 24
Peak memory 273980 kb
Host smart-83170fe8-cb4f-46bd-b2d7-bf1171de6a12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520017928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2520017928
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.755597406
Short name T533
Test name
Test status
Simulation time 25188014179 ps
CPU time 268.17 seconds
Started Jul 16 05:39:41 PM PDT 24
Finished Jul 16 05:44:11 PM PDT 24
Peak memory 249316 kb
Host smart-b70d47d5-69a5-426c-ad62-5161b16da39d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755597406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.755597406
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1026444779
Short name T602
Test name
Test status
Simulation time 189797094 ps
CPU time 15.94 seconds
Started Jul 16 05:39:43 PM PDT 24
Finished Jul 16 05:40:01 PM PDT 24
Peak memory 249160 kb
Host smart-d896da7c-29e4-4122-96f3-8fdbf7163051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10264
44779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1026444779
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1362364998
Short name T701
Test name
Test status
Simulation time 3040390022 ps
CPU time 40.23 seconds
Started Jul 16 05:39:42 PM PDT 24
Finished Jul 16 05:40:25 PM PDT 24
Peak memory 249380 kb
Host smart-b8902644-135f-4334-b1f4-01ed08e59fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13623
64998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1362364998
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1593994373
Short name T613
Test name
Test status
Simulation time 4156157400 ps
CPU time 56.32 seconds
Started Jul 16 05:39:42 PM PDT 24
Finished Jul 16 05:40:41 PM PDT 24
Peak memory 248988 kb
Host smart-59a2ac97-6c8f-47b0-b6c8-e3d4189e46cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15939
94373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1593994373
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.324975424
Short name T19
Test name
Test status
Simulation time 156986058 ps
CPU time 17.87 seconds
Started Jul 16 05:39:45 PM PDT 24
Finished Jul 16 05:40:04 PM PDT 24
Peak memory 249652 kb
Host smart-a776b594-b749-4f7a-8c5c-002707863d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32497
5424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.324975424
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2837362582
Short name T87
Test name
Test status
Simulation time 123845955382 ps
CPU time 1902.46 seconds
Started Jul 16 05:39:46 PM PDT 24
Finished Jul 16 06:11:30 PM PDT 24
Peak memory 287560 kb
Host smart-d9c369a0-4915-4ebb-8cc6-46bfeda9a4a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837362582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2837362582
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1495128374
Short name T629
Test name
Test status
Simulation time 15620193420 ps
CPU time 1105.63 seconds
Started Jul 16 05:39:45 PM PDT 24
Finished Jul 16 05:58:12 PM PDT 24
Peak memory 273604 kb
Host smart-90e3b8b9-6cc7-4fe4-9d29-eb5d244fcfa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495128374 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1495128374
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.23239991
Short name T511
Test name
Test status
Simulation time 50989648733 ps
CPU time 1794.73 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 06:09:52 PM PDT 24
Peak memory 270812 kb
Host smart-72945c5c-b3c5-4548-aed8-a0854cf4b816
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23239991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.23239991
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3123957348
Short name T237
Test name
Test status
Simulation time 1722536980 ps
CPU time 114.03 seconds
Started Jul 16 05:39:46 PM PDT 24
Finished Jul 16 05:41:41 PM PDT 24
Peak memory 256928 kb
Host smart-aedcb55d-dee8-4d1e-9d84-96f14c081add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31239
57348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3123957348
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3527067784
Short name T696
Test name
Test status
Simulation time 1058662914 ps
CPU time 27.12 seconds
Started Jul 16 05:39:43 PM PDT 24
Finished Jul 16 05:40:12 PM PDT 24
Peak memory 255884 kb
Host smart-531b4988-9552-4d70-a264-b8e317d6e99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35270
67784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3527067784
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.280315847
Short name T293
Test name
Test status
Simulation time 44103704128 ps
CPU time 2622.38 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 06:23:40 PM PDT 24
Peak memory 285628 kb
Host smart-e6fa5aab-9e2d-4d71-8092-c35236ae50c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280315847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.280315847
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1747813840
Short name T71
Test name
Test status
Simulation time 120179858947 ps
CPU time 2078.27 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 06:14:36 PM PDT 24
Peak memory 286128 kb
Host smart-f81382d5-a3da-4ebf-a272-2492f91977c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747813840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1747813840
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3829316643
Short name T298
Test name
Test status
Simulation time 49948635912 ps
CPU time 529.92 seconds
Started Jul 16 05:39:45 PM PDT 24
Finished Jul 16 05:48:36 PM PDT 24
Peak memory 255992 kb
Host smart-ca385a2f-f4f4-494d-85ac-83849b808651
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829316643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3829316643
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3630998946
Short name T406
Test name
Test status
Simulation time 6048589945 ps
CPU time 52.23 seconds
Started Jul 16 05:39:42 PM PDT 24
Finished Jul 16 05:40:36 PM PDT 24
Peak memory 257116 kb
Host smart-0976f661-ea76-4473-b58a-15b25a9e3406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36309
98946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3630998946
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3810851414
Short name T220
Test name
Test status
Simulation time 175608731 ps
CPU time 13.11 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 05:40:11 PM PDT 24
Peak memory 248856 kb
Host smart-d2f51e36-5d2c-4012-9fdb-29baff8a41c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38108
51414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3810851414
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.286688457
Short name T435
Test name
Test status
Simulation time 561438329 ps
CPU time 41.44 seconds
Started Jul 16 05:39:45 PM PDT 24
Finished Jul 16 05:40:28 PM PDT 24
Peak memory 249232 kb
Host smart-2bda9b66-bffe-4e7b-9a8f-f106eae2d10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28668
8457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.286688457
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3642829144
Short name T416
Test name
Test status
Simulation time 327000680 ps
CPU time 20.83 seconds
Started Jul 16 05:39:46 PM PDT 24
Finished Jul 16 05:40:08 PM PDT 24
Peak memory 256376 kb
Host smart-d2221c56-d621-45d8-8581-e229141ab2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36428
29144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3642829144
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1050161953
Short name T77
Test name
Test status
Simulation time 25894191710 ps
CPU time 879.12 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 05:54:37 PM PDT 24
Peak memory 265732 kb
Host smart-88b9132d-e25f-4110-a9e5-ef240f69fe0a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050161953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1050161953
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3901940530
Short name T674
Test name
Test status
Simulation time 48522135717 ps
CPU time 2797.07 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 06:26:35 PM PDT 24
Peak memory 288496 kb
Host smart-c663f9b4-ae1d-4bc7-a213-7bb66cc303d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901940530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3901940530
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1480298882
Short name T360
Test name
Test status
Simulation time 3122929119 ps
CPU time 195.79 seconds
Started Jul 16 05:39:54 PM PDT 24
Finished Jul 16 05:43:12 PM PDT 24
Peak memory 256804 kb
Host smart-cd2c3ba4-b6c2-48d5-9393-5821682c087a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14802
98882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1480298882
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3881401418
Short name T455
Test name
Test status
Simulation time 3521529509 ps
CPU time 45.02 seconds
Started Jul 16 05:39:54 PM PDT 24
Finished Jul 16 05:40:41 PM PDT 24
Peak memory 256628 kb
Host smart-e6b716be-5ef9-43bd-830b-25d97452ecb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38814
01418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3881401418
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.519381746
Short name T291
Test name
Test status
Simulation time 91864852921 ps
CPU time 1402.97 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 06:03:21 PM PDT 24
Peak memory 273560 kb
Host smart-bbaf7cb7-3355-457a-8654-1579d8b5602f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519381746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.519381746
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.731233939
Short name T628
Test name
Test status
Simulation time 46868511879 ps
CPU time 1387.6 seconds
Started Jul 16 05:39:52 PM PDT 24
Finished Jul 16 06:03:02 PM PDT 24
Peak memory 273224 kb
Host smart-53ac5f90-54c5-4e7b-aa64-125b4191693a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731233939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.731233939
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.173282179
Short name T530
Test name
Test status
Simulation time 114419596 ps
CPU time 10.38 seconds
Started Jul 16 05:39:52 PM PDT 24
Finished Jul 16 05:40:04 PM PDT 24
Peak memory 249280 kb
Host smart-658ff50f-b27f-4aab-a274-cc7ae36a6515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17328
2179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.173282179
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2800815887
Short name T558
Test name
Test status
Simulation time 303412237 ps
CPU time 13.61 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 05:40:11 PM PDT 24
Peak memory 248824 kb
Host smart-4e18b322-2681-4133-9a61-75522fa94bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28008
15887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2800815887
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1278043437
Short name T180
Test name
Test status
Simulation time 328609625 ps
CPU time 22.07 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:40:18 PM PDT 24
Peak memory 248692 kb
Host smart-acf46d8f-a1a1-44d8-8d6c-b74f04e49eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12780
43437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1278043437
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.29849797
Short name T409
Test name
Test status
Simulation time 159220823 ps
CPU time 5.2 seconds
Started Jul 16 05:39:54 PM PDT 24
Finished Jul 16 05:40:01 PM PDT 24
Peak memory 249572 kb
Host smart-cf218516-b4f0-4559-8153-c1acc281f3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29849
797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.29849797
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3939046487
Short name T103
Test name
Test status
Simulation time 48379232196 ps
CPU time 4567.18 seconds
Started Jul 16 05:39:54 PM PDT 24
Finished Jul 16 06:56:04 PM PDT 24
Peak memory 322224 kb
Host smart-6e250e53-a2f8-459a-876f-d1aee8e72333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939046487 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3939046487
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.4276098636
Short name T274
Test name
Test status
Simulation time 59720416020 ps
CPU time 1072.31 seconds
Started Jul 16 05:39:54 PM PDT 24
Finished Jul 16 05:57:49 PM PDT 24
Peak memory 273612 kb
Host smart-c2c473d9-38ce-4e30-b97d-0649a96eaf90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276098636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.4276098636
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1375051418
Short name T654
Test name
Test status
Simulation time 3944988902 ps
CPU time 149.73 seconds
Started Jul 16 05:39:52 PM PDT 24
Finished Jul 16 05:42:22 PM PDT 24
Peak memory 257472 kb
Host smart-e03437ed-366b-42ea-9618-ba111d0806e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13750
51418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1375051418
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2062090522
Short name T601
Test name
Test status
Simulation time 1201689575 ps
CPU time 61.64 seconds
Started Jul 16 05:39:54 PM PDT 24
Finished Jul 16 05:40:59 PM PDT 24
Peak memory 249180 kb
Host smart-8e2ea41c-eb10-4aec-92e8-66200d400ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20620
90522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2062090522
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3775305056
Short name T556
Test name
Test status
Simulation time 34568497321 ps
CPU time 1676.32 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 06:07:52 PM PDT 24
Peak memory 289576 kb
Host smart-026bea26-35d2-422c-9dc6-51ace536d65e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775305056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3775305056
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.903369374
Short name T111
Test name
Test status
Simulation time 61217659814 ps
CPU time 703.27 seconds
Started Jul 16 05:39:52 PM PDT 24
Finished Jul 16 05:51:37 PM PDT 24
Peak memory 249356 kb
Host smart-ee35db1f-ded2-4486-a5d2-47e63c7a5a6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903369374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.903369374
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.313106206
Short name T678
Test name
Test status
Simulation time 584195659 ps
CPU time 38.81 seconds
Started Jul 16 05:39:54 PM PDT 24
Finished Jul 16 05:40:35 PM PDT 24
Peak memory 249248 kb
Host smart-1dc5c24c-4e3c-4191-ae6b-8f495e65d8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31310
6206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.313106206
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2679330493
Short name T476
Test name
Test status
Simulation time 2569339030 ps
CPU time 31.32 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:40:26 PM PDT 24
Peak memory 256752 kb
Host smart-9f6ccce9-495b-4f46-b232-a9c9bd3c0930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26793
30493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2679330493
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1992022584
Short name T605
Test name
Test status
Simulation time 363024636 ps
CPU time 24.57 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:40:20 PM PDT 24
Peak memory 249244 kb
Host smart-cac3a00f-7bd8-4a2c-b563-bb651dbd96b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19920
22584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1992022584
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3915288366
Short name T551
Test name
Test status
Simulation time 1645551950 ps
CPU time 25.12 seconds
Started Jul 16 05:39:51 PM PDT 24
Finished Jul 16 05:40:17 PM PDT 24
Peak memory 255884 kb
Host smart-cd18cd7c-e018-4275-abb3-5a4c82111278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39152
88366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3915288366
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1789104907
Short name T50
Test name
Test status
Simulation time 66103485074 ps
CPU time 2159.26 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 06:15:55 PM PDT 24
Peak memory 290380 kb
Host smart-4d5bb160-07a1-4a92-9710-38a79ba8510d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789104907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1789104907
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.762282013
Short name T295
Test name
Test status
Simulation time 133985939602 ps
CPU time 2144.23 seconds
Started Jul 16 05:40:03 PM PDT 24
Finished Jul 16 06:15:49 PM PDT 24
Peak memory 282208 kb
Host smart-577ac739-1eed-405f-aac4-e09453856b47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762282013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.762282013
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3891034462
Short name T447
Test name
Test status
Simulation time 3949907983 ps
CPU time 99.59 seconds
Started Jul 16 05:39:54 PM PDT 24
Finished Jul 16 05:41:36 PM PDT 24
Peak memory 251144 kb
Host smart-88dad6c4-ed72-4493-b61b-590a22776cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38910
34462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3891034462
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1366059737
Short name T229
Test name
Test status
Simulation time 1207216950 ps
CPU time 14.58 seconds
Started Jul 16 05:39:55 PM PDT 24
Finished Jul 16 05:40:12 PM PDT 24
Peak memory 254652 kb
Host smart-d50d6356-5a75-4aea-9b90-ce413c3a1026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13660
59737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1366059737
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.519960758
Short name T524
Test name
Test status
Simulation time 304661546193 ps
CPU time 1366.09 seconds
Started Jul 16 05:40:00 PM PDT 24
Finished Jul 16 06:02:46 PM PDT 24
Peak memory 273924 kb
Host smart-0462547d-832b-4f9a-9579-0ad1361a8004
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519960758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.519960758
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1653893332
Short name T656
Test name
Test status
Simulation time 13810397043 ps
CPU time 1424.27 seconds
Started Jul 16 05:40:03 PM PDT 24
Finished Jul 16 06:03:49 PM PDT 24
Peak memory 289460 kb
Host smart-60e7563c-2cd0-4642-b0a2-bc474f9f2106
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653893332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1653893332
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2570170385
Short name T477
Test name
Test status
Simulation time 54600114291 ps
CPU time 321.33 seconds
Started Jul 16 05:40:03 PM PDT 24
Finished Jul 16 05:45:26 PM PDT 24
Peak memory 255720 kb
Host smart-56ac4f92-29e3-406f-8999-b66f720585fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570170385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2570170385
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3246796066
Short name T106
Test name
Test status
Simulation time 154769247 ps
CPU time 8.19 seconds
Started Jul 16 05:40:02 PM PDT 24
Finished Jul 16 05:40:11 PM PDT 24
Peak memory 249128 kb
Host smart-c2567f13-5381-4a80-94c3-a685b3fb4f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32467
96066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3246796066
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2428199425
Short name T392
Test name
Test status
Simulation time 957026399 ps
CPU time 54.62 seconds
Started Jul 16 05:39:52 PM PDT 24
Finished Jul 16 05:40:48 PM PDT 24
Peak memory 248824 kb
Host smart-bdc4ff9d-242c-4486-a730-c6179a545664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24281
99425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2428199425
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.348354927
Short name T288
Test name
Test status
Simulation time 358129887 ps
CPU time 25 seconds
Started Jul 16 05:39:53 PM PDT 24
Finished Jul 16 05:40:21 PM PDT 24
Peak memory 248776 kb
Host smart-518e86d3-0c97-44ae-bb71-e39a814ed959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34835
4927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.348354927
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3165954937
Short name T639
Test name
Test status
Simulation time 1620444718 ps
CPU time 31.08 seconds
Started Jul 16 05:39:50 PM PDT 24
Finished Jul 16 05:40:21 PM PDT 24
Peak memory 257332 kb
Host smart-0dc4e8c8-0dbb-487f-94ad-20c486ae1b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31659
54937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3165954937
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1683716277
Short name T493
Test name
Test status
Simulation time 30339021221 ps
CPU time 847.32 seconds
Started Jul 16 05:40:03 PM PDT 24
Finished Jul 16 05:54:11 PM PDT 24
Peak memory 273408 kb
Host smart-a149cee6-7452-46d1-bad7-de18c587a05f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683716277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1683716277
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3691155871
Short name T99
Test name
Test status
Simulation time 6023310602 ps
CPU time 590.23 seconds
Started Jul 16 05:40:02 PM PDT 24
Finished Jul 16 05:49:54 PM PDT 24
Peak memory 268796 kb
Host smart-264eb1f9-b3de-49e5-8fe0-fec2c1ae280f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691155871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3691155871
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3717663127
Short name T368
Test name
Test status
Simulation time 7950871866 ps
CPU time 157.09 seconds
Started Jul 16 05:40:01 PM PDT 24
Finished Jul 16 05:42:39 PM PDT 24
Peak memory 257640 kb
Host smart-aafec964-ad81-4fe1-9b9b-66d8dcc147af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37176
63127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3717663127
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1651470472
Short name T645
Test name
Test status
Simulation time 1127670773 ps
CPU time 21.77 seconds
Started Jul 16 05:40:01 PM PDT 24
Finished Jul 16 05:40:24 PM PDT 24
Peak memory 256980 kb
Host smart-42e0e73f-2bb5-46a0-bacb-267358deee43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16514
70472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1651470472
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1469687373
Short name T354
Test name
Test status
Simulation time 62876998567 ps
CPU time 2022.87 seconds
Started Jul 16 05:40:04 PM PDT 24
Finished Jul 16 06:13:48 PM PDT 24
Peak memory 283936 kb
Host smart-0a8852cc-b226-4319-abc1-966f96d5f9f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469687373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1469687373
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1110034538
Short name T271
Test name
Test status
Simulation time 7445042789 ps
CPU time 60.4 seconds
Started Jul 16 05:40:01 PM PDT 24
Finished Jul 16 05:41:03 PM PDT 24
Peak memory 257408 kb
Host smart-82abd635-d52a-41c9-abeb-cdab82f9c97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11100
34538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1110034538
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2817461540
Short name T700
Test name
Test status
Simulation time 432622572 ps
CPU time 32.34 seconds
Started Jul 16 05:40:02 PM PDT 24
Finished Jul 16 05:40:36 PM PDT 24
Peak memory 257148 kb
Host smart-a1a62efe-7403-42d2-903b-82c51bd0145c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28174
61540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2817461540
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.540284264
Short name T600
Test name
Test status
Simulation time 1089644112 ps
CPU time 62.91 seconds
Started Jul 16 05:40:03 PM PDT 24
Finished Jul 16 05:41:07 PM PDT 24
Peak memory 257440 kb
Host smart-87778049-51ea-4617-bb6a-e966917a3361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54028
4264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.540284264
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2233753417
Short name T648
Test name
Test status
Simulation time 268034825 ps
CPU time 31.13 seconds
Started Jul 16 05:40:03 PM PDT 24
Finished Jul 16 05:40:36 PM PDT 24
Peak memory 249224 kb
Host smart-c3a08e4f-3c3e-4eba-b42b-7596f0e1100c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22337
53417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2233753417
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1886229950
Short name T466
Test name
Test status
Simulation time 68374792219 ps
CPU time 1106.78 seconds
Started Jul 16 05:40:01 PM PDT 24
Finished Jul 16 05:58:29 PM PDT 24
Peak memory 284104 kb
Host smart-b27de502-fab2-4025-a01d-6d3acee93448
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886229950 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1886229950
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.541723171
Short name T287
Test name
Test status
Simulation time 169789164691 ps
CPU time 2759.59 seconds
Started Jul 16 05:40:44 PM PDT 24
Finished Jul 16 06:26:45 PM PDT 24
Peak memory 284604 kb
Host smart-f2a6b467-1fa0-407c-88ad-57c5f12af07d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541723171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.541723171
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.4070346665
Short name T670
Test name
Test status
Simulation time 17913872846 ps
CPU time 240.73 seconds
Started Jul 16 05:40:04 PM PDT 24
Finished Jul 16 05:44:05 PM PDT 24
Peak memory 252504 kb
Host smart-a32e0407-3761-48f6-a37b-32e85390b0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40703
46665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.4070346665
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.788418433
Short name T481
Test name
Test status
Simulation time 1251356175 ps
CPU time 34.67 seconds
Started Jul 16 05:40:04 PM PDT 24
Finished Jul 16 05:40:39 PM PDT 24
Peak memory 257428 kb
Host smart-eb6cef75-3d07-46fe-9c9e-13c4ad32cfc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78841
8433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.788418433
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.4020359085
Short name T290
Test name
Test status
Simulation time 80694806572 ps
CPU time 1084.78 seconds
Started Jul 16 05:40:01 PM PDT 24
Finished Jul 16 05:58:07 PM PDT 24
Peak memory 272116 kb
Host smart-8044e48e-f1b3-4771-b14f-8e22345bb9d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020359085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4020359085
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3200704035
Short name T370
Test name
Test status
Simulation time 120862124251 ps
CPU time 1712.33 seconds
Started Jul 16 05:40:01 PM PDT 24
Finished Jul 16 06:08:35 PM PDT 24
Peak memory 269876 kb
Host smart-eee3b6bc-e993-448c-854f-5518c9f15160
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200704035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3200704035
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2406838894
Short name T408
Test name
Test status
Simulation time 363308814 ps
CPU time 9.98 seconds
Started Jul 16 05:40:01 PM PDT 24
Finished Jul 16 05:40:12 PM PDT 24
Peak memory 249280 kb
Host smart-b00eb842-8631-42ac-a0d8-4595481adf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24068
38894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2406838894
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1441276275
Short name T553
Test name
Test status
Simulation time 555853346 ps
CPU time 13.13 seconds
Started Jul 16 05:40:00 PM PDT 24
Finished Jul 16 05:40:15 PM PDT 24
Peak memory 255168 kb
Host smart-d34f086a-70dc-4fee-9d14-12c637cf54f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14412
76275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1441276275
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1269056096
Short name T680
Test name
Test status
Simulation time 162585263 ps
CPU time 6.74 seconds
Started Jul 16 05:40:03 PM PDT 24
Finished Jul 16 05:40:11 PM PDT 24
Peak memory 248520 kb
Host smart-87bedfb0-dec3-4f47-ae76-47edeb6179b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12690
56096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1269056096
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3555168893
Short name T412
Test name
Test status
Simulation time 2985021648 ps
CPU time 33.4 seconds
Started Jul 16 05:40:02 PM PDT 24
Finished Jul 16 05:40:37 PM PDT 24
Peak memory 257288 kb
Host smart-fdefc997-d0d6-4e57-81cf-672a7613676a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35551
68893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3555168893
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2073052890
Short name T252
Test name
Test status
Simulation time 54845299841 ps
CPU time 3739.8 seconds
Started Jul 16 05:40:02 PM PDT 24
Finished Jul 16 06:42:24 PM PDT 24
Peak memory 289808 kb
Host smart-279d65dd-f884-4f6e-9711-3595b17b8d7a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073052890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2073052890
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1403987883
Short name T47
Test name
Test status
Simulation time 10130139577 ps
CPU time 996.49 seconds
Started Jul 16 05:40:03 PM PDT 24
Finished Jul 16 05:56:41 PM PDT 24
Peak memory 290120 kb
Host smart-50463a74-34c5-4c04-972c-0dae9e3e1f05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403987883 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1403987883
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.136359089
Short name T679
Test name
Test status
Simulation time 27200189510 ps
CPU time 1658.14 seconds
Started Jul 16 05:40:13 PM PDT 24
Finished Jul 16 06:07:53 PM PDT 24
Peak memory 290288 kb
Host smart-c56990ba-5a38-4aa7-b84e-6465c496649e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136359089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.136359089
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1812281934
Short name T344
Test name
Test status
Simulation time 3743013686 ps
CPU time 57.11 seconds
Started Jul 16 05:40:14 PM PDT 24
Finished Jul 16 05:41:13 PM PDT 24
Peak memory 257572 kb
Host smart-cdefdd12-1f73-4a0d-ae73-96aa593a1c8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18122
81934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1812281934
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3856966044
Short name T663
Test name
Test status
Simulation time 1440350901 ps
CPU time 33.08 seconds
Started Jul 16 05:40:13 PM PDT 24
Finished Jul 16 05:40:48 PM PDT 24
Peak memory 256532 kb
Host smart-08d311bf-a75d-4e98-8f7e-df59f76c80bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38569
66044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3856966044
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3896526525
Short name T294
Test name
Test status
Simulation time 26139343318 ps
CPU time 865.48 seconds
Started Jul 16 05:40:15 PM PDT 24
Finished Jul 16 05:54:42 PM PDT 24
Peak memory 273852 kb
Host smart-0c8c53b3-955e-4253-bc82-6fd89dbfb9ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896526525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3896526525
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1624744184
Short name T282
Test name
Test status
Simulation time 139164033333 ps
CPU time 2050.36 seconds
Started Jul 16 05:40:11 PM PDT 24
Finished Jul 16 06:14:23 PM PDT 24
Peak memory 273864 kb
Host smart-045f9121-b725-4e5e-93f4-48311caddff2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624744184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1624744184
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.757948765
Short name T64
Test name
Test status
Simulation time 93477321222 ps
CPU time 408.31 seconds
Started Jul 16 05:40:11 PM PDT 24
Finished Jul 16 05:47:01 PM PDT 24
Peak memory 249368 kb
Host smart-f72207c6-6506-4d34-bfbb-5bfc3572498e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757948765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.757948765
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1226406839
Short name T345
Test name
Test status
Simulation time 453967048 ps
CPU time 34.97 seconds
Started Jul 16 05:40:03 PM PDT 24
Finished Jul 16 05:40:39 PM PDT 24
Peak memory 249236 kb
Host smart-d505abb8-97c6-4be5-97a8-f55677310c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12264
06839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1226406839
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3009666170
Short name T413
Test name
Test status
Simulation time 1001718420 ps
CPU time 57.3 seconds
Started Jul 16 05:40:12 PM PDT 24
Finished Jul 16 05:41:11 PM PDT 24
Peak memory 248648 kb
Host smart-cd222d7a-3f04-471e-8537-b873d479ab31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30096
66170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3009666170
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1217806305
Short name T347
Test name
Test status
Simulation time 528481311 ps
CPU time 41.43 seconds
Started Jul 16 05:40:13 PM PDT 24
Finished Jul 16 05:40:56 PM PDT 24
Peak memory 257444 kb
Host smart-514670eb-eeb9-4d19-af51-d3e0d85c009a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12178
06305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1217806305
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1410858911
Short name T565
Test name
Test status
Simulation time 120676916 ps
CPU time 6.84 seconds
Started Jul 16 05:40:02 PM PDT 24
Finished Jul 16 05:40:10 PM PDT 24
Peak memory 249264 kb
Host smart-b8381e19-7221-48a7-b08d-0fd3da7cea67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14108
58911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1410858911
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.988533802
Short name T460
Test name
Test status
Simulation time 14690082911 ps
CPU time 1227.39 seconds
Started Jul 16 05:40:15 PM PDT 24
Finished Jul 16 06:00:44 PM PDT 24
Peak memory 282176 kb
Host smart-2c32b8c3-fdaa-4cd7-8b52-1477c91a4c06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988533802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.988533802
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.154307301
Short name T374
Test name
Test status
Simulation time 4091238990 ps
CPU time 248.46 seconds
Started Jul 16 05:40:13 PM PDT 24
Finished Jul 16 05:44:23 PM PDT 24
Peak memory 257152 kb
Host smart-2e8bdc73-cee7-41c6-a90b-84ece6082a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15430
7301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.154307301
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.4011159955
Short name T644
Test name
Test status
Simulation time 2958243272 ps
CPU time 12.07 seconds
Started Jul 16 05:40:13 PM PDT 24
Finished Jul 16 05:40:27 PM PDT 24
Peak memory 248896 kb
Host smart-1bd44914-792c-4fbb-a7c2-f59e7274e177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40111
59955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4011159955
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1290747433
Short name T423
Test name
Test status
Simulation time 118138247739 ps
CPU time 1737.05 seconds
Started Jul 16 05:40:11 PM PDT 24
Finished Jul 16 06:09:10 PM PDT 24
Peak memory 274016 kb
Host smart-694e7b29-99b9-4a64-93f0-fad174528ccf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290747433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1290747433
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.682961718
Short name T94
Test name
Test status
Simulation time 21934024033 ps
CPU time 1513.28 seconds
Started Jul 16 05:40:13 PM PDT 24
Finished Jul 16 06:05:28 PM PDT 24
Peak memory 273984 kb
Host smart-7aa484d7-a40a-4e03-9d0b-2ff9004980fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682961718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.682961718
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3884483060
Short name T366
Test name
Test status
Simulation time 779829828 ps
CPU time 21.52 seconds
Started Jul 16 05:40:15 PM PDT 24
Finished Jul 16 05:40:38 PM PDT 24
Peak memory 256756 kb
Host smart-13972e45-a532-443e-a341-b81238b1695a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38844
83060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3884483060
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1159453222
Short name T569
Test name
Test status
Simulation time 701844427 ps
CPU time 22 seconds
Started Jul 16 05:40:13 PM PDT 24
Finished Jul 16 05:40:37 PM PDT 24
Peak memory 256896 kb
Host smart-8906f51e-4e22-4d27-8902-b826af7a0642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11594
53222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1159453222
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3398246772
Short name T422
Test name
Test status
Simulation time 180903022 ps
CPU time 7.11 seconds
Started Jul 16 05:40:11 PM PDT 24
Finished Jul 16 05:40:20 PM PDT 24
Peak memory 255876 kb
Host smart-ece761f5-8ba7-4ef4-a5fe-14881334ecc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33982
46772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3398246772
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.3295087689
Short name T441
Test name
Test status
Simulation time 1399576259 ps
CPU time 42.23 seconds
Started Jul 16 05:40:11 PM PDT 24
Finished Jul 16 05:40:55 PM PDT 24
Peak memory 249296 kb
Host smart-25871148-1060-47e2-9622-b7a6a7736ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32950
87689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.3295087689
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3581751267
Short name T268
Test name
Test status
Simulation time 32721393195 ps
CPU time 1363.23 seconds
Started Jul 16 05:40:14 PM PDT 24
Finished Jul 16 06:02:59 PM PDT 24
Peak memory 289696 kb
Host smart-0c552fd9-e3d5-4d99-9676-371cea7fb021
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581751267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3581751267
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.4224608528
Short name T201
Test name
Test status
Simulation time 150581798 ps
CPU time 3.84 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:39:17 PM PDT 24
Peak memory 249572 kb
Host smart-f4ba48b3-46d8-4d56-bf50-a8654b96b292
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4224608528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4224608528
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2203001732
Short name T296
Test name
Test status
Simulation time 57446453199 ps
CPU time 2712.17 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 06:24:27 PM PDT 24
Peak memory 288028 kb
Host smart-970d21d8-77d5-4471-b2af-9d91b6fcca12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203001732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2203001732
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2256761694
Short name T361
Test name
Test status
Simulation time 2870264524 ps
CPU time 22.34 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 05:39:37 PM PDT 24
Peak memory 249392 kb
Host smart-9dbc8ac6-49fc-4ad3-b80d-d490268f6eab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2256761694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2256761694
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1244098649
Short name T531
Test name
Test status
Simulation time 1692183691 ps
CPU time 83.61 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 05:40:33 PM PDT 24
Peak memory 256908 kb
Host smart-f41de51d-cdf3-427a-ac5f-bd6bc20ac918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12440
98649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1244098649
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2181156555
Short name T21
Test name
Test status
Simulation time 337893940 ps
CPU time 35.01 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:39:48 PM PDT 24
Peak memory 249820 kb
Host smart-d6bab99f-b10f-4ec7-bda0-d37a6b8f5318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21811
56555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2181156555
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2592679995
Short name T547
Test name
Test status
Simulation time 122564400594 ps
CPU time 1892.78 seconds
Started Jul 16 05:39:10 PM PDT 24
Finished Jul 16 06:10:44 PM PDT 24
Peak memory 273604 kb
Host smart-2b99bd64-f5a5-476b-bf72-0ee8002a81a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592679995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2592679995
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1646673639
Short name T222
Test name
Test status
Simulation time 30115504106 ps
CPU time 334.31 seconds
Started Jul 16 05:39:10 PM PDT 24
Finished Jul 16 05:44:45 PM PDT 24
Peak memory 249396 kb
Host smart-7345bf44-d32e-4eee-9384-22c3a1005edd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646673639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1646673639
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4109696252
Short name T604
Test name
Test status
Simulation time 3124413364 ps
CPU time 25.01 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 05:39:35 PM PDT 24
Peak memory 256480 kb
Host smart-478c2d45-0060-46b9-a513-d8d9722ddaa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41096
96252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4109696252
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.4040755742
Short name T464
Test name
Test status
Simulation time 45920391 ps
CPU time 4.15 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 05:39:14 PM PDT 24
Peak memory 240636 kb
Host smart-6df998f5-1912-45f3-9f77-089f333312f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40407
55742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.4040755742
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2783732027
Short name T25
Test name
Test status
Simulation time 1009402978 ps
CPU time 56.63 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 05:40:06 PM PDT 24
Peak memory 257316 kb
Host smart-cfceae80-19b6-4bcc-8c30-1ea1ab044f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27837
32027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2783732027
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3018080960
Short name T503
Test name
Test status
Simulation time 459086412 ps
CPU time 42.61 seconds
Started Jul 16 05:39:15 PM PDT 24
Finished Jul 16 05:39:59 PM PDT 24
Peak memory 256212 kb
Host smart-d82fcca1-0622-4358-b29d-14989579ddda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30180
80960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3018080960
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1310843158
Short name T586
Test name
Test status
Simulation time 656781525 ps
CPU time 25.86 seconds
Started Jul 16 05:39:14 PM PDT 24
Finished Jul 16 05:39:41 PM PDT 24
Peak memory 249016 kb
Host smart-57c0314f-d7db-4c0e-9ad8-80c8e28bf624
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310843158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1310843158
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1243897740
Short name T234
Test name
Test status
Simulation time 68698878615 ps
CPU time 2366.49 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 06:18:37 PM PDT 24
Peak memory 279492 kb
Host smart-7d4adb0d-4c9f-4353-8c87-38e550de5336
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243897740 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1243897740
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3017444005
Short name T693
Test name
Test status
Simulation time 290405296546 ps
CPU time 3123.53 seconds
Started Jul 16 05:40:14 PM PDT 24
Finished Jul 16 06:32:20 PM PDT 24
Peak memory 290004 kb
Host smart-872ccd24-c36f-4ba8-a079-8fc947efba27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017444005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3017444005
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1783196752
Short name T582
Test name
Test status
Simulation time 513616382 ps
CPU time 18.11 seconds
Started Jul 16 05:40:11 PM PDT 24
Finished Jul 16 05:40:31 PM PDT 24
Peak memory 256312 kb
Host smart-807246f0-c552-4dac-815b-b30104e93ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17831
96752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1783196752
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.400109906
Short name T440
Test name
Test status
Simulation time 2406247801 ps
CPU time 40.99 seconds
Started Jul 16 05:40:19 PM PDT 24
Finished Jul 16 05:41:00 PM PDT 24
Peak memory 248664 kb
Host smart-a75b7a94-e0b7-4840-a077-ced24ddfd7a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40010
9906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.400109906
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.127482206
Short name T657
Test name
Test status
Simulation time 21414351206 ps
CPU time 967.76 seconds
Started Jul 16 05:40:12 PM PDT 24
Finished Jul 16 05:56:21 PM PDT 24
Peak memory 282068 kb
Host smart-3472fa10-7db6-45b3-a9f2-cc8d1f791341
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127482206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.127482206
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1942053524
Short name T591
Test name
Test status
Simulation time 25209248497 ps
CPU time 1032.6 seconds
Started Jul 16 05:40:19 PM PDT 24
Finished Jul 16 05:57:32 PM PDT 24
Peak memory 281808 kb
Host smart-ff0d355b-9716-4d25-b4ba-44070eedaba2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942053524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1942053524
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2267956298
Short name T576
Test name
Test status
Simulation time 4000562156 ps
CPU time 146.36 seconds
Started Jul 16 05:40:15 PM PDT 24
Finished Jul 16 05:42:43 PM PDT 24
Peak memory 255792 kb
Host smart-e685eb39-a150-44d2-b91a-21b9f32eb348
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267956298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2267956298
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.350802847
Short name T2
Test name
Test status
Simulation time 3901956304 ps
CPU time 50.56 seconds
Started Jul 16 05:40:14 PM PDT 24
Finished Jul 16 05:41:07 PM PDT 24
Peak memory 257020 kb
Host smart-dbe843b3-5118-47c5-a591-8d656ac128dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35080
2847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.350802847
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2818940600
Short name T479
Test name
Test status
Simulation time 3680073636 ps
CPU time 68.02 seconds
Started Jul 16 05:40:12 PM PDT 24
Finished Jul 16 05:41:21 PM PDT 24
Peak memory 257584 kb
Host smart-f447419d-cf3a-49cd-9fa4-e4c717a14df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28189
40600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2818940600
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1364493844
Short name T115
Test name
Test status
Simulation time 11138275785 ps
CPU time 46.35 seconds
Started Jul 16 05:40:13 PM PDT 24
Finished Jul 16 05:41:01 PM PDT 24
Peak memory 249364 kb
Host smart-3103219e-b656-4171-819c-c154edc4cc78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13644
93844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1364493844
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1102070378
Short name T18
Test name
Test status
Simulation time 502108664 ps
CPU time 31.71 seconds
Started Jul 16 05:40:13 PM PDT 24
Finished Jul 16 05:40:46 PM PDT 24
Peak memory 257396 kb
Host smart-521e0ec4-6807-4014-ad27-bcf0fbf37e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11020
70378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1102070378
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2137631396
Short name T254
Test name
Test status
Simulation time 51354112327 ps
CPU time 3007.47 seconds
Started Jul 16 05:40:15 PM PDT 24
Finished Jul 16 06:30:24 PM PDT 24
Peak memory 290288 kb
Host smart-e5627818-6b9a-4063-954d-4290fd16dc18
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137631396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2137631396
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2034644659
Short name T362
Test name
Test status
Simulation time 153033492022 ps
CPU time 2813.06 seconds
Started Jul 16 05:40:32 PM PDT 24
Finished Jul 16 06:27:26 PM PDT 24
Peak memory 288960 kb
Host smart-a5369817-a38d-4eeb-a5bb-4b510c17c8cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034644659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2034644659
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3630550085
Short name T349
Test name
Test status
Simulation time 17606887373 ps
CPU time 242.87 seconds
Started Jul 16 05:40:22 PM PDT 24
Finished Jul 16 05:44:26 PM PDT 24
Peak memory 256772 kb
Host smart-2e2b0102-2d64-41d8-94b0-53db78b5f10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36305
50085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3630550085
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1123831206
Short name T513
Test name
Test status
Simulation time 93855671 ps
CPU time 8.44 seconds
Started Jul 16 05:40:26 PM PDT 24
Finished Jul 16 05:40:35 PM PDT 24
Peak memory 249316 kb
Host smart-a074a12b-6248-43d8-9446-a24dafebf678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11238
31206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1123831206
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.4164851629
Short name T218
Test name
Test status
Simulation time 893398771219 ps
CPU time 3146.48 seconds
Started Jul 16 05:40:22 PM PDT 24
Finished Jul 16 06:32:50 PM PDT 24
Peak memory 282140 kb
Host smart-811c1a2f-6b31-4dbf-b73d-b69207435201
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164851629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.4164851629
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.423168451
Short name T691
Test name
Test status
Simulation time 46427354851 ps
CPU time 1171.17 seconds
Started Jul 16 05:40:21 PM PDT 24
Finished Jul 16 05:59:53 PM PDT 24
Peak memory 273000 kb
Host smart-7e8bf337-8107-4054-83ad-43288ba47124
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423168451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.423168451
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2841153880
Short name T673
Test name
Test status
Simulation time 42826415842 ps
CPU time 472.97 seconds
Started Jul 16 05:40:21 PM PDT 24
Finished Jul 16 05:48:15 PM PDT 24
Peak memory 249388 kb
Host smart-b72c8899-151a-472a-bd66-09c86d4b50cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841153880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2841153880
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.4122658890
Short name T651
Test name
Test status
Simulation time 197528663 ps
CPU time 20.25 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 05:40:45 PM PDT 24
Peak memory 249248 kb
Host smart-f90def61-43b3-4389-a504-5a3f4b2ea5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41226
58890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.4122658890
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4244975233
Short name T431
Test name
Test status
Simulation time 54449714 ps
CPU time 4.44 seconds
Started Jul 16 05:40:21 PM PDT 24
Finished Jul 16 05:40:26 PM PDT 24
Peak memory 240388 kb
Host smart-05200a9b-c383-4750-8812-f55afd92d3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42449
75233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4244975233
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1891816777
Short name T407
Test name
Test status
Simulation time 2921177892 ps
CPU time 49.29 seconds
Started Jul 16 05:40:22 PM PDT 24
Finished Jul 16 05:41:12 PM PDT 24
Peak memory 256432 kb
Host smart-b2dff454-9244-4d25-a1fe-56b3d42e4919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18918
16777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1891816777
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.541944816
Short name T593
Test name
Test status
Simulation time 276091420156 ps
CPU time 4218.38 seconds
Started Jul 16 05:40:25 PM PDT 24
Finished Jul 16 06:50:45 PM PDT 24
Peak memory 304732 kb
Host smart-224b3cb2-85dd-4351-9e80-f0f88873580d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541944816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.541944816
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1486607341
Short name T698
Test name
Test status
Simulation time 64940284087 ps
CPU time 6095.32 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 07:22:01 PM PDT 24
Peak memory 321084 kb
Host smart-c49d0818-41ce-4262-9674-7f68b1ccba09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486607341 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1486607341
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2047867547
Short name T621
Test name
Test status
Simulation time 94961209446 ps
CPU time 1683.81 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 06:08:29 PM PDT 24
Peak memory 282060 kb
Host smart-f7f7df87-dd0e-48c9-8632-5f8a924f064c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047867547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2047867547
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.548509247
Short name T671
Test name
Test status
Simulation time 4166831507 ps
CPU time 87.75 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 05:42:20 PM PDT 24
Peak memory 257528 kb
Host smart-0aff35a3-e8f7-4467-8925-3face73e8e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54850
9247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.548509247
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.298410601
Short name T595
Test name
Test status
Simulation time 3852052920 ps
CPU time 52.52 seconds
Started Jul 16 05:40:23 PM PDT 24
Finished Jul 16 05:41:16 PM PDT 24
Peak memory 249308 kb
Host smart-89d3ffef-a0cc-4a89-9f35-333cd02e860c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29841
0601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.298410601
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3418873532
Short name T702
Test name
Test status
Simulation time 20606846481 ps
CPU time 1452.25 seconds
Started Jul 16 05:40:22 PM PDT 24
Finished Jul 16 06:04:35 PM PDT 24
Peak memory 289528 kb
Host smart-5ac6c35e-139b-4ac8-8277-b369eef83ba4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418873532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3418873532
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1233059425
Short name T14
Test name
Test status
Simulation time 11365294034 ps
CPU time 1406.43 seconds
Started Jul 16 05:40:35 PM PDT 24
Finished Jul 16 06:04:03 PM PDT 24
Peak memory 290072 kb
Host smart-e3bde59b-7c1f-482f-af6a-d9fd16dcb8ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233059425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1233059425
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2260505412
Short name T183
Test name
Test status
Simulation time 38572153288 ps
CPU time 415.07 seconds
Started Jul 16 05:40:22 PM PDT 24
Finished Jul 16 05:47:18 PM PDT 24
Peak memory 249352 kb
Host smart-10969636-1262-41d5-a7bf-6dd11ba85653
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260505412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2260505412
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2718348039
Short name T463
Test name
Test status
Simulation time 433424064 ps
CPU time 10.12 seconds
Started Jul 16 05:40:21 PM PDT 24
Finished Jul 16 05:40:32 PM PDT 24
Peak memory 253932 kb
Host smart-ecd16909-4bb3-4400-b373-c070de5ff0e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27183
48039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2718348039
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.4145968237
Short name T548
Test name
Test status
Simulation time 885616683 ps
CPU time 50.56 seconds
Started Jul 16 05:40:26 PM PDT 24
Finished Jul 16 05:41:17 PM PDT 24
Peak memory 256872 kb
Host smart-4023c537-86fe-4205-8dbf-aead281d9d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41459
68237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.4145968237
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2001866557
Short name T256
Test name
Test status
Simulation time 894792753 ps
CPU time 27.77 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 05:40:53 PM PDT 24
Peak memory 248828 kb
Host smart-c4df0b78-04a6-4031-9e49-40645ea439df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20018
66557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2001866557
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2940225403
Short name T626
Test name
Test status
Simulation time 1698691841 ps
CPU time 13.98 seconds
Started Jul 16 05:40:21 PM PDT 24
Finished Jul 16 05:40:36 PM PDT 24
Peak memory 255912 kb
Host smart-db5bc959-e717-4f90-b253-6e7581df29e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29402
25403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2940225403
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.4111723466
Short name T473
Test name
Test status
Simulation time 27559061951 ps
CPU time 1653.36 seconds
Started Jul 16 05:40:20 PM PDT 24
Finished Jul 16 06:07:54 PM PDT 24
Peak memory 290064 kb
Host smart-a2f12941-28d6-475f-9456-8271ee793271
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111723466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4111723466
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.967448351
Short name T590
Test name
Test status
Simulation time 182611433 ps
CPU time 10.77 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 05:40:36 PM PDT 24
Peak memory 255516 kb
Host smart-a1a7fb83-2e67-4d1c-a330-6f35dbc76623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96744
8351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.967448351
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3017215209
Short name T461
Test name
Test status
Simulation time 306665899 ps
CPU time 22.45 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 05:41:15 PM PDT 24
Peak memory 256980 kb
Host smart-41369d69-3f3f-430c-9b89-a394a465627c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30172
15209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3017215209
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.702480106
Short name T561
Test name
Test status
Simulation time 126500627910 ps
CPU time 1980 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 06:13:26 PM PDT 24
Peak memory 282144 kb
Host smart-c0739f04-92eb-45a4-ad37-580081cfde2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702480106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.702480106
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1964248317
Short name T538
Test name
Test status
Simulation time 5574156448 ps
CPU time 228.99 seconds
Started Jul 16 05:40:23 PM PDT 24
Finished Jul 16 05:44:13 PM PDT 24
Peak memory 249352 kb
Host smart-b94066b4-1e49-4c13-82b0-ac8fb047ea36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964248317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1964248317
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.136436823
Short name T540
Test name
Test status
Simulation time 966871273 ps
CPU time 23.02 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 05:41:16 PM PDT 24
Peak memory 249156 kb
Host smart-295d0211-85fa-43f4-8594-de0e0e97e2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13643
6823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.136436823
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.4260124916
Short name T584
Test name
Test status
Simulation time 3406367143 ps
CPU time 26.01 seconds
Started Jul 16 05:40:23 PM PDT 24
Finished Jul 16 05:40:50 PM PDT 24
Peak memory 257052 kb
Host smart-2375c941-0970-445f-8e78-5bb86ff30827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42601
24916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.4260124916
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.289581131
Short name T515
Test name
Test status
Simulation time 2438144419 ps
CPU time 33.02 seconds
Started Jul 16 05:40:22 PM PDT 24
Finished Jul 16 05:40:55 PM PDT 24
Peak memory 257484 kb
Host smart-85c1bad3-2995-48fb-adb8-a56ab255ef16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28958
1131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.289581131
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1398319974
Short name T443
Test name
Test status
Simulation time 57344277178 ps
CPU time 3271.55 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 06:35:25 PM PDT 24
Peak memory 290188 kb
Host smart-8ec9ec49-c5ac-471d-b3ae-d3b3860e405a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398319974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1398319974
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3892238308
Short name T694
Test name
Test status
Simulation time 154296972685 ps
CPU time 2598.64 seconds
Started Jul 16 05:40:25 PM PDT 24
Finished Jul 16 06:23:45 PM PDT 24
Peak memory 290076 kb
Host smart-720e5cdb-961a-49bc-8e9a-a13b5dd4c81f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892238308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3892238308
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2534314916
Short name T560
Test name
Test status
Simulation time 1011570196 ps
CPU time 42.39 seconds
Started Jul 16 05:40:30 PM PDT 24
Finished Jul 16 05:41:13 PM PDT 24
Peak memory 257344 kb
Host smart-a0bd1bcd-df41-4f4e-b6ab-bedfe2c71379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25343
14916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2534314916
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2435083985
Short name T508
Test name
Test status
Simulation time 209313419 ps
CPU time 21.18 seconds
Started Jul 16 05:40:23 PM PDT 24
Finished Jul 16 05:40:44 PM PDT 24
Peak memory 248960 kb
Host smart-9fe9abee-4ab5-4ae3-8f5a-d73356d2c210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24350
83985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2435083985
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1454575216
Short name T684
Test name
Test status
Simulation time 12411923582 ps
CPU time 1250.57 seconds
Started Jul 16 05:40:36 PM PDT 24
Finished Jul 16 06:01:28 PM PDT 24
Peak memory 286956 kb
Host smart-71155076-6b12-4d8c-9280-42efbdea4f60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454575216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1454575216
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4168565843
Short name T498
Test name
Test status
Simulation time 25848959019 ps
CPU time 1152.67 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 05:59:38 PM PDT 24
Peak memory 282120 kb
Host smart-f7c487bf-4269-482d-bd57-54491f47194a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168565843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4168565843
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2747053006
Short name T685
Test name
Test status
Simulation time 5839378957 ps
CPU time 256.11 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 05:44:41 PM PDT 24
Peak memory 249352 kb
Host smart-21bf713e-b4ac-4abe-bfeb-717d0721ac30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747053006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2747053006
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2386883557
Short name T711
Test name
Test status
Simulation time 188423747 ps
CPU time 16.28 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 05:40:42 PM PDT 24
Peak memory 249232 kb
Host smart-e590ad66-30c3-4a23-a51b-699a32b90a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23868
83557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2386883557
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1807438958
Short name T42
Test name
Test status
Simulation time 648074716 ps
CPU time 37.89 seconds
Started Jul 16 05:40:23 PM PDT 24
Finished Jul 16 05:41:02 PM PDT 24
Peak memory 249300 kb
Host smart-41fb66b6-d810-4d62-9c1b-6078d494c7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18074
38958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1807438958
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1216676017
Short name T467
Test name
Test status
Simulation time 327852446 ps
CPU time 23.74 seconds
Started Jul 16 05:40:22 PM PDT 24
Finished Jul 16 05:40:46 PM PDT 24
Peak memory 248600 kb
Host smart-aa09509d-f96b-4aaf-a8ae-5bc0a160b9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12166
76017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1216676017
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.914314397
Short name T587
Test name
Test status
Simulation time 38014065 ps
CPU time 2.89 seconds
Started Jul 16 05:40:25 PM PDT 24
Finished Jul 16 05:40:29 PM PDT 24
Peak memory 249164 kb
Host smart-c11981d5-c3cb-487d-a6c6-63ec74b7b09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91431
4397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.914314397
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2369682878
Short name T184
Test name
Test status
Simulation time 136707501962 ps
CPU time 7320.82 seconds
Started Jul 16 05:40:35 PM PDT 24
Finished Jul 16 07:42:38 PM PDT 24
Peak memory 395216 kb
Host smart-ccbbfd10-8221-451f-9b69-76d47ef0ffa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369682878 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2369682878
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.485881940
Short name T380
Test name
Test status
Simulation time 92250898770 ps
CPU time 1880.73 seconds
Started Jul 16 05:40:23 PM PDT 24
Finished Jul 16 06:11:44 PM PDT 24
Peak memory 289760 kb
Host smart-6ae2a5ec-f5a3-42ad-96c0-7f99b6a1a84f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485881940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.485881940
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.4001865439
Short name T709
Test name
Test status
Simulation time 1338236850 ps
CPU time 19.03 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 05:40:44 PM PDT 24
Peak memory 248840 kb
Host smart-2d02c475-df18-414f-bb02-329cda2ece05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40018
65439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.4001865439
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2573091705
Short name T588
Test name
Test status
Simulation time 115210376 ps
CPU time 12.99 seconds
Started Jul 16 05:40:35 PM PDT 24
Finished Jul 16 05:40:50 PM PDT 24
Peak memory 249196 kb
Host smart-17f48c64-bec8-4c9d-a715-b95f72d4138b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25730
91705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2573091705
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2545033081
Short name T322
Test name
Test status
Simulation time 53816642198 ps
CPU time 1926.45 seconds
Started Jul 16 05:40:26 PM PDT 24
Finished Jul 16 06:12:33 PM PDT 24
Peak memory 273668 kb
Host smart-5a4d59b0-36c1-499d-9a9b-3a525ad1cef4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545033081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2545033081
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3555089286
Short name T471
Test name
Test status
Simulation time 49419954915 ps
CPU time 2986.46 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 06:30:11 PM PDT 24
Peak memory 287908 kb
Host smart-e104ea31-ac0d-42ce-9342-a204d9218090
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555089286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3555089286
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2550747201
Short name T303
Test name
Test status
Simulation time 13255179619 ps
CPU time 528.96 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 05:49:13 PM PDT 24
Peak memory 249396 kb
Host smart-bc41b87e-9563-434e-a8f2-5f58582b56fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550747201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2550747201
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3825344319
Short name T500
Test name
Test status
Simulation time 1226660104 ps
CPU time 31.88 seconds
Started Jul 16 05:40:25 PM PDT 24
Finished Jul 16 05:40:58 PM PDT 24
Peak memory 257480 kb
Host smart-0ee9c852-4588-43c5-a95d-f132100deab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38253
44319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3825344319
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2589754648
Short name T706
Test name
Test status
Simulation time 883088741 ps
CPU time 45.82 seconds
Started Jul 16 05:40:24 PM PDT 24
Finished Jul 16 05:41:11 PM PDT 24
Peak memory 248572 kb
Host smart-4c4604ea-69fd-456a-a080-2ddae142d56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25897
54648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2589754648
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1326011193
Short name T519
Test name
Test status
Simulation time 474860143 ps
CPU time 27.37 seconds
Started Jul 16 05:40:22 PM PDT 24
Finished Jul 16 05:40:50 PM PDT 24
Peak memory 256488 kb
Host smart-47614947-f665-42e4-805c-3b14ba61549d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13260
11193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1326011193
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2068269843
Short name T39
Test name
Test status
Simulation time 22776444476 ps
CPU time 761.62 seconds
Started Jul 16 05:40:32 PM PDT 24
Finished Jul 16 05:53:15 PM PDT 24
Peak memory 265648 kb
Host smart-16d55490-88d0-4fc0-973e-61c45ed790eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068269843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2068269843
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.681948229
Short name T88
Test name
Test status
Simulation time 201287561719 ps
CPU time 3254.7 seconds
Started Jul 16 05:40:23 PM PDT 24
Finished Jul 16 06:34:39 PM PDT 24
Peak memory 306108 kb
Host smart-49a5c199-3006-4950-9593-a8c83ef5aec4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681948229 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.681948229
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2397601475
Short name T607
Test name
Test status
Simulation time 420478525326 ps
CPU time 3532.72 seconds
Started Jul 16 05:40:32 PM PDT 24
Finished Jul 16 06:39:26 PM PDT 24
Peak memory 289180 kb
Host smart-e0bcf44a-a56d-49aa-942a-20783140909e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397601475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2397601475
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.668067398
Short name T474
Test name
Test status
Simulation time 10114295960 ps
CPU time 113.97 seconds
Started Jul 16 05:40:33 PM PDT 24
Finished Jul 16 05:42:27 PM PDT 24
Peak memory 251672 kb
Host smart-b565bd43-864d-4878-9958-8f73dfacc6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66806
7398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.668067398
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1537223886
Short name T69
Test name
Test status
Simulation time 1576568963 ps
CPU time 53.28 seconds
Started Jul 16 05:40:33 PM PDT 24
Finished Jul 16 05:41:27 PM PDT 24
Peak memory 249844 kb
Host smart-2377f3d9-a03e-4600-aadb-6bbb6c575540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15372
23886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1537223886
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3398706085
Short name T611
Test name
Test status
Simulation time 11114823431 ps
CPU time 1218.96 seconds
Started Jul 16 05:40:36 PM PDT 24
Finished Jul 16 06:00:56 PM PDT 24
Peak memory 286156 kb
Host smart-7f073faa-eb4d-4800-8299-1e6e5bd0a6d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398706085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3398706085
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.759291316
Short name T70
Test name
Test status
Simulation time 11728981120 ps
CPU time 1390.39 seconds
Started Jul 16 05:40:37 PM PDT 24
Finished Jul 16 06:03:48 PM PDT 24
Peak memory 290204 kb
Host smart-8ddda533-c004-427d-84b0-887c0c654576
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759291316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.759291316
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3702036216
Short name T426
Test name
Test status
Simulation time 273495363 ps
CPU time 8 seconds
Started Jul 16 05:40:25 PM PDT 24
Finished Jul 16 05:40:34 PM PDT 24
Peak memory 249212 kb
Host smart-519e835c-c786-4491-8527-a48ea80e7deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37020
36216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3702036216
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1505916049
Short name T1
Test name
Test status
Simulation time 1028513580 ps
CPU time 34.79 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 05:41:28 PM PDT 24
Peak memory 248484 kb
Host smart-ac09e85d-728b-494a-9c3c-b4af6a649f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15059
16049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1505916049
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.305884469
Short name T267
Test name
Test status
Simulation time 891352366 ps
CPU time 52.16 seconds
Started Jul 16 05:41:59 PM PDT 24
Finished Jul 16 05:42:54 PM PDT 24
Peak memory 257420 kb
Host smart-99bcded3-a11b-4eed-bec8-a971bbbe1fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30588
4469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.305884469
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.20879399
Short name T263
Test name
Test status
Simulation time 95617553296 ps
CPU time 1503.35 seconds
Started Jul 16 05:40:34 PM PDT 24
Finished Jul 16 06:05:39 PM PDT 24
Peak memory 265820 kb
Host smart-9453dfa3-c4a1-48b9-aed6-266e3caf81e5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20879399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_hand
ler_stress_all.20879399
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.350439109
Short name T95
Test name
Test status
Simulation time 177274798240 ps
CPU time 4124.12 seconds
Started Jul 16 05:40:31 PM PDT 24
Finished Jul 16 06:49:16 PM PDT 24
Peak memory 338972 kb
Host smart-a809a1fb-3c4e-47e6-8b81-ef9278cf5734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350439109 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.350439109
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1260511996
Short name T510
Test name
Test status
Simulation time 125786278682 ps
CPU time 1713.4 seconds
Started Jul 16 05:40:36 PM PDT 24
Finished Jul 16 06:09:11 PM PDT 24
Peak memory 274012 kb
Host smart-dfff097d-7e15-43b5-80bd-de0283de3a48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260511996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1260511996
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3294554784
Short name T491
Test name
Test status
Simulation time 12767458610 ps
CPU time 140.54 seconds
Started Jul 16 05:40:32 PM PDT 24
Finished Jul 16 05:42:54 PM PDT 24
Peak memory 252528 kb
Host smart-4a1d8ac8-7582-4b65-8276-011e763420f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32945
54784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3294554784
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1364889534
Short name T231
Test name
Test status
Simulation time 411639290 ps
CPU time 32.51 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 05:41:25 PM PDT 24
Peak memory 256864 kb
Host smart-1a3c87fe-f10d-4b49-ab30-92ab913639c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13648
89534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1364889534
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.307469749
Short name T521
Test name
Test status
Simulation time 36676515461 ps
CPU time 1118.74 seconds
Started Jul 16 05:40:36 PM PDT 24
Finished Jul 16 05:59:16 PM PDT 24
Peak memory 273788 kb
Host smart-7f3457d4-78ef-4018-a130-ada3e7971f76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307469749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.307469749
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2895064978
Short name T549
Test name
Test status
Simulation time 17534770550 ps
CPU time 1127.99 seconds
Started Jul 16 05:40:34 PM PDT 24
Finished Jul 16 05:59:24 PM PDT 24
Peak memory 285424 kb
Host smart-3f470352-f81f-4f76-92a8-a975e479bb41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895064978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2895064978
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.969629214
Short name T432
Test name
Test status
Simulation time 257746904 ps
CPU time 17.12 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 05:41:10 PM PDT 24
Peak memory 249224 kb
Host smart-05a81435-1e7b-40d7-85a6-59770685c960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96962
9214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.969629214
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3561941063
Short name T59
Test name
Test status
Simulation time 4831870569 ps
CPU time 78.85 seconds
Started Jul 16 05:40:33 PM PDT 24
Finished Jul 16 05:41:52 PM PDT 24
Peak memory 248920 kb
Host smart-9f577c9c-33ee-491b-86da-43f6883a68ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35619
41063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3561941063
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1676283409
Short name T74
Test name
Test status
Simulation time 155806956 ps
CPU time 9.53 seconds
Started Jul 16 05:40:34 PM PDT 24
Finished Jul 16 05:40:44 PM PDT 24
Peak memory 248920 kb
Host smart-a30ec6b0-5573-4471-9a4c-2624951c789c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16762
83409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1676283409
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1366430616
Short name T384
Test name
Test status
Simulation time 53268579 ps
CPU time 5.99 seconds
Started Jul 16 05:40:32 PM PDT 24
Finished Jul 16 05:40:38 PM PDT 24
Peak memory 252032 kb
Host smart-ad2139bb-c5bc-46a4-a0d7-09c03b75057e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13664
30616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1366430616
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2120861716
Short name T536
Test name
Test status
Simulation time 1467770514 ps
CPU time 143.75 seconds
Started Jul 16 05:40:35 PM PDT 24
Finished Jul 16 05:43:00 PM PDT 24
Peak memory 256444 kb
Host smart-21cc0ecf-6fd7-4237-9043-b48ad7747746
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120861716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2120861716
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1967423036
Short name T527
Test name
Test status
Simulation time 35888717599 ps
CPU time 2514.41 seconds
Started Jul 16 05:40:33 PM PDT 24
Finished Jul 16 06:22:28 PM PDT 24
Peak memory 289932 kb
Host smart-cdcc562b-b800-453b-be33-7ca912798595
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967423036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1967423036
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1232013533
Short name T699
Test name
Test status
Simulation time 18844659408 ps
CPU time 110.48 seconds
Started Jul 16 05:40:33 PM PDT 24
Finished Jul 16 05:42:24 PM PDT 24
Peak memory 257524 kb
Host smart-a45b7fd9-2d56-41c6-8c83-dbb945e88a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12320
13533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1232013533
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2829321969
Short name T499
Test name
Test status
Simulation time 1666067263 ps
CPU time 26.98 seconds
Started Jul 16 05:40:32 PM PDT 24
Finished Jul 16 05:41:00 PM PDT 24
Peak memory 256920 kb
Host smart-6646bc9a-b33f-4ffc-b4f2-5eb7ec1d75df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28293
21969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2829321969
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.656507590
Short name T635
Test name
Test status
Simulation time 67147656941 ps
CPU time 1932.27 seconds
Started Jul 16 05:40:34 PM PDT 24
Finished Jul 16 06:12:48 PM PDT 24
Peak memory 273276 kb
Host smart-a640e330-c2b2-4902-b663-239e95a4cbb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656507590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.656507590
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3527654567
Short name T270
Test name
Test status
Simulation time 32078598436 ps
CPU time 1477.29 seconds
Started Jul 16 05:40:35 PM PDT 24
Finished Jul 16 06:05:14 PM PDT 24
Peak memory 273448 kb
Host smart-1913d15b-5430-451a-973a-46ac696e3d97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527654567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3527654567
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3389828038
Short name T395
Test name
Test status
Simulation time 35506493069 ps
CPU time 380.5 seconds
Started Jul 16 05:40:34 PM PDT 24
Finished Jul 16 05:46:55 PM PDT 24
Peak memory 256420 kb
Host smart-d54c7d90-b526-4fc0-8bee-689cd2fe8dc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389828038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3389828038
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1044724237
Short name T340
Test name
Test status
Simulation time 2658348351 ps
CPU time 29.59 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 05:41:22 PM PDT 24
Peak memory 256620 kb
Host smart-38c7dffe-1704-4aad-a630-506ef00fe116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10447
24237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1044724237
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.713678112
Short name T615
Test name
Test status
Simulation time 202060674 ps
CPU time 14.5 seconds
Started Jul 16 05:40:35 PM PDT 24
Finished Jul 16 05:40:51 PM PDT 24
Peak memory 255788 kb
Host smart-ec4a3739-57f0-450f-9da0-dfd32cd74cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71367
8112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.713678112
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1315746663
Short name T704
Test name
Test status
Simulation time 785640486 ps
CPU time 49.75 seconds
Started Jul 16 05:40:35 PM PDT 24
Finished Jul 16 05:41:26 PM PDT 24
Peak memory 249232 kb
Host smart-9f6b92f1-78a7-47aa-8960-42050a6ae57b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13157
46663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1315746663
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1595005790
Short name T618
Test name
Test status
Simulation time 56663601 ps
CPU time 3.07 seconds
Started Jul 16 05:40:37 PM PDT 24
Finished Jul 16 05:40:40 PM PDT 24
Peak memory 251540 kb
Host smart-ccad4d80-1e6b-4d24-8801-d2bd6717c4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15950
05790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1595005790
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4226606202
Short name T245
Test name
Test status
Simulation time 41938446735 ps
CPU time 2803.46 seconds
Started Jul 16 05:40:33 PM PDT 24
Finished Jul 16 06:27:17 PM PDT 24
Peak memory 290336 kb
Host smart-db68f5aa-722e-4df7-ad29-0db5b21f3aef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226606202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4226606202
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.4050874171
Short name T31
Test name
Test status
Simulation time 87284325853 ps
CPU time 2769.13 seconds
Started Jul 16 05:40:36 PM PDT 24
Finished Jul 16 06:26:47 PM PDT 24
Peak memory 316632 kb
Host smart-ea9d1e34-7e60-4cd3-808a-e42704e6c98d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050874171 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.4050874171
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3566520639
Short name T568
Test name
Test status
Simulation time 24813042948 ps
CPU time 1531.61 seconds
Started Jul 16 05:40:39 PM PDT 24
Finished Jul 16 06:06:11 PM PDT 24
Peak memory 273940 kb
Host smart-b2c4f392-394c-467d-b9b1-0cba2afdcf7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566520639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3566520639
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3995626473
Short name T446
Test name
Test status
Simulation time 887721421 ps
CPU time 63.38 seconds
Started Jul 16 05:40:34 PM PDT 24
Finished Jul 16 05:41:39 PM PDT 24
Peak memory 257476 kb
Host smart-3f4c6e99-d957-4f75-8168-64160a09e205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39956
26473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3995626473
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.819407027
Short name T358
Test name
Test status
Simulation time 352955081 ps
CPU time 23.39 seconds
Started Jul 16 05:40:34 PM PDT 24
Finished Jul 16 05:40:58 PM PDT 24
Peak memory 257424 kb
Host smart-525cde73-bd7c-422c-9c75-0b02b09cb5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81940
7027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.819407027
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2789736630
Short name T589
Test name
Test status
Simulation time 13098782262 ps
CPU time 1185.52 seconds
Started Jul 16 05:40:45 PM PDT 24
Finished Jul 16 06:00:32 PM PDT 24
Peak memory 283748 kb
Host smart-68abe1b3-65ea-46ee-a352-a7ed5fb3c45b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789736630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2789736630
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.183583318
Short name T378
Test name
Test status
Simulation time 368038194071 ps
CPU time 2599.5 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 06:24:12 PM PDT 24
Peak memory 290124 kb
Host smart-9359c7c9-cbfc-4a84-959d-5e36c92526d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183583318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.183583318
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2996804944
Short name T490
Test name
Test status
Simulation time 6943577061 ps
CPU time 142.73 seconds
Started Jul 16 05:40:44 PM PDT 24
Finished Jul 16 05:43:07 PM PDT 24
Peak memory 256684 kb
Host smart-67b2bd60-f415-45ce-af6e-50e9abc54baf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996804944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2996804944
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1165276622
Short name T30
Test name
Test status
Simulation time 75005596 ps
CPU time 6.09 seconds
Started Jul 16 05:40:33 PM PDT 24
Finished Jul 16 05:40:40 PM PDT 24
Peak memory 249164 kb
Host smart-75436406-e339-478e-aeaa-148c8a799395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11652
76622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1165276622
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.13137789
Short name T48
Test name
Test status
Simulation time 502851029 ps
CPU time 15.01 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 05:41:08 PM PDT 24
Peak memory 248656 kb
Host smart-f7569998-8ab9-457f-8b02-fde3f13deacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13137
789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.13137789
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3264013232
Short name T516
Test name
Test status
Simulation time 155428599 ps
CPU time 7.61 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 05:40:59 PM PDT 24
Peak memory 248736 kb
Host smart-f7e61bab-9a6e-4dcd-b3c3-131457883463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32640
13232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3264013232
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3156359285
Short name T363
Test name
Test status
Simulation time 5349669739 ps
CPU time 66.06 seconds
Started Jul 16 05:40:33 PM PDT 24
Finished Jul 16 05:41:40 PM PDT 24
Peak memory 256476 kb
Host smart-be1c069e-3393-4982-a975-26fcb9ed3132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31563
59285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3156359285
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1026806978
Short name T259
Test name
Test status
Simulation time 58563374541 ps
CPU time 1919.36 seconds
Started Jul 16 05:40:45 PM PDT 24
Finished Jul 16 06:12:47 PM PDT 24
Peak memory 289272 kb
Host smart-7f324cd5-85d6-4027-a703-bba2cc85262e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026806978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1026806978
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3243047985
Short name T203
Test name
Test status
Simulation time 129211493 ps
CPU time 3.34 seconds
Started Jul 16 05:39:16 PM PDT 24
Finished Jul 16 05:39:19 PM PDT 24
Peak memory 249532 kb
Host smart-790f4a9d-df99-4392-a271-bc0163c74c94
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3243047985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3243047985
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2555768313
Short name T403
Test name
Test status
Simulation time 31401041645 ps
CPU time 721.84 seconds
Started Jul 16 05:39:16 PM PDT 24
Finished Jul 16 05:51:18 PM PDT 24
Peak memory 267048 kb
Host smart-fa0d6563-6cfe-4445-861e-2d53a4e5630f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555768313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2555768313
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2438186248
Short name T664
Test name
Test status
Simulation time 1137056705 ps
CPU time 15.29 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:39:28 PM PDT 24
Peak memory 249172 kb
Host smart-703ea3ee-5993-4ba2-a505-2c1f7cec36ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2438186248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2438186248
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1562614220
Short name T405
Test name
Test status
Simulation time 1716758474 ps
CPU time 85.82 seconds
Started Jul 16 05:39:10 PM PDT 24
Finished Jul 16 05:40:37 PM PDT 24
Peak memory 256772 kb
Host smart-96b8f2fe-d273-4636-8dea-d8ac4ba8d4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15626
14220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1562614220
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.427628832
Short name T442
Test name
Test status
Simulation time 107718220 ps
CPU time 10.29 seconds
Started Jul 16 05:39:07 PM PDT 24
Finished Jul 16 05:39:18 PM PDT 24
Peak memory 249180 kb
Host smart-8010a618-6061-4f8c-966c-70e171d11205
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42762
8832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.427628832
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.4066076609
Short name T16
Test name
Test status
Simulation time 10851770813 ps
CPU time 976.64 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 05:55:31 PM PDT 24
Peak memory 273296 kb
Host smart-14e24aa1-9348-4631-b0b1-639aa28e60f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066076609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.4066076609
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1087234882
Short name T567
Test name
Test status
Simulation time 28968681610 ps
CPU time 1598.43 seconds
Started Jul 16 05:39:14 PM PDT 24
Finished Jul 16 06:05:54 PM PDT 24
Peak memory 273936 kb
Host smart-6c78d133-9fe1-4b03-84e9-94d9d02858dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087234882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1087234882
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2762969710
Short name T341
Test name
Test status
Simulation time 295198573 ps
CPU time 25.15 seconds
Started Jul 16 05:39:12 PM PDT 24
Finished Jul 16 05:39:39 PM PDT 24
Peak memory 249288 kb
Host smart-9e30431c-9d39-47a8-bd00-e6c0bf034ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27629
69710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2762969710
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2140547941
Short name T687
Test name
Test status
Simulation time 339191135 ps
CPU time 22.65 seconds
Started Jul 16 05:39:12 PM PDT 24
Finished Jul 16 05:39:36 PM PDT 24
Peak memory 256868 kb
Host smart-da569f55-fac0-430d-b7bc-ed82e2b38588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21405
47941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2140547941
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.135433555
Short name T13
Test name
Test status
Simulation time 1250677620 ps
CPU time 48.99 seconds
Started Jul 16 05:39:15 PM PDT 24
Finished Jul 16 05:40:05 PM PDT 24
Peak memory 270848 kb
Host smart-62b79ce3-0726-4cc2-b114-843bfe345cb5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=135433555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.135433555
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.427658952
Short name T113
Test name
Test status
Simulation time 1177150091 ps
CPU time 29.54 seconds
Started Jul 16 05:39:08 PM PDT 24
Finished Jul 16 05:39:38 PM PDT 24
Peak memory 249244 kb
Host smart-8d00c05b-8539-4786-b51b-1efd6fc2d73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42765
8952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.427658952
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2236595186
Short name T457
Test name
Test status
Simulation time 1410755158 ps
CPU time 15.11 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 05:39:25 PM PDT 24
Peak memory 255992 kb
Host smart-c2ad82ed-8c50-4a27-9a84-272ee6c2f020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22365
95186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2236595186
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2763945506
Short name T91
Test name
Test status
Simulation time 1059091429 ps
CPU time 76.46 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:40:29 PM PDT 24
Peak memory 256508 kb
Host smart-a0f955b0-0058-47a5-b6f8-2e8e3678c051
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763945506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2763945506
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2100821263
Short name T631
Test name
Test status
Simulation time 28054901530 ps
CPU time 1962.83 seconds
Started Jul 16 05:40:45 PM PDT 24
Finished Jul 16 06:13:30 PM PDT 24
Peak memory 290060 kb
Host smart-a4f52462-ab4b-4c4f-9038-d40de550d14a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100821263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2100821263
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.752709605
Short name T356
Test name
Test status
Simulation time 17065100389 ps
CPU time 277.02 seconds
Started Jul 16 05:40:46 PM PDT 24
Finished Jul 16 05:45:25 PM PDT 24
Peak memory 256936 kb
Host smart-b5798d8a-db71-41f3-a243-d6391bb9c3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75270
9605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.752709605
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.358600560
Short name T603
Test name
Test status
Simulation time 540154291 ps
CPU time 38.08 seconds
Started Jul 16 05:40:49 PM PDT 24
Finished Jul 16 05:41:29 PM PDT 24
Peak memory 256928 kb
Host smart-18b0a3de-22cd-4c78-af5c-f7060c57aa1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35860
0560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.358600560
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.727320455
Short name T469
Test name
Test status
Simulation time 10171344376 ps
CPU time 839.84 seconds
Started Jul 16 05:40:45 PM PDT 24
Finished Jul 16 05:54:47 PM PDT 24
Peak memory 273372 kb
Host smart-395660fe-209b-4903-b076-7aaad99e084c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727320455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.727320455
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2412567416
Short name T596
Test name
Test status
Simulation time 121048100577 ps
CPU time 1945.71 seconds
Started Jul 16 05:40:45 PM PDT 24
Finished Jul 16 06:13:12 PM PDT 24
Peak memory 283004 kb
Host smart-674f0075-b38a-4b63-a782-99f9ed060424
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412567416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2412567416
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1274813980
Short name T305
Test name
Test status
Simulation time 13777767537 ps
CPU time 546.01 seconds
Started Jul 16 05:40:43 PM PDT 24
Finished Jul 16 05:49:50 PM PDT 24
Peak memory 249296 kb
Host smart-e5e92ff8-1fae-476a-9b91-247743e426ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274813980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1274813980
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2028061629
Short name T51
Test name
Test status
Simulation time 465300172 ps
CPU time 9.03 seconds
Started Jul 16 05:40:44 PM PDT 24
Finished Jul 16 05:40:55 PM PDT 24
Peak memory 249260 kb
Host smart-1fee9185-df2b-4e89-9b8d-05cccd587d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20280
61629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2028061629
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.318311532
Short name T592
Test name
Test status
Simulation time 3399621813 ps
CPU time 59.17 seconds
Started Jul 16 05:40:44 PM PDT 24
Finished Jul 16 05:41:44 PM PDT 24
Peak memory 257584 kb
Host smart-e3498fb0-0e8a-4d32-81c6-3a2e820bfca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31831
1532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.318311532
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.81942433
Short name T73
Test name
Test status
Simulation time 119507353 ps
CPU time 12.47 seconds
Started Jul 16 05:40:45 PM PDT 24
Finished Jul 16 05:41:00 PM PDT 24
Peak memory 248516 kb
Host smart-bc60500f-5555-459a-92f9-c63f4aebb035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81942
433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.81942433
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3424219571
Short name T662
Test name
Test status
Simulation time 828465652 ps
CPU time 30.35 seconds
Started Jul 16 05:40:44 PM PDT 24
Finished Jul 16 05:41:16 PM PDT 24
Peak memory 257292 kb
Host smart-930c46bc-9207-4ed8-af81-bc8e0803f7b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34242
19571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3424219571
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1787830618
Short name T529
Test name
Test status
Simulation time 74681488696 ps
CPU time 984.48 seconds
Started Jul 16 05:40:47 PM PDT 24
Finished Jul 16 05:57:13 PM PDT 24
Peak memory 283468 kb
Host smart-31065d3d-23be-4b48-bfbc-b5f5bebc8854
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787830618 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1787830618
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2682022335
Short name T495
Test name
Test status
Simulation time 24233896590 ps
CPU time 678.84 seconds
Started Jul 16 05:40:46 PM PDT 24
Finished Jul 16 05:52:07 PM PDT 24
Peak memory 273480 kb
Host smart-8b29ef34-8f4b-407a-82b9-000b8f348898
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682022335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2682022335
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1354111305
Short name T389
Test name
Test status
Simulation time 1554944317 ps
CPU time 104.38 seconds
Started Jul 16 05:40:43 PM PDT 24
Finished Jul 16 05:42:29 PM PDT 24
Peak memory 256788 kb
Host smart-62b1d33b-a27b-4929-8269-8391e884085d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13541
11305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1354111305
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1431961583
Short name T630
Test name
Test status
Simulation time 611934012 ps
CPU time 17.21 seconds
Started Jul 16 05:40:44 PM PDT 24
Finished Jul 16 05:41:02 PM PDT 24
Peak memory 249100 kb
Host smart-5a58cec2-9cca-4814-b94d-1dea57e7483a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14319
61583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1431961583
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1441414608
Short name T317
Test name
Test status
Simulation time 192998279060 ps
CPU time 2693.08 seconds
Started Jul 16 05:40:46 PM PDT 24
Finished Jul 16 06:25:42 PM PDT 24
Peak memory 290140 kb
Host smart-16aaea58-837a-4bbc-bda9-2f755d632e82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441414608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1441414608
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2816657643
Short name T610
Test name
Test status
Simulation time 42082706718 ps
CPU time 2428.6 seconds
Started Jul 16 05:40:49 PM PDT 24
Finished Jul 16 06:21:19 PM PDT 24
Peak memory 290152 kb
Host smart-cd9ec9fa-3fa0-4f67-8cad-307911a50b24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816657643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2816657643
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3025906659
Short name T310
Test name
Test status
Simulation time 48104272533 ps
CPU time 441.98 seconds
Started Jul 16 05:40:44 PM PDT 24
Finished Jul 16 05:48:08 PM PDT 24
Peak memory 257444 kb
Host smart-9ed996e2-e6e2-4cbe-924d-536e1668ebdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025906659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3025906659
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2336085072
Short name T617
Test name
Test status
Simulation time 993533771 ps
CPU time 28.17 seconds
Started Jul 16 05:40:46 PM PDT 24
Finished Jul 16 05:41:17 PM PDT 24
Peak memory 256888 kb
Host smart-dbd1e434-34ad-40da-95a0-3720a9f382b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23360
85072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2336085072
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1373610381
Short name T625
Test name
Test status
Simulation time 2246431659 ps
CPU time 37.7 seconds
Started Jul 16 05:40:44 PM PDT 24
Finished Jul 16 05:41:23 PM PDT 24
Peak memory 249388 kb
Host smart-02dbc19c-eeaf-41ad-91b1-018a61972252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13736
10381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1373610381
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3377407139
Short name T43
Test name
Test status
Simulation time 566579468 ps
CPU time 33.85 seconds
Started Jul 16 05:40:43 PM PDT 24
Finished Jul 16 05:41:17 PM PDT 24
Peak memory 249288 kb
Host smart-bd550f14-c3c8-4e9e-8c7a-abaa29e4f35a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33774
07139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3377407139
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2160335137
Short name T638
Test name
Test status
Simulation time 5077567142 ps
CPU time 75.83 seconds
Started Jul 16 05:40:47 PM PDT 24
Finished Jul 16 05:42:05 PM PDT 24
Peak memory 249756 kb
Host smart-da435407-a0f4-4bc7-a07a-e38fdd9c9eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21603
35137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2160335137
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1735934735
Short name T489
Test name
Test status
Simulation time 8548768906 ps
CPU time 972.01 seconds
Started Jul 16 05:40:49 PM PDT 24
Finished Jul 16 05:57:02 PM PDT 24
Peak memory 272920 kb
Host smart-8901b8aa-5bbf-47d6-9efb-0b6bf6e73137
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735934735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1735934735
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1008350278
Short name T297
Test name
Test status
Simulation time 23878195987 ps
CPU time 1673.91 seconds
Started Jul 16 05:40:47 PM PDT 24
Finished Jul 16 06:08:43 PM PDT 24
Peak memory 273556 kb
Host smart-f9cd11a7-a63b-40ce-82b1-3d2bf01c6cae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008350278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1008350278
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2053173170
Short name T682
Test name
Test status
Simulation time 16975455014 ps
CPU time 241.65 seconds
Started Jul 16 05:40:49 PM PDT 24
Finished Jul 16 05:44:52 PM PDT 24
Peak memory 257588 kb
Host smart-687961f1-a856-44d1-97ec-ba7cf4141081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20531
73170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2053173170
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.197081906
Short name T410
Test name
Test status
Simulation time 4039525617 ps
CPU time 58.76 seconds
Started Jul 16 05:40:45 PM PDT 24
Finished Jul 16 05:41:46 PM PDT 24
Peak memory 249316 kb
Host smart-8d9d3f73-bea4-496a-a9b8-f83c7a0d07a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19708
1906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.197081906
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2645717777
Short name T319
Test name
Test status
Simulation time 55434750848 ps
CPU time 1913.77 seconds
Started Jul 16 05:40:55 PM PDT 24
Finished Jul 16 06:12:50 PM PDT 24
Peak memory 289304 kb
Host smart-fdce3057-6171-4cac-b591-6447dfb6e8a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645717777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2645717777
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.4082441503
Short name T241
Test name
Test status
Simulation time 16716105697 ps
CPU time 1274.91 seconds
Started Jul 16 05:40:57 PM PDT 24
Finished Jul 16 06:02:13 PM PDT 24
Peak memory 273936 kb
Host smart-803d37b8-2f2e-42a5-9c03-86c27b0e8d6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082441503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.4082441503
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1250327253
Short name T496
Test name
Test status
Simulation time 108161596654 ps
CPU time 515.68 seconds
Started Jul 16 05:40:48 PM PDT 24
Finished Jul 16 05:49:25 PM PDT 24
Peak memory 255100 kb
Host smart-9ce6b84e-8bf3-4b7c-b666-a044fcb102c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250327253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1250327253
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3798558308
Short name T506
Test name
Test status
Simulation time 6050865820 ps
CPU time 52.11 seconds
Started Jul 16 05:40:50 PM PDT 24
Finished Jul 16 05:41:44 PM PDT 24
Peak memory 257556 kb
Host smart-6d8cfe6d-b695-4e5a-85fa-460d4712fae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37985
58308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3798558308
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1560612778
Short name T550
Test name
Test status
Simulation time 656142508 ps
CPU time 16.23 seconds
Started Jul 16 05:40:45 PM PDT 24
Finished Jul 16 05:41:04 PM PDT 24
Peak memory 248704 kb
Host smart-1f3971f0-45c6-4961-8e8d-9416fd682ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15606
12778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1560612778
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2173735130
Short name T36
Test name
Test status
Simulation time 284698393 ps
CPU time 8.15 seconds
Started Jul 16 05:40:46 PM PDT 24
Finished Jul 16 05:40:57 PM PDT 24
Peak memory 249192 kb
Host smart-2c22226a-ccb0-421c-a189-849b48c16b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21737
35130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2173735130
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.4083882187
Short name T281
Test name
Test status
Simulation time 742406471 ps
CPU time 19.23 seconds
Started Jul 16 05:40:45 PM PDT 24
Finished Jul 16 05:41:07 PM PDT 24
Peak memory 257328 kb
Host smart-3e2651cb-dd61-4d9a-a51a-49efa6104713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40838
82187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.4083882187
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1237892827
Short name T472
Test name
Test status
Simulation time 211687139338 ps
CPU time 1851.15 seconds
Started Jul 16 05:40:55 PM PDT 24
Finished Jul 16 06:11:48 PM PDT 24
Peak memory 289768 kb
Host smart-3887eb97-71e7-4643-bd96-49785e9b510b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237892827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1237892827
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2707356109
Short name T710
Test name
Test status
Simulation time 67480650539 ps
CPU time 2326.51 seconds
Started Jul 16 05:41:01 PM PDT 24
Finished Jul 16 06:19:48 PM PDT 24
Peak memory 282008 kb
Host smart-ccb822aa-d0c2-40d7-8847-df31b694ef45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707356109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2707356109
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1979160520
Short name T451
Test name
Test status
Simulation time 2090224651 ps
CPU time 109.58 seconds
Started Jul 16 05:40:55 PM PDT 24
Finished Jul 16 05:42:46 PM PDT 24
Peak memory 250284 kb
Host smart-44a9a70a-33c6-48c5-8fd1-741679270e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19791
60520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1979160520
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3405461185
Short name T640
Test name
Test status
Simulation time 2388408419 ps
CPU time 77.76 seconds
Started Jul 16 05:40:55 PM PDT 24
Finished Jul 16 05:42:14 PM PDT 24
Peak memory 249324 kb
Host smart-e9262a08-72c2-4b8e-b019-1c32de346adc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34054
61185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3405461185
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3778545581
Short name T306
Test name
Test status
Simulation time 113934087070 ps
CPU time 1692.24 seconds
Started Jul 16 05:40:57 PM PDT 24
Finished Jul 16 06:09:11 PM PDT 24
Peak memory 273252 kb
Host smart-0b9b524c-76c0-449c-aa60-eca6970bfa33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778545581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3778545581
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.405917829
Short name T660
Test name
Test status
Simulation time 115968416113 ps
CPU time 3162.8 seconds
Started Jul 16 05:40:58 PM PDT 24
Finished Jul 16 06:33:42 PM PDT 24
Peak memory 290040 kb
Host smart-9dfd1d05-cd90-40d4-8030-a1c03e452ab5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405917829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.405917829
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.770835198
Short name T11
Test name
Test status
Simulation time 7514620245 ps
CPU time 296.51 seconds
Started Jul 16 05:40:57 PM PDT 24
Finished Jul 16 05:45:55 PM PDT 24
Peak memory 249328 kb
Host smart-506ad030-0065-4c04-81fb-0dee00b4f744
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770835198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.770835198
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2944403902
Short name T692
Test name
Test status
Simulation time 132665047 ps
CPU time 8.01 seconds
Started Jul 16 05:40:57 PM PDT 24
Finished Jul 16 05:41:06 PM PDT 24
Peak memory 253180 kb
Host smart-ed471b12-a8c0-405d-b4a2-07a89d93722b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29444
03902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2944403902
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1934621000
Short name T239
Test name
Test status
Simulation time 1359628450 ps
CPU time 29.07 seconds
Started Jul 16 05:40:55 PM PDT 24
Finished Jul 16 05:41:26 PM PDT 24
Peak memory 248628 kb
Host smart-79097b96-ed0c-488b-a94f-e43e9869f238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19346
21000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1934621000
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.206386688
Short name T672
Test name
Test status
Simulation time 1956255360 ps
CPU time 27.58 seconds
Started Jul 16 05:40:57 PM PDT 24
Finished Jul 16 05:41:25 PM PDT 24
Peak memory 249648 kb
Host smart-ee364bbb-37a1-4fe7-ac25-22db18ab7cfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20638
6688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.206386688
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.588882072
Short name T450
Test name
Test status
Simulation time 271677055 ps
CPU time 25.08 seconds
Started Jul 16 05:40:56 PM PDT 24
Finished Jul 16 05:41:22 PM PDT 24
Peak memory 249264 kb
Host smart-6e3dad45-95e9-492f-8c05-89ee2dc55ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58888
2072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.588882072
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.38022157
Short name T101
Test name
Test status
Simulation time 61874491638 ps
CPU time 1972.93 seconds
Started Jul 16 05:40:56 PM PDT 24
Finished Jul 16 06:13:50 PM PDT 24
Peak memory 272476 kb
Host smart-5c489544-1230-497f-a7bb-8daf145bc083
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38022157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_hand
ler_stress_all.38022157
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1001765910
Short name T623
Test name
Test status
Simulation time 32346070597 ps
CPU time 2163.15 seconds
Started Jul 16 05:42:10 PM PDT 24
Finished Jul 16 06:18:17 PM PDT 24
Peak memory 273920 kb
Host smart-72b22d79-c786-4e3d-a543-df82c4550e93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001765910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1001765910
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.236434758
Short name T400
Test name
Test status
Simulation time 4451825068 ps
CPU time 104.33 seconds
Started Jul 16 05:40:54 PM PDT 24
Finished Jul 16 05:42:40 PM PDT 24
Peak memory 257500 kb
Host smart-badaba20-4519-4bb2-b9f3-407454aa03b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23643
4758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.236434758
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1113085626
Short name T690
Test name
Test status
Simulation time 8211061091 ps
CPU time 40.23 seconds
Started Jul 16 05:41:03 PM PDT 24
Finished Jul 16 05:41:43 PM PDT 24
Peak memory 248676 kb
Host smart-769130cd-44ca-424f-8588-e3753cbe3507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11130
85626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1113085626
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.938287773
Short name T708
Test name
Test status
Simulation time 134598884712 ps
CPU time 2270.47 seconds
Started Jul 16 05:40:55 PM PDT 24
Finished Jul 16 06:18:47 PM PDT 24
Peak memory 290288 kb
Host smart-594e0451-a012-450a-98af-de18b0b7e62b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938287773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.938287773
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2208589194
Short name T494
Test name
Test status
Simulation time 7712325120 ps
CPU time 152.93 seconds
Started Jul 16 05:40:56 PM PDT 24
Finished Jul 16 05:43:30 PM PDT 24
Peak memory 248140 kb
Host smart-4190bc19-a42a-4ccd-a880-1930502088d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208589194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2208589194
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2318514757
Short name T396
Test name
Test status
Simulation time 1525714244 ps
CPU time 28.55 seconds
Started Jul 16 05:40:56 PM PDT 24
Finished Jul 16 05:41:25 PM PDT 24
Peak memory 256680 kb
Host smart-4c6a4623-efe6-47bb-a9e3-17012c918e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23185
14757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2318514757
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.178048768
Short name T277
Test name
Test status
Simulation time 691600796 ps
CPU time 28.76 seconds
Started Jul 16 05:40:54 PM PDT 24
Finished Jul 16 05:41:23 PM PDT 24
Peak memory 248732 kb
Host smart-2c9054b6-edf0-4df4-ad0a-56dab5dcc720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17804
8768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.178048768
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3623939027
Short name T67
Test name
Test status
Simulation time 247421575 ps
CPU time 31.34 seconds
Started Jul 16 05:40:56 PM PDT 24
Finished Jul 16 05:41:28 PM PDT 24
Peak memory 249156 kb
Host smart-8e2cdf63-7a93-4830-b3fc-164eff0a33b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36239
39027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3623939027
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3708951502
Short name T598
Test name
Test status
Simulation time 5626784496 ps
CPU time 59.4 seconds
Started Jul 16 05:40:55 PM PDT 24
Finished Jul 16 05:41:55 PM PDT 24
Peak memory 257532 kb
Host smart-ac8033ff-8dd1-4acb-a147-7e5bab18e45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37089
51502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3708951502
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2847200195
Short name T255
Test name
Test status
Simulation time 10224849040 ps
CPU time 547.54 seconds
Started Jul 16 05:40:59 PM PDT 24
Finished Jul 16 05:50:07 PM PDT 24
Peak memory 257584 kb
Host smart-352e40db-f448-4db9-87ce-72a4760eef85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847200195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2847200195
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3702764977
Short name T81
Test name
Test status
Simulation time 258916147556 ps
CPU time 3299.62 seconds
Started Jul 16 05:40:52 PM PDT 24
Finished Jul 16 06:35:54 PM PDT 24
Peak memory 339544 kb
Host smart-ae212536-9885-4ae6-9d70-aa53d849ee5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702764977 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3702764977
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2270998431
Short name T421
Test name
Test status
Simulation time 104275965900 ps
CPU time 1697.66 seconds
Started Jul 16 05:40:58 PM PDT 24
Finished Jul 16 06:09:16 PM PDT 24
Peak memory 273752 kb
Host smart-16e4e43f-abe7-477f-826d-51cb9d0d0efb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270998431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2270998431
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.401861192
Short name T632
Test name
Test status
Simulation time 5552206628 ps
CPU time 251.23 seconds
Started Jul 16 05:40:57 PM PDT 24
Finished Jul 16 05:45:09 PM PDT 24
Peak memory 252504 kb
Host smart-3c3d2d90-1639-43df-9a3e-84538a3a066f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40186
1192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.401861192
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.170694713
Short name T76
Test name
Test status
Simulation time 1046998589 ps
CPU time 35.27 seconds
Started Jul 16 05:40:59 PM PDT 24
Finished Jul 16 05:41:35 PM PDT 24
Peak memory 249172 kb
Host smart-a6e84844-5807-4378-a80c-965ad2b4a04c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17069
4713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.170694713
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2252577368
Short name T488
Test name
Test status
Simulation time 44490785458 ps
CPU time 1805.39 seconds
Started Jul 16 05:41:07 PM PDT 24
Finished Jul 16 06:11:14 PM PDT 24
Peak memory 273680 kb
Host smart-a1bd4cd0-9b5b-43de-8dc2-661a90401d46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252577368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2252577368
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.281059191
Short name T313
Test name
Test status
Simulation time 3472316284 ps
CPU time 135.29 seconds
Started Jul 16 05:40:57 PM PDT 24
Finished Jul 16 05:43:13 PM PDT 24
Peak memory 249332 kb
Host smart-85289274-2891-4506-a1b5-1d4b1e0227ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281059191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.281059191
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1845956787
Short name T705
Test name
Test status
Simulation time 277207204 ps
CPU time 8.3 seconds
Started Jul 16 05:40:55 PM PDT 24
Finished Jul 16 05:41:05 PM PDT 24
Peak memory 249288 kb
Host smart-a36ff9a3-c7f4-4689-933d-562171f15f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18459
56787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1845956787
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1509341201
Short name T346
Test name
Test status
Simulation time 420060423 ps
CPU time 4.91 seconds
Started Jul 16 05:40:56 PM PDT 24
Finished Jul 16 05:41:02 PM PDT 24
Peak memory 241084 kb
Host smart-8da17a11-c61b-497f-adb2-f9c5b501aa29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15093
41201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1509341201
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1238611466
Short name T284
Test name
Test status
Simulation time 588906563 ps
CPU time 18.57 seconds
Started Jul 16 05:40:56 PM PDT 24
Finished Jul 16 05:41:16 PM PDT 24
Peak memory 256420 kb
Host smart-5bac3446-a9ac-4a02-b9ac-639b5fef52f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12386
11466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1238611466
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3509156129
Short name T337
Test name
Test status
Simulation time 267149551 ps
CPU time 29.13 seconds
Started Jul 16 05:40:58 PM PDT 24
Finished Jul 16 05:41:28 PM PDT 24
Peak memory 257320 kb
Host smart-bc03d833-42db-43a7-b621-97e6a79f7a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35091
56129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3509156129
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1837348563
Short name T236
Test name
Test status
Simulation time 28884280252 ps
CPU time 511.16 seconds
Started Jul 16 05:41:08 PM PDT 24
Finished Jul 16 05:49:40 PM PDT 24
Peak memory 274004 kb
Host smart-54a89632-3181-4fa1-91bb-d5edd392cb72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837348563 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1837348563
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2299538063
Short name T505
Test name
Test status
Simulation time 232313147004 ps
CPU time 2140.92 seconds
Started Jul 16 05:41:05 PM PDT 24
Finished Jul 16 06:16:47 PM PDT 24
Peak memory 273904 kb
Host smart-3d730534-b2ba-441e-af16-e03c397838c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299538063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2299538063
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2160974161
Short name T342
Test name
Test status
Simulation time 3596903700 ps
CPU time 209.56 seconds
Started Jul 16 05:41:12 PM PDT 24
Finished Jul 16 05:44:42 PM PDT 24
Peak memory 257072 kb
Host smart-75661c0c-79fa-4725-8fae-079f76370dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21609
74161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2160974161
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.4208449981
Short name T452
Test name
Test status
Simulation time 361276998 ps
CPU time 24.8 seconds
Started Jul 16 05:41:06 PM PDT 24
Finished Jul 16 05:41:32 PM PDT 24
Peak memory 249248 kb
Host smart-57176460-0075-4c67-86a4-65341d39c230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42084
49981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4208449981
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.648358678
Short name T32
Test name
Test status
Simulation time 60656808712 ps
CPU time 1267.43 seconds
Started Jul 16 05:41:07 PM PDT 24
Finished Jul 16 06:02:16 PM PDT 24
Peak memory 289600 kb
Host smart-da41424f-0b92-4f05-b498-b88058039d49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648358678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.648358678
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1604749929
Short name T535
Test name
Test status
Simulation time 11166077800 ps
CPU time 1364.12 seconds
Started Jul 16 05:41:22 PM PDT 24
Finished Jul 16 06:04:07 PM PDT 24
Peak memory 290152 kb
Host smart-dfb73082-a4ab-4ed3-b038-a445c9bba045
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604749929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1604749929
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1946454899
Short name T637
Test name
Test status
Simulation time 9858204146 ps
CPU time 385.37 seconds
Started Jul 16 05:41:10 PM PDT 24
Finished Jul 16 05:47:36 PM PDT 24
Peak memory 249356 kb
Host smart-a79aebd2-3eb0-4384-9511-bba7045b6217
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946454899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1946454899
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2882074447
Short name T17
Test name
Test status
Simulation time 2254299196 ps
CPU time 67.4 seconds
Started Jul 16 05:41:07 PM PDT 24
Finished Jul 16 05:42:16 PM PDT 24
Peak memory 256760 kb
Host smart-868abb52-31d5-4595-ab74-91a5fb37b658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28820
74447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2882074447
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3687690282
Short name T475
Test name
Test status
Simulation time 334813679 ps
CPU time 29.89 seconds
Started Jul 16 05:41:06 PM PDT 24
Finished Jul 16 05:41:36 PM PDT 24
Peak memory 257016 kb
Host smart-92cf1466-e6ae-4edf-80a3-fc26206092c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36876
90282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3687690282
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2326927460
Short name T104
Test name
Test status
Simulation time 1255791370 ps
CPU time 25.34 seconds
Started Jul 16 05:41:04 PM PDT 24
Finished Jul 16 05:41:30 PM PDT 24
Peak memory 249368 kb
Host smart-317ecca3-3963-4374-862e-fa288e127ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23269
27460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2326927460
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.274079018
Short name T371
Test name
Test status
Simulation time 753330377 ps
CPU time 40.75 seconds
Started Jul 16 05:41:07 PM PDT 24
Finished Jul 16 05:41:49 PM PDT 24
Peak memory 256968 kb
Host smart-354e4ad9-892e-45e0-8b25-48d9cabca4e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27407
9018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.274079018
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.4097016051
Short name T93
Test name
Test status
Simulation time 60814789209 ps
CPU time 1087.17 seconds
Started Jul 16 05:41:07 PM PDT 24
Finished Jul 16 05:59:15 PM PDT 24
Peak memory 272936 kb
Host smart-118abf01-e0b7-45ad-a5ad-6dc2d4eb0d13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097016051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.4097016051
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3850036087
Short name T415
Test name
Test status
Simulation time 4915211847 ps
CPU time 143.3 seconds
Started Jul 16 05:41:06 PM PDT 24
Finished Jul 16 05:43:30 PM PDT 24
Peak memory 257068 kb
Host smart-f05b74b9-5ef8-468c-84d8-4a246c4ff462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38500
36087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3850036087
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.743544055
Short name T260
Test name
Test status
Simulation time 1793488054 ps
CPU time 30.74 seconds
Started Jul 16 05:41:11 PM PDT 24
Finished Jul 16 05:41:43 PM PDT 24
Peak memory 249256 kb
Host smart-4c885c1d-e2fd-4a86-86c8-3ccf7f614da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74354
4055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.743544055
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3602673239
Short name T486
Test name
Test status
Simulation time 43982214696 ps
CPU time 1496.64 seconds
Started Jul 16 05:41:06 PM PDT 24
Finished Jul 16 06:06:04 PM PDT 24
Peak memory 274108 kb
Host smart-4fe74377-64b3-4d25-8e38-56b7a086d760
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602673239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3602673239
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.4224199911
Short name T458
Test name
Test status
Simulation time 7636979743 ps
CPU time 973.22 seconds
Started Jul 16 05:41:16 PM PDT 24
Finished Jul 16 05:57:33 PM PDT 24
Peak memory 273588 kb
Host smart-ea351754-6636-4346-9285-5d90e94fc349
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224199911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.4224199911
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3797187045
Short name T459
Test name
Test status
Simulation time 45590493909 ps
CPU time 392.96 seconds
Started Jul 16 05:41:12 PM PDT 24
Finished Jul 16 05:47:46 PM PDT 24
Peak memory 256116 kb
Host smart-bdc71959-9dcd-4e02-994a-162c6fe03796
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797187045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3797187045
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3624556457
Short name T417
Test name
Test status
Simulation time 290096223 ps
CPU time 33.65 seconds
Started Jul 16 05:41:13 PM PDT 24
Finished Jul 16 05:41:48 PM PDT 24
Peak memory 257300 kb
Host smart-54c948dd-2c8a-4f4c-b7cb-bab84dcbd19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36245
56457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3624556457
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.4279089345
Short name T557
Test name
Test status
Simulation time 223790713 ps
CPU time 21.8 seconds
Started Jul 16 05:41:07 PM PDT 24
Finished Jul 16 05:41:30 PM PDT 24
Peak memory 249252 kb
Host smart-5e6d9754-21e7-40e5-a77a-b3542f182f7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42790
89345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.4279089345
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3429212013
Short name T265
Test name
Test status
Simulation time 210810291 ps
CPU time 24.04 seconds
Started Jul 16 05:41:13 PM PDT 24
Finished Jul 16 05:41:38 PM PDT 24
Peak memory 257308 kb
Host smart-d998a8fb-11f1-42b7-899e-c48ef174a5ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34292
12013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3429212013
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3953318319
Short name T375
Test name
Test status
Simulation time 4839841765 ps
CPU time 29.07 seconds
Started Jul 16 05:41:10 PM PDT 24
Finished Jul 16 05:41:39 PM PDT 24
Peak memory 256700 kb
Host smart-d8a16889-8bdf-41fc-ac3f-f648c3757e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39533
18319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3953318319
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.859482164
Short name T272
Test name
Test status
Simulation time 86524482571 ps
CPU time 2598.98 seconds
Started Jul 16 05:41:17 PM PDT 24
Finished Jul 16 06:24:39 PM PDT 24
Peak memory 287120 kb
Host smart-1f060426-8358-4305-a1bf-c7ff09b069b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859482164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.859482164
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2630899160
Short name T54
Test name
Test status
Simulation time 79038305193 ps
CPU time 1485.27 seconds
Started Jul 16 05:41:16 PM PDT 24
Finished Jul 16 06:06:04 PM PDT 24
Peak memory 273172 kb
Host smart-ef7ab842-f742-41bd-95e6-cc403c1f2917
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630899160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2630899160
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2994395815
Short name T382
Test name
Test status
Simulation time 2231827015 ps
CPU time 136.34 seconds
Started Jul 16 05:41:17 PM PDT 24
Finished Jul 16 05:43:37 PM PDT 24
Peak memory 257108 kb
Host smart-b6fb7a11-c1b7-4d2a-9649-05a3e9c88dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29943
95815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2994395815
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.4228584071
Short name T454
Test name
Test status
Simulation time 1351594732 ps
CPU time 69.71 seconds
Started Jul 16 05:41:14 PM PDT 24
Finished Jul 16 05:42:26 PM PDT 24
Peak memory 249672 kb
Host smart-7c9833de-f47a-496d-8a1d-f5aeb5265fb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42285
84071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.4228584071
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3222597270
Short name T543
Test name
Test status
Simulation time 960255165665 ps
CPU time 2738.7 seconds
Started Jul 16 05:41:18 PM PDT 24
Finished Jul 16 06:27:00 PM PDT 24
Peak memory 289352 kb
Host smart-ebef1ee7-36f4-4d80-a4ae-38e2500a05ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222597270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3222597270
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3659769060
Short name T563
Test name
Test status
Simulation time 54522783475 ps
CPU time 3202.73 seconds
Started Jul 16 05:41:18 PM PDT 24
Finished Jul 16 06:34:44 PM PDT 24
Peak memory 289516 kb
Host smart-aeeaca88-63df-4b40-8fff-232bd5fe4f69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659769060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3659769060
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1301293376
Short name T353
Test name
Test status
Simulation time 369417546 ps
CPU time 7.09 seconds
Started Jul 16 05:41:16 PM PDT 24
Finished Jul 16 05:41:26 PM PDT 24
Peak memory 249116 kb
Host smart-9235daee-8318-47a5-8e0b-d59f79522180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13012
93376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1301293376
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1239987517
Short name T98
Test name
Test status
Simulation time 1163143273 ps
CPU time 26.25 seconds
Started Jul 16 05:41:18 PM PDT 24
Finished Jul 16 05:41:47 PM PDT 24
Peak memory 249312 kb
Host smart-229b69f3-cb61-41c9-a144-a6c101cee42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12399
87517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1239987517
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1430018168
Short name T248
Test name
Test status
Simulation time 458365537 ps
CPU time 25.62 seconds
Started Jul 16 05:41:15 PM PDT 24
Finished Jul 16 05:41:44 PM PDT 24
Peak memory 249396 kb
Host smart-bcf35890-e4e8-4cb8-997e-f091e3773c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14300
18168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1430018168
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3858092951
Short name T377
Test name
Test status
Simulation time 364717888 ps
CPU time 38.25 seconds
Started Jul 16 05:41:14 PM PDT 24
Finished Jul 16 05:41:54 PM PDT 24
Peak memory 249484 kb
Host smart-1c960b6c-2fe9-4578-8a34-4479fb12d5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38580
92951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3858092951
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1631410862
Short name T44
Test name
Test status
Simulation time 42942196196 ps
CPU time 1352.05 seconds
Started Jul 16 05:41:15 PM PDT 24
Finished Jul 16 06:03:51 PM PDT 24
Peak memory 290148 kb
Host smart-5862a848-ee71-4be6-9b72-bb90e5ba693b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631410862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1631410862
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.757540638
Short name T683
Test name
Test status
Simulation time 173874396102 ps
CPU time 4246.95 seconds
Started Jul 16 05:41:16 PM PDT 24
Finished Jul 16 06:52:06 PM PDT 24
Peak memory 338660 kb
Host smart-4ad8a5d3-04e6-4ab5-9f32-6d0fd4e39267
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757540638 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.757540638
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2116654796
Short name T453
Test name
Test status
Simulation time 44192281463 ps
CPU time 1181.41 seconds
Started Jul 16 05:41:16 PM PDT 24
Finished Jul 16 06:01:01 PM PDT 24
Peak memory 289280 kb
Host smart-ea60769a-aea0-4b96-b3f6-08f07aee8069
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116654796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2116654796
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.289972923
Short name T181
Test name
Test status
Simulation time 3713251792 ps
CPU time 79.13 seconds
Started Jul 16 05:41:16 PM PDT 24
Finished Jul 16 05:42:39 PM PDT 24
Peak memory 257568 kb
Host smart-74b0a2b8-3026-430d-8aae-33b9dad5cc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28997
2923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.289972923
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3503540780
Short name T517
Test name
Test status
Simulation time 63996792 ps
CPU time 2.91 seconds
Started Jul 16 05:41:20 PM PDT 24
Finished Jul 16 05:41:24 PM PDT 24
Peak memory 240456 kb
Host smart-78257289-4079-46bc-ace6-d2ed25c20355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35035
40780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3503540780
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2021580877
Short name T299
Test name
Test status
Simulation time 179543719842 ps
CPU time 2999.39 seconds
Started Jul 16 05:41:15 PM PDT 24
Finished Jul 16 06:31:18 PM PDT 24
Peak memory 282044 kb
Host smart-69b635aa-adb0-4444-8faa-3d2af9a49d68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021580877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2021580877
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3082424709
Short name T522
Test name
Test status
Simulation time 120032106022 ps
CPU time 784.86 seconds
Started Jul 16 05:41:15 PM PDT 24
Finished Jul 16 05:54:23 PM PDT 24
Peak memory 273940 kb
Host smart-c2aab56a-85e2-4d0b-969e-5adec62a628e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082424709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3082424709
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2893764403
Short name T301
Test name
Test status
Simulation time 1371988488 ps
CPU time 57.23 seconds
Started Jul 16 05:41:20 PM PDT 24
Finished Jul 16 05:42:19 PM PDT 24
Peak memory 249040 kb
Host smart-bcae6cd6-a6f2-4ebe-a1b2-03c1c5d8a5cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893764403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2893764403
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.4008193479
Short name T646
Test name
Test status
Simulation time 402931331 ps
CPU time 21.33 seconds
Started Jul 16 05:41:17 PM PDT 24
Finished Jul 16 05:41:42 PM PDT 24
Peak memory 256780 kb
Host smart-8eefeaa3-5915-4766-945b-ff6015327a41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40081
93479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.4008193479
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2880556775
Short name T564
Test name
Test status
Simulation time 703676486 ps
CPU time 40.89 seconds
Started Jul 16 05:41:16 PM PDT 24
Finished Jul 16 05:42:00 PM PDT 24
Peak memory 248812 kb
Host smart-1d2b1fec-4367-4499-bad9-050dced897c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28805
56775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2880556775
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.557198933
Short name T492
Test name
Test status
Simulation time 290716488 ps
CPU time 42.27 seconds
Started Jul 16 05:41:14 PM PDT 24
Finished Jul 16 05:41:59 PM PDT 24
Peak memory 249092 kb
Host smart-10cee226-3090-46ce-8d53-5d7b4e4cf605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55719
8933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.557198933
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.4091809249
Short name T677
Test name
Test status
Simulation time 1209238742 ps
CPU time 75.34 seconds
Started Jul 16 05:41:35 PM PDT 24
Finished Jul 16 05:42:51 PM PDT 24
Peak memory 257432 kb
Host smart-6df4952c-2169-4184-bd73-7a40881b6ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40918
09249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.4091809249
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1831471566
Short name T261
Test name
Test status
Simulation time 218229981216 ps
CPU time 4176.18 seconds
Started Jul 16 05:41:16 PM PDT 24
Finished Jul 16 06:50:56 PM PDT 24
Peak memory 298524 kb
Host smart-20614a57-c312-4fa1-93fc-1e742261cd40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831471566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1831471566
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1946004230
Short name T213
Test name
Test status
Simulation time 251702360 ps
CPU time 3.19 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 05:39:18 PM PDT 24
Peak memory 249556 kb
Host smart-40a4a473-b3e7-4a2a-947f-fcf030e48e32
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1946004230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1946004230
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3022484657
Short name T49
Test name
Test status
Simulation time 316747294086 ps
CPU time 1397.31 seconds
Started Jul 16 05:39:10 PM PDT 24
Finished Jul 16 06:02:28 PM PDT 24
Peak memory 289696 kb
Host smart-a7a7e3d7-e41d-4491-a33f-1c048d239edb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022484657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3022484657
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.3394022958
Short name T555
Test name
Test status
Simulation time 1350450924 ps
CPU time 30.18 seconds
Started Jul 16 05:39:08 PM PDT 24
Finished Jul 16 05:39:39 PM PDT 24
Peak memory 249200 kb
Host smart-6b3b4887-4e2c-45e7-800a-5b7fcaa33d63
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3394022958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.3394022958
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3299177625
Short name T214
Test name
Test status
Simulation time 19726047607 ps
CPU time 261.08 seconds
Started Jul 16 05:39:08 PM PDT 24
Finished Jul 16 05:43:30 PM PDT 24
Peak memory 257500 kb
Host smart-ef8cf6b5-f302-4bf3-906c-055b57afbfac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32991
77625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3299177625
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.626788825
Short name T398
Test name
Test status
Simulation time 489712711 ps
CPU time 21.67 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 05:39:37 PM PDT 24
Peak memory 256996 kb
Host smart-a20affba-dd70-4906-ba36-1a38da8603eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62678
8825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.626788825
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2504084920
Short name T579
Test name
Test status
Simulation time 66659351874 ps
CPU time 1630.66 seconds
Started Jul 16 05:39:20 PM PDT 24
Finished Jul 16 06:06:31 PM PDT 24
Peak memory 289884 kb
Host smart-b40f9946-dc02-41a1-9073-76d82d83d2ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504084920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2504084920
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3475113728
Short name T391
Test name
Test status
Simulation time 43337636504 ps
CPU time 495.36 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 05:47:29 PM PDT 24
Peak memory 249268 kb
Host smart-16db354a-78aa-4702-8750-29bc7f118e30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475113728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3475113728
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2727980745
Short name T411
Test name
Test status
Simulation time 5036275458 ps
CPU time 55.71 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 05:40:05 PM PDT 24
Peak memory 249256 kb
Host smart-677ea33f-e3b6-4483-b61f-0a49383adf6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27279
80745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2727980745
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2942801544
Short name T280
Test name
Test status
Simulation time 59705864 ps
CPU time 4.49 seconds
Started Jul 16 05:39:20 PM PDT 24
Finished Jul 16 05:39:26 PM PDT 24
Peak memory 240996 kb
Host smart-cf4e5570-f309-4192-a1ed-b3c0c7c48ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29428
01544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2942801544
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2208040516
Short name T570
Test name
Test status
Simulation time 2503997492 ps
CPU time 44.84 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:39:57 PM PDT 24
Peak memory 249296 kb
Host smart-088d851c-4f16-4cba-b20b-b621688a30af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22080
40516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2208040516
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.545670827
Short name T523
Test name
Test status
Simulation time 1315000539 ps
CPU time 49.4 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 05:39:59 PM PDT 24
Peak memory 257328 kb
Host smart-cc323bd1-3ec7-4ef9-8664-54ca90dcc1f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54567
0827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.545670827
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.677503362
Short name T57
Test name
Test status
Simulation time 369458184549 ps
CPU time 3123.09 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 06:31:15 PM PDT 24
Peak memory 300564 kb
Host smart-bc49014e-a013-4c90-bbb4-bf91dc7015dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677503362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.677503362
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3998659229
Short name T200
Test name
Test status
Simulation time 33572888 ps
CPU time 3.34 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:39:15 PM PDT 24
Peak memory 249540 kb
Host smart-b8ed296e-a516-4a24-8cee-2c6b6028c503
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3998659229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3998659229
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2996329599
Short name T554
Test name
Test status
Simulation time 51134085816 ps
CPU time 1340.91 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 06:01:36 PM PDT 24
Peak memory 289480 kb
Host smart-8f4473e8-ee76-4c9b-bf8d-ab159a0a2cfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996329599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2996329599
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2810365751
Short name T233
Test name
Test status
Simulation time 698893832 ps
CPU time 8.91 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:39:21 PM PDT 24
Peak memory 249272 kb
Host smart-f8c5e3d2-769d-4a9b-b2f6-7587614caf0a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2810365751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2810365751
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2123648876
Short name T414
Test name
Test status
Simulation time 659503199 ps
CPU time 24.32 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 05:39:38 PM PDT 24
Peak memory 256980 kb
Host smart-e1eaeadf-7bf7-44ac-9609-0427dbac7d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21236
48876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2123648876
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2756650616
Short name T286
Test name
Test status
Simulation time 1169865500 ps
CPU time 56.42 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:40:09 PM PDT 24
Peak memory 256524 kb
Host smart-3c1179a9-6123-42b5-91ca-b0e0ce466fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27566
50616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2756650616
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3636603218
Short name T504
Test name
Test status
Simulation time 111442817100 ps
CPU time 1812.84 seconds
Started Jul 16 05:39:14 PM PDT 24
Finished Jul 16 06:09:28 PM PDT 24
Peak memory 273336 kb
Host smart-0395a5f4-546a-4438-84f4-2427d840f26d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636603218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3636603218
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3600999013
Short name T676
Test name
Test status
Simulation time 20425516458 ps
CPU time 1098.11 seconds
Started Jul 16 05:39:14 PM PDT 24
Finished Jul 16 05:57:34 PM PDT 24
Peak memory 290052 kb
Host smart-f07400c0-eed1-4dec-9df6-7f0a05c039c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600999013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3600999013
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1527975158
Short name T226
Test name
Test status
Simulation time 74911619589 ps
CPU time 670.35 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:50:22 PM PDT 24
Peak memory 256008 kb
Host smart-c847188a-8fa6-4f0c-b7df-901df2eeb89a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527975158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1527975158
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.576771232
Short name T276
Test name
Test status
Simulation time 538015330 ps
CPU time 34.38 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:39:47 PM PDT 24
Peak memory 256564 kb
Host smart-6bb3c02d-1786-4c98-adf7-17a62ca37883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57677
1232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.576771232
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2543341049
Short name T61
Test name
Test status
Simulation time 2901130576 ps
CPU time 25.49 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:39:38 PM PDT 24
Peak memory 255912 kb
Host smart-d11b2575-d3f2-43b1-8bc0-e3e061fbb842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25433
41049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2543341049
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1135710184
Short name T468
Test name
Test status
Simulation time 263696257 ps
CPU time 18.83 seconds
Started Jul 16 05:39:10 PM PDT 24
Finished Jul 16 05:39:30 PM PDT 24
Peak memory 249236 kb
Host smart-fcddf5dd-fc6a-41b4-a7c0-6f1bcd949be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11357
10184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1135710184
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.790334657
Short name T394
Test name
Test status
Simulation time 187945753 ps
CPU time 20.52 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 05:39:35 PM PDT 24
Peak memory 249216 kb
Host smart-fa703891-0a17-461c-bae6-cff4325ea158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79033
4657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.790334657
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2561100138
Short name T351
Test name
Test status
Simulation time 631936320 ps
CPU time 30.9 seconds
Started Jul 16 05:39:13 PM PDT 24
Finished Jul 16 05:39:45 PM PDT 24
Peak memory 257276 kb
Host smart-5dcc2cbb-6c50-4eb7-8450-71c25641e5f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561100138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2561100138
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3626609303
Short name T209
Test name
Test status
Simulation time 207655885 ps
CPU time 4.37 seconds
Started Jul 16 05:39:25 PM PDT 24
Finished Jul 16 05:39:31 PM PDT 24
Peak memory 249552 kb
Host smart-6d90293e-6a10-425d-bcd0-b0fb154ffbd7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3626609303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3626609303
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1228775721
Short name T404
Test name
Test status
Simulation time 132989785798 ps
CPU time 2210.75 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 06:16:15 PM PDT 24
Peak memory 273640 kb
Host smart-ded22ddd-d38c-4323-b209-f23ec22abebb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228775721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1228775721
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.611435388
Short name T385
Test name
Test status
Simulation time 3864053506 ps
CPU time 43.71 seconds
Started Jul 16 05:39:21 PM PDT 24
Finished Jul 16 05:40:06 PM PDT 24
Peak memory 249296 kb
Host smart-ce4f0c2e-293f-475d-93eb-aac68e4cae2b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=611435388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.611435388
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1356667604
Short name T577
Test name
Test status
Simulation time 10737170937 ps
CPU time 156.17 seconds
Started Jul 16 05:39:17 PM PDT 24
Finished Jul 16 05:41:54 PM PDT 24
Peak memory 256812 kb
Host smart-acfbd3aa-bd2d-4e32-b175-165b9dc39430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13566
67604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1356667604
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2169376165
Short name T597
Test name
Test status
Simulation time 465983112 ps
CPU time 27.19 seconds
Started Jul 16 05:39:17 PM PDT 24
Finished Jul 16 05:39:45 PM PDT 24
Peak memory 249496 kb
Host smart-0d567063-b440-4044-a24c-bf73e8ecadd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21693
76165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2169376165
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3836222228
Short name T580
Test name
Test status
Simulation time 47037052812 ps
CPU time 2842.7 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 06:26:47 PM PDT 24
Peak memory 282068 kb
Host smart-c939626c-b24c-48e9-9be2-cb3b4b0ec819
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836222228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3836222228
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1869950159
Short name T658
Test name
Test status
Simulation time 61362245124 ps
CPU time 1961.52 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 06:12:07 PM PDT 24
Peak memory 273936 kb
Host smart-7cad0760-9892-4ed4-b8d8-a037c2fcf313
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869950159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1869950159
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2281768906
Short name T9
Test name
Test status
Simulation time 4118642483 ps
CPU time 177.55 seconds
Started Jul 16 05:39:20 PM PDT 24
Finished Jul 16 05:42:19 PM PDT 24
Peak memory 249296 kb
Host smart-96435232-5a7b-437c-9f57-bf064999ffd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281768906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2281768906
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3928030088
Short name T278
Test name
Test status
Simulation time 1268098743 ps
CPU time 78.51 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 05:40:29 PM PDT 24
Peak memory 256752 kb
Host smart-1dc55fcd-e39d-4045-a68e-a0a3ffc8fc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39280
30088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3928030088
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1278192381
Short name T544
Test name
Test status
Simulation time 625061336 ps
CPU time 38.93 seconds
Started Jul 16 05:39:11 PM PDT 24
Finished Jul 16 05:39:51 PM PDT 24
Peak memory 248580 kb
Host smart-92869a53-25a5-4481-bb61-f8d71bbb7547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12781
92381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1278192381
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.680111114
Short name T444
Test name
Test status
Simulation time 744851907 ps
CPU time 13.88 seconds
Started Jul 16 05:39:30 PM PDT 24
Finished Jul 16 05:39:45 PM PDT 24
Peak memory 249200 kb
Host smart-0e96e320-7a98-42c5-b23c-63cfc672be25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68011
1114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.680111114
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1300407049
Short name T647
Test name
Test status
Simulation time 130092159 ps
CPU time 15.98 seconds
Started Jul 16 05:39:09 PM PDT 24
Finished Jul 16 05:39:26 PM PDT 24
Peak memory 249224 kb
Host smart-f706724e-cb47-4ded-b637-1d39b3f68e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13004
07049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1300407049
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.117809457
Short name T65
Test name
Test status
Simulation time 14661546 ps
CPU time 2.43 seconds
Started Jul 16 05:39:21 PM PDT 24
Finished Jul 16 05:39:25 PM PDT 24
Peak memory 249504 kb
Host smart-f9b9cde6-63b3-491a-a1a1-d3b0ca410960
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=117809457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.117809457
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2636414971
Short name T624
Test name
Test status
Simulation time 22841575754 ps
CPU time 1348.46 seconds
Started Jul 16 05:39:22 PM PDT 24
Finished Jul 16 06:01:52 PM PDT 24
Peak memory 273028 kb
Host smart-7d2585b7-9ec9-43ab-b4fd-8ac2e8c72d94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636414971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2636414971
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1391491035
Short name T68
Test name
Test status
Simulation time 625502286 ps
CPU time 10.73 seconds
Started Jul 16 05:39:30 PM PDT 24
Finished Jul 16 05:39:41 PM PDT 24
Peak memory 249168 kb
Host smart-3cf8f212-ae15-4bc4-a872-ff4439bc53cc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1391491035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1391491035
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2218568893
Short name T420
Test name
Test status
Simulation time 1422396302 ps
CPU time 107.62 seconds
Started Jul 16 05:39:22 PM PDT 24
Finished Jul 16 05:41:11 PM PDT 24
Peak memory 251252 kb
Host smart-73ef74dc-4899-42d7-951f-c2ede5d5cbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22185
68893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2218568893
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.632278362
Short name T686
Test name
Test status
Simulation time 777083783 ps
CPU time 17.14 seconds
Started Jul 16 05:39:25 PM PDT 24
Finished Jul 16 05:39:44 PM PDT 24
Peak memory 249264 kb
Host smart-1b37eb00-0fe1-4ba1-827c-3cc26752fe1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63227
8362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.632278362
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.596082698
Short name T323
Test name
Test status
Simulation time 209397639972 ps
CPU time 3564.13 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 06:38:53 PM PDT 24
Peak memory 290188 kb
Host smart-90abfeec-da62-4202-9b30-87d2fa1671e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596082698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.596082698
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.5942939
Short name T652
Test name
Test status
Simulation time 62550138393 ps
CPU time 1736.46 seconds
Started Jul 16 05:39:22 PM PDT 24
Finished Jul 16 06:08:20 PM PDT 24
Peak memory 274052 kb
Host smart-dbb39eba-52e4-4d64-ba32-8e6c27bf88f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5942939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.5942939
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2394396500
Short name T311
Test name
Test status
Simulation time 29852537471 ps
CPU time 527.29 seconds
Started Jul 16 05:39:21 PM PDT 24
Finished Jul 16 05:48:09 PM PDT 24
Peak memory 256240 kb
Host smart-5e86acfe-d3c1-4fae-9632-da5964bebe71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394396500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2394396500
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3352915666
Short name T433
Test name
Test status
Simulation time 990598069 ps
CPU time 37.9 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 05:40:03 PM PDT 24
Peak memory 257064 kb
Host smart-eda82b20-15b8-48dd-afad-40a019e70657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33529
15666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3352915666
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2816192198
Short name T641
Test name
Test status
Simulation time 3533516551 ps
CPU time 57.15 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 05:40:22 PM PDT 24
Peak memory 249404 kb
Host smart-435ace0d-edbf-4180-bca6-5df96e960a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28161
92198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2816192198
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3800882751
Short name T609
Test name
Test status
Simulation time 68165193 ps
CPU time 9.05 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 05:39:34 PM PDT 24
Peak memory 248728 kb
Host smart-dd6f5dab-99ad-4ab6-bb1a-5394da56b881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38008
82751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3800882751
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2515257372
Short name T650
Test name
Test status
Simulation time 848287974 ps
CPU time 23.32 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 05:39:52 PM PDT 24
Peak memory 257448 kb
Host smart-e3fc2204-7b08-4888-b9b4-54b436a8a9aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25152
57372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2515257372
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.351275471
Short name T210
Test name
Test status
Simulation time 44771765 ps
CPU time 3.76 seconds
Started Jul 16 05:39:28 PM PDT 24
Finished Jul 16 05:39:33 PM PDT 24
Peak memory 249540 kb
Host smart-2fc7ccd7-48b0-4e63-87ab-dc92473a465f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=351275471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.351275471
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3939000853
Short name T224
Test name
Test status
Simulation time 27332376318 ps
CPU time 736.98 seconds
Started Jul 16 05:39:21 PM PDT 24
Finished Jul 16 05:51:40 PM PDT 24
Peak memory 273708 kb
Host smart-16aa4889-85bd-48fc-b3d8-c443e0dbca9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939000853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3939000853
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3811502728
Short name T179
Test name
Test status
Simulation time 263524738 ps
CPU time 11.89 seconds
Started Jul 16 05:39:30 PM PDT 24
Finished Jul 16 05:39:43 PM PDT 24
Peak memory 249236 kb
Host smart-70cb7f43-c3c0-4bd4-8b83-a8cf04767c95
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3811502728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3811502728
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.334403031
Short name T350
Test name
Test status
Simulation time 19164778232 ps
CPU time 293.67 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 05:44:19 PM PDT 24
Peak memory 257144 kb
Host smart-36358c70-0812-4fa5-be38-02b9284b425e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33440
3031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.334403031
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.963156209
Short name T606
Test name
Test status
Simulation time 1713383822 ps
CPU time 48.77 seconds
Started Jul 16 05:39:21 PM PDT 24
Finished Jul 16 05:40:12 PM PDT 24
Peak memory 256392 kb
Host smart-5926171a-eb40-4bbb-b018-18ca2b48d74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96315
6209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.963156209
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2887158166
Short name T321
Test name
Test status
Simulation time 23566805793 ps
CPU time 1187.22 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 05:59:13 PM PDT 24
Peak memory 287856 kb
Host smart-ead0afb9-0c3b-4641-8fa9-7f023b983b27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887158166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2887158166
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3582398891
Short name T217
Test name
Test status
Simulation time 18637876885 ps
CPU time 1056.19 seconds
Started Jul 16 05:39:22 PM PDT 24
Finished Jul 16 05:57:00 PM PDT 24
Peak memory 273976 kb
Host smart-cab13a51-23df-4ac7-a1d0-26e7a00604ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582398891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3582398891
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.4294298325
Short name T85
Test name
Test status
Simulation time 24063027901 ps
CPU time 486.14 seconds
Started Jul 16 05:39:21 PM PDT 24
Finished Jul 16 05:47:28 PM PDT 24
Peak memory 249012 kb
Host smart-7e28f0e7-1c48-43b0-9501-6bda99b8121b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294298325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.4294298325
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.288548077
Short name T46
Test name
Test status
Simulation time 5446444431 ps
CPU time 61.83 seconds
Started Jul 16 05:39:27 PM PDT 24
Finished Jul 16 05:40:31 PM PDT 24
Peak memory 257060 kb
Host smart-aa443a15-17f8-4786-bed8-92b4a1a7669e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28854
8077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.288548077
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3584891470
Short name T520
Test name
Test status
Simulation time 49549894 ps
CPU time 6.59 seconds
Started Jul 16 05:39:22 PM PDT 24
Finished Jul 16 05:39:30 PM PDT 24
Peak memory 254252 kb
Host smart-88bc39a5-bb4e-4974-ad86-584e7880dad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35848
91470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3584891470
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3292066291
Short name T348
Test name
Test status
Simulation time 160984777 ps
CPU time 11.65 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 05:39:36 PM PDT 24
Peak memory 253664 kb
Host smart-05780efe-b5e0-4f7d-86ae-da36554b2214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32920
66291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3292066291
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1778138416
Short name T228
Test name
Test status
Simulation time 305733277 ps
CPU time 17.09 seconds
Started Jul 16 05:39:24 PM PDT 24
Finished Jul 16 05:39:43 PM PDT 24
Peak memory 254776 kb
Host smart-7eb81f76-6d35-40eb-b459-369c234ef716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17781
38416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1778138416
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1994725196
Short name T58
Test name
Test status
Simulation time 97657145369 ps
CPU time 2211.3 seconds
Started Jul 16 05:39:23 PM PDT 24
Finished Jul 16 06:16:16 PM PDT 24
Peak memory 305724 kb
Host smart-560c289a-4461-4e11-a0a1-c971f443d8be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994725196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1994725196
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3018476347
Short name T257
Test name
Test status
Simulation time 71779011936 ps
CPU time 2895.62 seconds
Started Jul 16 05:39:26 PM PDT 24
Finished Jul 16 06:27:44 PM PDT 24
Peak memory 306456 kb
Host smart-ace28b71-58a4-402f-9a42-9ebb6f3737b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018476347 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3018476347
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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