Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	67980	1			T5	3403		T15	2		T17	7
class_i[0x1]	84707	1			T5	10		T13	6		T15	17
class_i[0x2]	62119	1			T3	91		T15	8		T17	4
class_i[0x3]	54772	1			T5	12		T15	5		T17	8

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	70344	1			T3	38		T5	1116		T15	4
alert[0x1]	69430	1			T3	15		T5	2029		T15	8
alert[0x2]	66538	1			T3	6		T5	184		T13	1
alert[0x3]	63266	1			T3	32		T5	96		T13	5

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

269285

1

T3

91

T5

3425

T13

6

esc_ping_fail

293

1

T7

2

T8

1

T9

3

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	70262	1			T3	38		T5	1116		T15	4
esc_integrity_fail	alert[0x1]	69352	1			T3	15		T5	2029		T15	8
esc_integrity_fail	alert[0x2]	66465	1			T3	6		T5	184		T13	1
esc_integrity_fail	alert[0x3]	63206	1			T3	32		T5	96		T13	5
esc_ping_fail	alert[0x0]	82	1			T9	1		T293	1		T63	2
esc_ping_fail	alert[0x1]	78	1			T7	1		T9	1		T219	1
esc_ping_fail	alert[0x2]	73	1			T8	1		T293	1		T63	2
esc_ping_fail	alert[0x3]	60	1			T7	1		T9	1		T293	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	67910	1			T5	3403		T15	2		T17	7
esc_integrity_fail	class_i[0x1]	84660	1			T5	10		T13	6		T15	17
esc_integrity_fail	class_i[0x2]	62050	1			T3	91		T15	8		T17	4
esc_integrity_fail	class_i[0x3]	54665	1			T5	12		T15	5		T17	8
esc_ping_fail	class_i[0x0]	70	1			T7	2		T9	1		T219	1
esc_ping_fail	class_i[0x1]	47	1			T8	1		T287	1		T289	1
esc_ping_fail	class_i[0x2]	69	1			T9	1		T293	1		T219	1
esc_ping_fail	class_i[0x3]	107	1			T9	1		T293	2		T63	9