Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	655097595	0	0	624
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	655097595	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	655097595	654909513	0	0
tb.dut.CheckAccuCntDw	0	0	624	624	0	0
tb.dut.CheckEscCntDw	0	0	624	624	0	0
tb.dut.CheckNAlerts	0	0	624	624	0	0
tb.dut.CheckNClasses	0	0	624	624	0	0
tb.dut.CheckNEscSev	0	0	624	624	0	0
tb.dut.CrashdumpKnownO_A	0	0	655097595	654909513	0	0
tb.dut.EdnKnownO_A	0	0	655097595	654909513	0	0
tb.dut.EscPKnownO_A	0	0	655097595	654909513	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	655097595	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	655097595	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	655097595	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	655097595	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	655097595	90	0	0
tb.dut.IrqAKnownO_A	0	0	655097595	654909513	0	0
tb.dut.IrqBKnownO_A	0	0	655097595	654909513	0	0
tb.dut.IrqCKnownO_A	0	0	655097595	654909513	0	0
tb.dut.IrqDKnownO_A	0	0	655097595	654909513	0	0
tb.dut.TlAReadyKnownO_A	0	0	655097595	654909513	0	0
tb.dut.TlDValidKnownO_A	0	0	655097595	654909513	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	678819125	2431121	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	678819125	12230	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	678819125	12285	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	678819125	12247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	678819125	12116	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	678819125	12230	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	678819125	12076	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	678819125	12389	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	678819125	11938	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	678819125	11896	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	678819125	12291	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	678819125	12182	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	678819125	11801	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	678819125	12103	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	678819125	11785	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	678819125	12322	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	678819125	12111	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	678819125	12047	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	678819125	11910	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	678819125	12456	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	678819125	12251	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	678819125	12249	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	678819125	12117	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	678819125	12411	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	678819125	12344	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	678819125	11748	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	678819125	12191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	678819125	12018	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	678819125	12660	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	678819125	12223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	678819125	12060	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	678819125	12134	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	678819125	12356	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	678819125	12342	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	678819125	12111	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	678819125	12269	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	678819125	12260	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	678819125	12153	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	678819125	12052	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	678819125	12118	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	678819125	12165	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	678819125	11934	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	678819125	12359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	678819125	12176	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	678819125	12047	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	678819125	12210	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	678819125	12274	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	678819125	12191	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	678819125	11951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	678819125	12226	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	678819125	11819	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	678819125	11969	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	678819125	12418	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	678819125	11974	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	678819125	12378	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	678819125	12069	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	678819125	12175	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	678819125	12139	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	678819125	12152	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	678819125	12243	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	678819125	12492	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	678819125	12068	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	678819125	12013	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	678819125	12100	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	678819125	12359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	678819125	12243	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	678819125	12138	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	678819125	12065	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	678819125	12484	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	678819125	12129	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	678819125	22624	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	678819125	12027	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	678819125	12183	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	678819125	12259	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	678819125	11935	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	678819125	12177	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	678819125	11703	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	678819125	12204	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	678819125	12107	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	655097595	3588	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	655097595	204858	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	655097595	296253826	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	655097595	331	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	655097595	921	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	655097595	52	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	655097595	493	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	654280250	229764528	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	655097595	1028	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	655097595	1003	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	655097595	976	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	655097595	958	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	655097595	1620	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	655097595	168874	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	655097595	1502	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	655097595	65	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	655097595	1680	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	655097595	1410	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	654278676	654205473	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	655097595	654909513	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	655097595	5736	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	655097595	206378	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	655097595	365650442	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	655097595	336	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	655097595	508	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	655097595	22	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	655097595	229	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	654280250	275182980	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	655097595	588	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	655097595	579	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	655097595	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	655097595	556	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	655097595	1211	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	655097595	141320	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	655097595	1128	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	655097595	61	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	655097595	1616	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	655097595	1346	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	654278676	654205473	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	655097595	654909513	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	655097595	3662	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	655097595	198574	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	655097595	375872319	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	655097595	352	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	655097595	520	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	655097595	20	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	655097595	273	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	654280250	292512024	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	655097595	606	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	655097595	594	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	655097595	583	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	655097595	575	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	655097595	1517	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	655097595	161143	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	655097595	1423	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	655097595	73	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	655097595	1628	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	655097595	1358	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	654278676	654205473	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	655097595	654909513	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	655097595	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	655097595	1775	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	655097595	208803	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	655097595	380862600	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	655097595	311	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	655097595	530	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	655097595	24	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	655097595	262	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	654280250	293949802	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	655097595	591	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	655097595	582	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	655097595	574	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	655097595	559	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	655097595	2077	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	655097595	210515	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	655097595	2004	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	655097595	49	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	655097595	1664	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	655097595	1394	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	654278676	654205473	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	655097595	654909513	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	678819125	125528993	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	678819125	678150126	0	0
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