Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	161	1			T5	1		T13	3		T15	1
index[0x1]	185	1			T1	1		T13	1		T17	1
index[0x2]	157	1			T2	2		T13	6		T16	1
index[0x3]	175	1			T5	1		T13	3		T18	2

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	241	1			T5	1		T13	8		T15	1
lens_less_than_1000[1]	121	1			T13	3		T17	1		T18	1
lens_less_than_1000[2]	112	1			T1	1		T2	2		T13	1
lens_less_than_1000[3]	54	1			T22	3		T18	2		T218	1
lens_less_than_1000[4]	40	1			T16	1		T26	2		T85	1
lens_less_than_1000[5]	44	1			T16	1		T18	1		T25	1
lens_less_than_1000[6]	24	1			T114	1		T217	2		T220	1
lens_less_than_1000[7]	19	1			T93	1		T67	2		T97	1
lens_less_than_1000[8]	12	1			T5	1		T13	1		T18	1
lens_less_than_1000[9]	1	1			T256	1		-	-		-	-
len_2	10	1			T82	1		T98	1		T190	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x2] , index[0x3]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	59	1			T13	2		T15	1		T71	1
index[0x0]	lens_less_than_1000[1]	20	1			T114	1		T93	1		T67	1
index[0x0]	lens_less_than_1000[2]	32	1			T13	1		T240	1		T257	1
index[0x0]	lens_less_than_1000[3]	18	1			T22	3		T18	1		T218	1
index[0x0]	lens_less_than_1000[4]	5	1			T85	1		T108	1		T258	1
index[0x0]	lens_less_than_1000[5]	14	1			T16	1		T25	1		T82	1
index[0x0]	lens_less_than_1000[6]	5	1			T259	1		T260	1		T261	1
index[0x0]	lens_less_than_1000[7]	5	1			T67	2		T105	1		T225	1
index[0x0]	lens_less_than_1000[8]	2	1			T5	1		T85	1		-	-
index[0x0]	len_2	1	1			T262	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	69	1			T13	1		T74	1		T46	1
index[0x1]	lens_less_than_1000[1]	40	1			T17	1		T18	1		T80	1
index[0x1]	lens_less_than_1000[2]	27	1			T1	1		T18	2		T46	1
index[0x1]	lens_less_than_1000[3]	8	1			T48	1		T49	1		T67	1
index[0x1]	lens_less_than_1000[4]	7	1			T106	1		T242	1		T190	1
index[0x1]	lens_less_than_1000[5]	14	1			T18	1		T82	1		T263	1
index[0x1]	lens_less_than_1000[6]	8	1			T220	1		T258	1		T264	1
index[0x1]	lens_less_than_1000[7]	4	1			T265	1		T184	2		T266	1
index[0x1]	lens_less_than_1000[8]	4	1			T18	1		T116	1		T267	1
index[0x1]	lens_less_than_1000[9]	1	1			T256	1		-	-		-	-
index[0x1]	len_2	3	1			T82	1		T98	1		T268	1
index[0x2]	lens_less_than_1000[0]	61	1			T13	3		T18	1		T26	1
index[0x2]	lens_less_than_1000[1]	24	1			T13	3		T72	1		T115	1
index[0x2]	lens_less_than_1000[2]	25	1			T2	2		T22	1		T26	1
index[0x2]	lens_less_than_1000[3]	12	1			T93	1		T269	1		T57	1
index[0x2]	lens_less_than_1000[4]	11	1			T16	1		T26	1		T49	1
index[0x2]	lens_less_than_1000[5]	10	1			T113	1		T82	1		T93	1
index[0x2]	lens_less_than_1000[6]	4	1			T114	1		T217	1		T107	1
index[0x2]	lens_less_than_1000[7]	5	1			T97	1		T56	1		T57	1
index[0x2]	lens_less_than_1000[8]	2	1			T270	1		T271	1		-	-
index[0x2]	len_2	3	1			T272	1		T273	1		T274	1
index[0x3]	lens_less_than_1000[0]	52	1			T5	1		T13	2		T18	1
index[0x3]	lens_less_than_1000[1]	37	1			T73	1		T38	1		T81	1
index[0x3]	lens_less_than_1000[2]	28	1			T46	1		T82	1		T218	1
index[0x3]	lens_less_than_1000[3]	16	1			T18	1		T48	1		T95	1
index[0x3]	lens_less_than_1000[4]	17	1			T26	1		T49	1		T229	1
index[0x3]	lens_less_than_1000[5]	6	1			T275	1		T276	1		T251	1
index[0x3]	lens_less_than_1000[6]	7	1			T217	1		T58	2		T277	1
index[0x3]	lens_less_than_1000[7]	5	1			T93	1		T258	1		T278	1
index[0x3]	lens_less_than_1000[8]	4	1			T13	1		T91	1		T183	1
index[0x3]	len_2	3	1			T190	1		T279	1		T280	1