Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	65	1			T5	2		T13	3		T18	1
class_index[0x1]	61	1			T5	1		T70	1		T46	4
class_index[0x2]	73	1			T23	1		T71	1		T77	1
class_index[0x3]	49	1			T26	1		T27	1		T46	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	102	1			T13	1		T23	1		T18	1
intr_timeout_cnt[1]	51	1			T13	2		T71	1		T77	1
intr_timeout_cnt[2]	22	1			T5	3		T46	1		T93	1
intr_timeout_cnt[3]	20	1			T84	1		T86	1		T89	1
intr_timeout_cnt[4]	12	1			T70	1		T86	1		T55	1
intr_timeout_cnt[5]	12	1			T26	1		T82	1		T240	1
intr_timeout_cnt[6]	5	1			T82	2		T233	1		T241	1
intr_timeout_cnt[7]	6	1			T85	1		T56	1		T60	2
intr_timeout_cnt[8]	7	1			T81	1		T242	2		T61	1
intr_timeout_cnt[9]	11	1			T82	1		T95	1		T56	2

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	26	1			T13	1		T18	1		T26	1
class_index[0x0]	intr_timeout_cnt[1]	13	1			T13	2		T83	1		T98	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T5	2		T93	1		T88	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T86	1		T54	1		T190	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T70	1		T55	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	4	1			T240	1		T98	1		T60	2
class_index[0x0]	intr_timeout_cnt[6]	2	1			T233	1		T241	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T81	1		T61	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T56	1		T243	1		T244	1
class_index[0x1]	intr_timeout_cnt[0]	23	1			T70	1		T46	4		T35	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T62	1		T87	1		T116	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T5	1		T245	1		T190	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T89	1		T246	1		T243	1
class_index[0x1]	intr_timeout_cnt[4]	7	1			T86	1		T58	4		T247	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T242	1		T248	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T249	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T250	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	4	1			T56	1		T251	1		T252	1
class_index[0x2]	intr_timeout_cnt[0]	33	1			T23	1		T76	1		T84	1
class_index[0x2]	intr_timeout_cnt[1]	15	1			T71	1		T77	1		T26	1
class_index[0x2]	intr_timeout_cnt[2]	1	1			T86	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[3]	5	1			T84	1		T54	1		T190	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T58	1		T251	1		T183	1
class_index[0x2]	intr_timeout_cnt[5]	4	1			T82	1		T247	1		T249	2
class_index[0x2]	intr_timeout_cnt[6]	2	1			T82	1		T248	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	5	1			T85	1		T56	1		T60	2
class_index[0x2]	intr_timeout_cnt[8]	2	1			T242	1		T252	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	3	1			T95	1		T253	1		T254	1
class_index[0x3]	intr_timeout_cnt[0]	20	1			T27	1		T82	1		T114	1
class_index[0x3]	intr_timeout_cnt[1]	11	1			T81	1		T93	1		T242	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T46	1		T86	1		T99	1
class_index[0x3]	intr_timeout_cnt[3]	6	1			T98	1		T242	1		T241	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T26	1		T242	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T82	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T242	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T82	1		-	-		-	-