Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	358043	1			T1	1859		T2	31		T3	15
all_values[1]	358043	1			T1	1859		T2	31		T3	15
all_values[2]	358043	1			T1	1859		T2	31		T3	15
all_values[3]	358043	1			T1	1859		T2	31		T3	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

713655

1

T1

3817

T2

60

T3

36

auto[1]

718517

1

T1

3619

T2

64

T3

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

844783

1

T1

3738

T2

64

T3

11

auto[1]

587389

1

T1

3698

T2

60

T3

49

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	101402	1			T1	470		T2	9		T3	3
all_values[0]	auto[0]	auto[1]	77260	1			T1	463		T2	8		T3	9
all_values[0]	auto[1]	auto[0]	102208	1			T1	466		T2	7		T3	1
all_values[0]	auto[1]	auto[1]	77173	1			T1	460		T2	7		T3	2
all_values[1]	auto[0]	auto[0]	106560	1			T1	477		T2	8		T3	2
all_values[1]	auto[0]	auto[1]	71641	1			T1	476		T2	7		T3	9
all_values[1]	auto[1]	auto[0]	108045	1			T1	453		T2	8		T3	1
all_values[1]	auto[1]	auto[1]	71797	1			T1	453		T2	8		T3	3
all_values[2]	auto[0]	auto[0]	105909	1			T1	475		T2	8		T3	1
all_values[2]	auto[0]	auto[1]	72037	1			T1	471		T2	8		T3	5
all_values[2]	auto[1]	auto[0]	107658	1			T1	458		T2	8		T19	10
all_values[2]	auto[1]	auto[1]	72439	1			T1	455		T2	7		T3	9
all_values[3]	auto[0]	auto[0]	106026	1			T1	500		T2	6		T3	2
all_values[3]	auto[0]	auto[1]	72820	1			T1	485		T2	6		T3	5
all_values[3]	auto[1]	auto[0]	106975	1			T1	439		T2	10		T3	1
all_values[3]	auto[1]	auto[1]	72222	1			T1	435		T2	9		T3	7