Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	358043	1			T1	1859		T2	31		T3	15
all_pins[1]	358043	1			T1	1859		T2	31		T3	15
all_pins[2]	358043	1			T1	1859		T2	31		T3	15
all_pins[3]	358043	1			T1	1859		T2	31		T3	15

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1138541	1			T1	5633		T2	93		T3	39
values[0x1]	293631	1			T1	1803		T2	31		T3	21
transitions[0x0=>0x1]	194394	1			T1	1153		T2	21		T3	11
transitions[0x1=>0x0]	194660	1			T1	1153		T2	22		T3	11

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	280870	1			T1	1399		T2	24		T3	13
all_pins[0]	values[0x1]	77173	1			T1	460		T2	7		T3	2
all_pins[0]	transitions[0x0=>0x1]	76523	1			T1	460		T2	6		T19	10
all_pins[0]	transitions[0x1=>0x0]	71838	1			T1	435		T2	9		T3	5
all_pins[1]	values[0x0]	286246	1			T1	1406		T2	23		T3	12
all_pins[1]	values[0x1]	71797	1			T1	453		T2	8		T3	3
all_pins[1]	transitions[0x0=>0x1]	38657	1			T1	227		T2	5		T3	2
all_pins[1]	transitions[0x1=>0x0]	44033	1			T1	234		T2	4		T3	1
all_pins[2]	values[0x0]	285604	1			T1	1404		T2	24		T3	6
all_pins[2]	values[0x1]	72439	1			T1	455		T2	7		T3	9
all_pins[2]	transitions[0x0=>0x1]	39570	1			T1	240		T2	4		T3	7
all_pins[2]	transitions[0x1=>0x0]	38928	1			T1	238		T2	5		T3	1
all_pins[3]	values[0x0]	285821	1			T1	1424		T2	22		T3	8
all_pins[3]	values[0x1]	72222	1			T1	435		T2	9		T3	7
all_pins[3]	transitions[0x0=>0x1]	39644	1			T1	226		T2	6		T3	2
all_pins[3]	transitions[0x1=>0x0]	39861	1			T1	246		T2	4		T3	4