Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	96219	1			T1	511		T6	664		T13	1194
accum_cnt_1000	226935	1			T1	456		T4	1097		T5	1034
accum_cnt_100	26053	1			T1	25		T4	71		T5	305
accum_cnt_50	70528	1			T1	20		T2	4		T3	4
accum_cnt_10	178863	1			T1	4221		T2	62		T3	34
accum_cnt_0	408824	1			T1	11		T2	30		T3	38

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	264939	1			T1	1407		T2	24		T3	19
class_index[0x1]	264939	1			T1	1407		T2	24		T3	19
class_index[0x2]	264939	1			T1	1407		T2	24		T3	19
class_index[0x3]	264939	1			T1	1407		T2	24		T3	19

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	27112	1			T13	720		T18	226		T72	33
class_index[0x0]	accum_cnt_1000	67140	1			T5	315		T13	649		T22	29
class_index[0x0]	accum_cnt_100	8120	1			T5	90		T13	35		T43	8
class_index[0x0]	accum_cnt_50	21694	1			T3	4		T20	10		T5	241
class_index[0x0]	accum_cnt_10	42033	1			T1	1405		T2	24		T3	15
class_index[0x0]	accum_cnt_0	88106	1			T1	2		T19	3		T20	6
class_index[0x1]	accum_cnt_2000	23855	1			T13	474		T15	457		T16	534
class_index[0x1]	accum_cnt_1000	56646	1			T5	433		T6	1102		T13	454
class_index[0x1]	accum_cnt_100	6222	1			T5	120		T6	104		T13	75
class_index[0x1]	accum_cnt_50	20400	1			T19	17		T5	90		T6	75
class_index[0x1]	accum_cnt_10	36756	1			T1	1405		T2	1		T19	7
class_index[0x1]	accum_cnt_0	108261	1			T1	2		T2	23		T3	19
class_index[0x2]	accum_cnt_2000	20449	1			T1	511		T15	602		T16	70
class_index[0x2]	accum_cnt_1000	50435	1			T1	456		T4	1097		T5	182
class_index[0x2]	accum_cnt_100	5271	1			T1	25		T4	71		T5	36
class_index[0x2]	accum_cnt_50	11712	1			T1	20		T2	4		T4	62
class_index[0x2]	accum_cnt_10	51541	1			T1	7		T2	15		T3	19
class_index[0x2]	accum_cnt_0	109631	1			T1	4		T2	5		T19	2
class_index[0x3]	accum_cnt_2000	24803	1			T6	664		T14	626		T15	495
class_index[0x3]	accum_cnt_1000	52714	1			T5	104		T6	557		T13	10
class_index[0x3]	accum_cnt_100	6440	1			T5	59		T6	28		T13	43
class_index[0x3]	accum_cnt_50	16722	1			T5	38		T6	24		T13	1576
class_index[0x3]	accum_cnt_10	48533	1			T1	1404		T2	22		T19	1
class_index[0x3]	accum_cnt_0	102826	1			T1	3		T2	2		T3	19