Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	9736	1			T17	47		T18	30		T90	46
alert[0x1]	9554	1			T18	2		T25	3877		T90	54
alert[0x2]	9830	1			T13	9		T75	2		T90	1142
alert[0x3]	16262	1			T18	3		T26	364		T90	5
alert[0x4]	10723	1			T17	1		T18	20		T25	52
alert[0x5]	7404	1			T13	1		T18	121		T75	1
alert[0x6]	13975	1			T18	220		T25	21		T26	14
alert[0x7]	13636	1			T6	31		T22	247		T90	85
alert[0x8]	5674	1			T13	1		T16	10		T17	7
alert[0x9]	11369	1			T5	2		T13	7		T22	7
alert[0xa]	10203	1			T25	42		T286	8		T114	43
alert[0xb]	7995	1			T6	85		T13	8		T286	56
alert[0xc]	6889	1			T7	1		T75	1		T26	64
alert[0xd]	7138	1			T16	2		T18	6		T25	159
alert[0xe]	12312	1			T16	2		T18	1		T46	8
alert[0xf]	7564	1			T25	80		T26	2535		T90	546
alert[0x10]	7177	1			T16	105		T18	376		T27	147
alert[0x11]	5005	1			T13	1		T18	28		T25	316
alert[0x12]	5267	1			T26	2		T90	121		T27	24
alert[0x13]	4585	1			T22	20		T26	32		T90	117
alert[0x14]	5065	1			T16	24		T18	249		T25	174
alert[0x15]	3920	1			T37	1		T114	64		T218	5
alert[0x16]	6995	1			T27	14		T37	1		T286	160
alert[0x17]	3756	1			T17	1		T18	17		T25	309
alert[0x18]	3459	1			T22	198		T75	1		T85	45
alert[0x19]	5982	1			T16	1		T18	18		T26	5
alert[0x1a]	12650	1			T16	4		T18	6		T25	36
alert[0x1b]	3750	1			T6	413		T22	190		T25	47
alert[0x1c]	4442	1			T4	1		T5	3		T18	23
alert[0x1d]	14893	1			T4	2		T5	3		T26	58
alert[0x1e]	7313	1			T16	47		T90	27		T286	202
alert[0x1f]	13512	1			T17	2		T26	55		T90	130
alert[0x20]	7640	1			T18	7		T25	760		T27	19
alert[0x21]	8932	1			T16	6		T22	776		T18	7
alert[0x22]	4002	1			T16	7		T25	10		T75	1
alert[0x23]	6883	1			T25	522		T117	1		T85	1
alert[0x24]	6462	1			T6	251		T26	5		T90	28
alert[0x25]	3537	1			T6	363		T13	17		T15	13
alert[0x26]	3611	1			T18	43		T90	64		T117	1
alert[0x27]	14248	1			T5	5		T6	946		T18	9
alert[0x28]	7552	1			T6	52		T26	9		T90	120
alert[0x29]	6876	1			T13	10		T17	13		T22	448
alert[0x2a]	8200	1			T5	16		T13	4		T46	2
alert[0x2b]	5390	1			T22	905		T18	202		T75	4
alert[0x2c]	9943	1			T5	4		T18	15		T25	12
alert[0x2d]	12203	1			T17	2		T18	188		T7	1
alert[0x2e]	15078	1			T18	35		T25	29		T90	58
alert[0x2f]	24540	1			T6	1354		T13	2		T16	4
alert[0x30]	6542	1			T18	10		T25	90		T90	21
alert[0x31]	8107	1			T6	2		T13	2		T22	130
alert[0x32]	6087	1			T13	1		T90	82		T46	1
alert[0x33]	12308	1			T15	1		T18	2148		T25	466
alert[0x34]	5948	1			T5	1		T6	31		T22	7
alert[0x35]	9411	1			T6	19		T13	2		T18	11
alert[0x36]	9156	1			T13	1		T17	4		T18	6
alert[0x37]	2920	1			T6	38		T13	2		T22	317
alert[0x38]	9642	1			T6	246		T25	1670		T7	1
alert[0x39]	6348	1			T6	3		T16	2		T286	3439
alert[0x3a]	2562	1			T5	4		T6	77		T18	158
alert[0x3b]	2760	1			T16	3		T17	8		T18	8
alert[0x3c]	7599	1			T17	3		T25	1157		T7	1
alert[0x3d]	12188	1			T6	119		T22	33		T25	185
alert[0x3e]	6962	1			T18	94		T25	498		T75	2
alert[0x3f]	5582	1			T6	56		T25	900		T26	21
alert[0x40]	2294	1			T5	6		T25	90		T286	39

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	107140	1			T6	4047		T13	53		T15	14
class_i[0x1]	130577	1			T4	3		T5	28		T6	14
class_i[0x2]	161599	1			T5	14		T6	14		T13	11
class_i[0x3]	130232	1			T5	2		T6	11		T16	15

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

528898

1

T5

44

T6

4086

T13

68

alert_ping_fail

650

1

T4

3

T7

9

T8

6

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	9728	1			T17	47		T18	30		T90	46
alert_integrity_fail	alert[0x1]	9549	1			T18	2		T25	3877		T90	54
alert_integrity_fail	alert[0x2]	9819	1			T13	9		T75	2		T90	1142
alert_integrity_fail	alert[0x3]	16255	1			T18	3		T26	364		T90	5
alert_integrity_fail	alert[0x4]	10712	1			T17	1		T18	20		T25	52
alert_integrity_fail	alert[0x5]	7389	1			T13	1		T18	121		T75	1
alert_integrity_fail	alert[0x6]	13959	1			T18	220		T25	21		T26	14
alert_integrity_fail	alert[0x7]	13626	1			T6	31		T22	247		T90	85
alert_integrity_fail	alert[0x8]	5661	1			T13	1		T16	10		T17	7
alert_integrity_fail	alert[0x9]	11361	1			T5	2		T13	7		T22	7
alert_integrity_fail	alert[0xa]	10193	1			T25	42		T286	8		T114	43
alert_integrity_fail	alert[0xb]	7987	1			T6	85		T13	8		T286	56
alert_integrity_fail	alert[0xc]	6884	1			T75	1		T26	64		T90	557
alert_integrity_fail	alert[0xd]	7130	1			T16	2		T18	6		T25	159
alert_integrity_fail	alert[0xe]	12309	1			T16	2		T18	1		T46	8
alert_integrity_fail	alert[0xf]	7550	1			T25	80		T26	2535		T90	546
alert_integrity_fail	alert[0x10]	7173	1			T16	105		T18	376		T27	147
alert_integrity_fail	alert[0x11]	4996	1			T13	1		T18	28		T25	316
alert_integrity_fail	alert[0x12]	5254	1			T26	2		T90	121		T27	24
alert_integrity_fail	alert[0x13]	4573	1			T22	20		T26	32		T90	117
alert_integrity_fail	alert[0x14]	5060	1			T16	24		T18	249		T25	174
alert_integrity_fail	alert[0x15]	3906	1			T114	64		T218	5		T50	1
alert_integrity_fail	alert[0x16]	6982	1			T27	14		T286	160		T85	114
alert_integrity_fail	alert[0x17]	3742	1			T17	1		T18	17		T25	309
alert_integrity_fail	alert[0x18]	3451	1			T22	198		T75	1		T85	45
alert_integrity_fail	alert[0x19]	5978	1			T16	1		T18	18		T26	5
alert_integrity_fail	alert[0x1a]	12641	1			T16	4		T18	6		T25	36
alert_integrity_fail	alert[0x1b]	3734	1			T6	413		T22	190		T25	47
alert_integrity_fail	alert[0x1c]	4428	1			T5	3		T18	23		T26	10
alert_integrity_fail	alert[0x1d]	14880	1			T5	3		T26	58		T27	153
alert_integrity_fail	alert[0x1e]	7302	1			T16	47		T90	27		T286	202
alert_integrity_fail	alert[0x1f]	13500	1			T17	2		T26	55		T90	130
alert_integrity_fail	alert[0x20]	7628	1			T18	7		T25	760		T27	19
alert_integrity_fail	alert[0x21]	8926	1			T16	6		T22	776		T18	7
alert_integrity_fail	alert[0x22]	3989	1			T16	7		T25	10		T75	1
alert_integrity_fail	alert[0x23]	6875	1			T25	522		T117	1		T85	1
alert_integrity_fail	alert[0x24]	6451	1			T6	251		T26	5		T90	28
alert_integrity_fail	alert[0x25]	3523	1			T6	363		T13	17		T15	13
alert_integrity_fail	alert[0x26]	3605	1			T18	43		T90	64		T117	1
alert_integrity_fail	alert[0x27]	14240	1			T5	5		T6	946		T18	9
alert_integrity_fail	alert[0x28]	7536	1			T6	52		T26	9		T90	120
alert_integrity_fail	alert[0x29]	6865	1			T13	10		T17	13		T22	448
alert_integrity_fail	alert[0x2a]	8193	1			T5	16		T13	4		T46	2
alert_integrity_fail	alert[0x2b]	5381	1			T22	905		T18	202		T75	4
alert_integrity_fail	alert[0x2c]	9932	1			T5	4		T18	15		T25	12
alert_integrity_fail	alert[0x2d]	12190	1			T17	2		T18	188		T90	282
alert_integrity_fail	alert[0x2e]	15064	1			T18	35		T25	29		T90	58
alert_integrity_fail	alert[0x2f]	24527	1			T6	1354		T13	2		T16	4
alert_integrity_fail	alert[0x30]	6534	1			T18	10		T25	90		T90	21
alert_integrity_fail	alert[0x31]	8097	1			T6	2		T13	2		T22	130
alert_integrity_fail	alert[0x32]	6083	1			T13	1		T90	82		T46	1
alert_integrity_fail	alert[0x33]	12296	1			T15	1		T18	2148		T25	466
alert_integrity_fail	alert[0x34]	5936	1			T5	1		T6	31		T22	7
alert_integrity_fail	alert[0x35]	9397	1			T6	19		T13	2		T18	11
alert_integrity_fail	alert[0x36]	9148	1			T13	1		T17	4		T18	6
alert_integrity_fail	alert[0x37]	2908	1			T6	38		T13	2		T22	317
alert_integrity_fail	alert[0x38]	9629	1			T6	246		T25	1670		T46	8
alert_integrity_fail	alert[0x39]	6337	1			T6	3		T16	2		T286	3439
alert_integrity_fail	alert[0x3a]	2555	1			T5	4		T6	77		T18	158
alert_integrity_fail	alert[0x3b]	2756	1			T16	3		T17	8		T18	8
alert_integrity_fail	alert[0x3c]	7587	1			T17	3		T25	1157		T286	66
alert_integrity_fail	alert[0x3d]	12179	1			T6	119		T22	33		T25	185
alert_integrity_fail	alert[0x3e]	6956	1			T18	94		T25	498		T75	2
alert_integrity_fail	alert[0x3f]	5573	1			T6	56		T25	900		T26	21
alert_integrity_fail	alert[0x40]	2290	1			T5	6		T25	90		T286	39
alert_ping_fail	alert[0x0]	8	1			T63	1		T287	1		T288	1
alert_ping_fail	alert[0x1]	5	1			T9	1		T63	1		T230	1
alert_ping_fail	alert[0x2]	11	1			T63	1		T64	1		T230	1
alert_ping_fail	alert[0x3]	7	1			T289	1		T290	1		T291	1
alert_ping_fail	alert[0x4]	11	1			T7	1		T287	1		T289	2
alert_ping_fail	alert[0x5]	15	1			T219	1		T63	2		T65	1
alert_ping_fail	alert[0x6]	16	1			T64	1		T270	1		T292	1
alert_ping_fail	alert[0x7]	10	1			T293	1		T294	1		T292	2
alert_ping_fail	alert[0x8]	13	1			T293	1		T63	2		T65	2
alert_ping_fail	alert[0x9]	8	1			T295	1		T296	1		T288	1
alert_ping_fail	alert[0xa]	10	1			T293	1		T287	1		T213	1
alert_ping_fail	alert[0xb]	8	1			T287	1		T297	1		T298	1
alert_ping_fail	alert[0xc]	5	1			T7	1		T288	1		T299	1
alert_ping_fail	alert[0xd]	8	1			T295	1		T291	1		T300	1
alert_ping_fail	alert[0xe]	3	1			T301	1		T302	1		T303	1
alert_ping_fail	alert[0xf]	14	1			T287	1		T213	1		T270	1
alert_ping_fail	alert[0x10]	4	1			T64	1		T294	1		T304	1
alert_ping_fail	alert[0x11]	9	1			T297	2		T296	1		T299	2
alert_ping_fail	alert[0x12]	13	1			T63	1		T230	1		T289	1
alert_ping_fail	alert[0x13]	12	1			T305	1		T304	1		T306	1
alert_ping_fail	alert[0x14]	5	1			T270	1		T294	1		T297	1
alert_ping_fail	alert[0x15]	14	1			T37	1		T63	1		T64	1
alert_ping_fail	alert[0x16]	13	1			T37	1		T270	1		T294	2
alert_ping_fail	alert[0x17]	14	1			T8	1		T293	1		T219	1
alert_ping_fail	alert[0x18]	8	1			T287	1		T305	2		T307	1
alert_ping_fail	alert[0x19]	4	1			T304	1		T291	1		T303	1
alert_ping_fail	alert[0x1a]	9	1			T7	1		T63	1		T289	1
alert_ping_fail	alert[0x1b]	16	1			T7	1		T230	1		T212	1
alert_ping_fail	alert[0x1c]	14	1			T4	1		T7	1		T37	1
alert_ping_fail	alert[0x1d]	13	1			T4	2		T64	1		T270	1
alert_ping_fail	alert[0x1e]	11	1			T9	1		T301	1		T289	1
alert_ping_fail	alert[0x1f]	12	1			T37	1		T64	1		T230	1
alert_ping_fail	alert[0x20]	12	1			T64	1		T270	1		T305	1
alert_ping_fail	alert[0x21]	6	1			T37	1		T289	1		T297	1
alert_ping_fail	alert[0x22]	13	1			T232	1		T212	2		T308	1
alert_ping_fail	alert[0x23]	8	1			T63	1		T64	1		T65	1
alert_ping_fail	alert[0x24]	11	1			T230	1		T304	1		T297	1
alert_ping_fail	alert[0x25]	14	1			T301	1		T289	1		T305	1
alert_ping_fail	alert[0x26]	6	1			T230	1		T287	1		T295	1
alert_ping_fail	alert[0x27]	8	1			T213	1		T270	1		T304	1
alert_ping_fail	alert[0x28]	16	1			T37	2		T281	1		T219	1
alert_ping_fail	alert[0x29]	11	1			T293	1		T65	1		T305	1
alert_ping_fail	alert[0x2a]	7	1			T65	1		T230	1		T287	1
alert_ping_fail	alert[0x2b]	9	1			T297	1		T309	1		T296	1
alert_ping_fail	alert[0x2c]	11	1			T8	1		T310	1		T311	1
alert_ping_fail	alert[0x2d]	13	1			T7	1		T8	1		T9	1
alert_ping_fail	alert[0x2e]	14	1			T64	1		T287	1		T270	1
alert_ping_fail	alert[0x2f]	13	1			T8	1		T9	1		T294	1
alert_ping_fail	alert[0x30]	8	1			T304	2		T297	1		T296	1
alert_ping_fail	alert[0x31]	10	1			T63	1		T287	1		T270	1
alert_ping_fail	alert[0x32]	4	1			T65	1		T290	1		T312	1
alert_ping_fail	alert[0x33]	12	1			T270	1		T294	1		T307	1
alert_ping_fail	alert[0x34]	12	1			T270	1		T299	1		T290	1
alert_ping_fail	alert[0x35]	14	1			T219	1		T301	1		T270	1
alert_ping_fail	alert[0x36]	8	1			T8	1		T230	1		T304	1
alert_ping_fail	alert[0x37]	12	1			T7	1		T301	1		T295	1
alert_ping_fail	alert[0x38]	13	1			T7	1		T301	1		T289	1
alert_ping_fail	alert[0x39]	11	1			T213	1		T304	1		T309	1
alert_ping_fail	alert[0x3a]	7	1			T9	1		T289	1		T297	1
alert_ping_fail	alert[0x3b]	4	1			T65	1		T287	1		T290	1
alert_ping_fail	alert[0x3c]	12	1			T7	1		T63	1		T294	1
alert_ping_fail	alert[0x3d]	9	1			T8	1		T293	1		T304	1
alert_ping_fail	alert[0x3e]	6	1			T297	1		T313	1		T278	1
alert_ping_fail	alert[0x3f]	9	1			T9	1		T65	1		T270	1
alert_ping_fail	alert[0x40]	4	1			T65	2		T304	1		T290	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	106945	1			T6	4047		T13	53		T15	14
alert_integrity_fail	class_i[0x1]	130431	1			T5	28		T6	14		T13	4
alert_integrity_fail	class_i[0x2]	161427	1			T5	14		T6	14		T13	11
alert_integrity_fail	class_i[0x3]	130095	1			T5	2		T6	11		T16	15
alert_ping_fail	class_i[0x0]	195	1			T7	1		T8	1		T9	2
alert_ping_fail	class_i[0x1]	146	1			T4	3		T7	2		T8	1
alert_ping_fail	class_i[0x2]	172	1			T7	5		T8	3		T9	2
alert_ping_fail	class_i[0x3]	137	1			T7	1		T8	1		T37	7