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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.68 100.00 100.00 100.00 99.38 99.44


Total test records in report: 829
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T766 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1692038846 Jul 17 05:19:07 PM PDT 24 Jul 17 05:19:38 PM PDT 24 1388039112 ps
T767 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3538609840 Jul 17 05:19:07 PM PDT 24 Jul 17 05:19:21 PM PDT 24 86789979 ps
T768 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1450663607 Jul 17 05:19:08 PM PDT 24 Jul 17 05:19:33 PM PDT 24 1319239083 ps
T148 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1236834618 Jul 17 05:18:49 PM PDT 24 Jul 17 05:21:54 PM PDT 24 3079270889 ps
T769 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3477333148 Jul 17 05:18:33 PM PDT 24 Jul 17 05:21:59 PM PDT 24 7102085039 ps
T770 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3040592174 Jul 17 05:18:31 PM PDT 24 Jul 17 05:18:39 PM PDT 24 76577150 ps
T771 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1630541146 Jul 17 05:19:09 PM PDT 24 Jul 17 05:19:15 PM PDT 24 16126476 ps
T142 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1032679173 Jul 17 05:18:51 PM PDT 24 Jul 17 05:23:55 PM PDT 24 17560508735 ps
T772 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.687528543 Jul 17 05:18:47 PM PDT 24 Jul 17 05:19:37 PM PDT 24 2724210589 ps
T166 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4193596220 Jul 17 05:18:43 PM PDT 24 Jul 17 05:18:47 PM PDT 24 49766896 ps
T178 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2202153971 Jul 17 05:19:06 PM PDT 24 Jul 17 05:19:26 PM PDT 24 204074434 ps
T773 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2156627597 Jul 17 05:18:47 PM PDT 24 Jul 17 05:18:50 PM PDT 24 10512311 ps
T174 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1263337716 Jul 17 05:18:31 PM PDT 24 Jul 17 05:18:38 PM PDT 24 106540946 ps
T774 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3507485027 Jul 17 05:18:52 PM PDT 24 Jul 17 05:18:57 PM PDT 24 66753898 ps
T775 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1966821853 Jul 17 05:19:08 PM PDT 24 Jul 17 05:19:13 PM PDT 24 10395116 ps
T776 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.849157590 Jul 17 05:18:44 PM PDT 24 Jul 17 05:18:48 PM PDT 24 22558197 ps
T777 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.453153885 Jul 17 05:18:30 PM PDT 24 Jul 17 05:18:40 PM PDT 24 113341049 ps
T778 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3490728795 Jul 17 05:19:08 PM PDT 24 Jul 17 05:19:13 PM PDT 24 10499565 ps
T779 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2556655625 Jul 17 05:18:48 PM PDT 24 Jul 17 05:19:25 PM PDT 24 565267199 ps
T780 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3829690726 Jul 17 05:19:09 PM PDT 24 Jul 17 05:19:23 PM PDT 24 132952919 ps
T781 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1729903784 Jul 17 05:18:34 PM PDT 24 Jul 17 05:18:38 PM PDT 24 8557630 ps
T782 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3060245140 Jul 17 05:18:45 PM PDT 24 Jul 17 05:18:56 PM PDT 24 198611247 ps
T783 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3965138541 Jul 17 05:19:06 PM PDT 24 Jul 17 05:19:23 PM PDT 24 373922112 ps
T784 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2690056827 Jul 17 05:18:52 PM PDT 24 Jul 17 05:19:03 PM PDT 24 124255554 ps
T785 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.824032078 Jul 17 05:18:32 PM PDT 24 Jul 17 05:19:12 PM PDT 24 1046680011 ps
T786 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2378756904 Jul 17 05:19:08 PM PDT 24 Jul 17 05:19:19 PM PDT 24 1234642863 ps
T787 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4110240375 Jul 17 05:19:08 PM PDT 24 Jul 17 05:19:14 PM PDT 24 21955652 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3130369841 Jul 17 05:18:29 PM PDT 24 Jul 17 05:18:33 PM PDT 24 89957496 ps
T789 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2893913717 Jul 17 05:18:33 PM PDT 24 Jul 17 05:18:44 PM PDT 24 100449764 ps
T790 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2378319570 Jul 17 05:18:30 PM PDT 24 Jul 17 05:18:32 PM PDT 24 8711538 ps
T791 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3688911641 Jul 17 05:18:48 PM PDT 24 Jul 17 05:18:55 PM PDT 24 67000431 ps
T792 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1679302288 Jul 17 05:19:10 PM PDT 24 Jul 17 05:19:16 PM PDT 24 8982086 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.80376094 Jul 17 05:18:26 PM PDT 24 Jul 17 05:18:28 PM PDT 24 6296569 ps
T794 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2007745754 Jul 17 05:18:27 PM PDT 24 Jul 17 05:18:30 PM PDT 24 18189192 ps
T795 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1829835627 Jul 17 05:19:10 PM PDT 24 Jul 17 05:19:17 PM PDT 24 16462579 ps
T796 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.107602854 Jul 17 05:19:07 PM PDT 24 Jul 17 05:19:12 PM PDT 24 7593944 ps
T797 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3014456960 Jul 17 05:18:27 PM PDT 24 Jul 17 05:18:43 PM PDT 24 443893691 ps
T798 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3129337646 Jul 17 05:18:11 PM PDT 24 Jul 17 05:18:27 PM PDT 24 641419151 ps
T799 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2733665441 Jul 17 05:19:07 PM PDT 24 Jul 17 05:19:10 PM PDT 24 8181478 ps
T153 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3672059792 Jul 17 05:18:27 PM PDT 24 Jul 17 05:20:50 PM PDT 24 2151782278 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.4005003608 Jul 17 05:18:31 PM PDT 24 Jul 17 05:18:41 PM PDT 24 102427885 ps
T801 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3744959853 Jul 17 05:18:31 PM PDT 24 Jul 17 05:20:38 PM PDT 24 6174459884 ps
T802 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3933037859 Jul 17 05:18:31 PM PDT 24 Jul 17 05:18:53 PM PDT 24 174297315 ps
T803 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.271961653 Jul 17 05:18:31 PM PDT 24 Jul 17 05:22:07 PM PDT 24 14331314771 ps
T804 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3475680321 Jul 17 05:18:33 PM PDT 24 Jul 17 05:18:42 PM PDT 24 121176354 ps
T805 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.222248075 Jul 17 05:18:33 PM PDT 24 Jul 17 05:18:41 PM PDT 24 264235954 ps
T806 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2556407142 Jul 17 05:18:43 PM PDT 24 Jul 17 05:18:51 PM PDT 24 213038929 ps
T807 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3196747883 Jul 17 05:19:10 PM PDT 24 Jul 17 05:19:22 PM PDT 24 133174678 ps
T808 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3038448823 Jul 17 05:18:32 PM PDT 24 Jul 17 05:18:40 PM PDT 24 83099524 ps
T150 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4218403268 Jul 17 05:18:32 PM PDT 24 Jul 17 05:25:57 PM PDT 24 113453031202 ps
T156 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3653600842 Jul 17 05:18:49 PM PDT 24 Jul 17 05:21:34 PM PDT 24 6125247683 ps
T151 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.261642055 Jul 17 05:19:37 PM PDT 24 Jul 17 05:37:36 PM PDT 24 73297201848 ps
T809 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1441209234 Jul 17 05:19:11 PM PDT 24 Jul 17 05:19:19 PM PDT 24 8678281 ps
T165 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2182672069 Jul 17 05:19:11 PM PDT 24 Jul 17 05:20:28 PM PDT 24 894938399 ps
T167 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.957434327 Jul 17 05:18:42 PM PDT 24 Jul 17 05:18:47 PM PDT 24 68666514 ps
T810 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1485702988 Jul 17 05:19:09 PM PDT 24 Jul 17 05:19:45 PM PDT 24 530462876 ps
T811 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.272019917 Jul 17 05:18:44 PM PDT 24 Jul 17 05:18:46 PM PDT 24 8123449 ps
T339 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1488531351 Jul 17 05:18:50 PM PDT 24 Jul 17 05:23:33 PM PDT 24 13184666358 ps
T812 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3646364461 Jul 17 05:24:24 PM PDT 24 Jul 17 05:24:32 PM PDT 24 37517602 ps
T813 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3353761060 Jul 17 05:18:51 PM PDT 24 Jul 17 05:19:01 PM PDT 24 86763072 ps
T154 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3610920664 Jul 17 05:18:33 PM PDT 24 Jul 17 05:20:06 PM PDT 24 3717797391 ps
T814 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3488136248 Jul 17 05:18:31 PM PDT 24 Jul 17 05:18:59 PM PDT 24 163081724 ps
T815 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1166745030 Jul 17 05:19:08 PM PDT 24 Jul 17 05:19:14 PM PDT 24 9300878 ps
T816 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.556223645 Jul 17 05:18:43 PM PDT 24 Jul 17 05:18:52 PM PDT 24 111075305 ps
T817 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3756534482 Jul 17 05:18:28 PM PDT 24 Jul 17 05:18:34 PM PDT 24 30445802 ps
T818 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2827264316 Jul 17 05:18:27 PM PDT 24 Jul 17 05:18:38 PM PDT 24 514306015 ps
T819 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3919958786 Jul 17 05:18:46 PM PDT 24 Jul 17 05:18:58 PM PDT 24 366456550 ps
T820 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4114550440 Jul 17 05:18:33 PM PDT 24 Jul 17 05:18:43 PM PDT 24 99258582 ps
T821 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.475856833 Jul 17 05:18:52 PM PDT 24 Jul 17 05:19:02 PM PDT 24 218119853 ps
T822 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3877314366 Jul 17 05:18:46 PM PDT 24 Jul 17 05:18:49 PM PDT 24 11286824 ps
T140 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.868437448 Jul 17 05:18:45 PM PDT 24 Jul 17 05:20:36 PM PDT 24 902779382 ps
T823 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1734359881 Jul 17 05:18:44 PM PDT 24 Jul 17 05:19:05 PM PDT 24 1441074201 ps
T824 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2021981249 Jul 17 05:19:07 PM PDT 24 Jul 17 05:19:23 PM PDT 24 1077045655 ps
T825 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2804535420 Jul 17 05:18:37 PM PDT 24 Jul 17 05:19:06 PM PDT 24 1164967342 ps
T157 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2913436044 Jul 17 05:18:51 PM PDT 24 Jul 17 05:24:14 PM PDT 24 70173873166 ps
T826 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4008192062 Jul 17 05:18:47 PM PDT 24 Jul 17 05:19:08 PM PDT 24 553283866 ps
T827 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.412878570 Jul 17 05:19:05 PM PDT 24 Jul 17 05:19:16 PM PDT 24 252056393 ps
T828 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4210048314 Jul 17 05:18:28 PM PDT 24 Jul 17 05:21:22 PM PDT 24 2854216898 ps
T829 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1477296354 Jul 17 05:18:27 PM PDT 24 Jul 17 05:18:37 PM PDT 24 781513510 ps

Test location /workspace/coverage/default/4.alert_handler_stress_all.121887876
Short name T13
Test name
Test status
Simulation time 76657988909 ps
CPU time 4247.87 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 07:18:48 PM PDT 24
Peak memory 305212 kb
Host smart-b69a711b-749c-419e-8585-032bb85cfd77
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121887876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.121887876
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.3575754876
Short name T26
Test name
Test status
Simulation time 144541314074 ps
CPU time 3917.1 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 07:13:52 PM PDT 24
Peak memory 330892 kb
Host smart-bf05bf76-4bdb-4867-8da3-51ba145e1eef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575754876 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.3575754876
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.600082040
Short name T10
Test name
Test status
Simulation time 1760035122 ps
CPU time 23.85 seconds
Started Jul 17 06:07:50 PM PDT 24
Finished Jul 17 06:08:19 PM PDT 24
Peak memory 273604 kb
Host smart-c7a44251-639b-4e84-9310-2db7933868c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=600082040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.600082040
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.455349876
Short name T120
Test name
Test status
Simulation time 14659418635 ps
CPU time 986.46 seconds
Started Jul 17 05:18:50 PM PDT 24
Finished Jul 17 05:35:18 PM PDT 24
Peak memory 273200 kb
Host smart-3977bf7f-45f4-4c12-b353-82be48d6716e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455349876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.455349876
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.529888101
Short name T158
Test name
Test status
Simulation time 157392420 ps
CPU time 22.59 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:19:11 PM PDT 24
Peak memory 240928 kb
Host smart-d2004593-fb31-427e-a6de-f004633cbbaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=529888101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.529888101
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3723684095
Short name T5
Test name
Test status
Simulation time 133015561323 ps
CPU time 2553.91 seconds
Started Jul 17 06:09:07 PM PDT 24
Finished Jul 17 06:51:43 PM PDT 24
Peak memory 289280 kb
Host smart-68c5ee66-f6d5-4eb9-8c2a-7daf5ae90683
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723684095 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3723684095
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2982099649
Short name T93
Test name
Test status
Simulation time 45874070727 ps
CPU time 3625.08 seconds
Started Jul 17 06:08:00 PM PDT 24
Finished Jul 17 07:08:27 PM PDT 24
Peak memory 305452 kb
Host smart-52773331-facd-42a8-9d5c-27dae6ddb3ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982099649 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2982099649
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3836014137
Short name T111
Test name
Test status
Simulation time 459404291401 ps
CPU time 2388.43 seconds
Started Jul 17 06:08:51 PM PDT 24
Finished Jul 17 06:48:44 PM PDT 24
Peak memory 283676 kb
Host smart-3a9fe229-8cea-4158-b336-3dffa6ca9ee1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836014137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3836014137
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2429263158
Short name T45
Test name
Test status
Simulation time 30330486574 ps
CPU time 1725.53 seconds
Started Jul 17 06:09:34 PM PDT 24
Finished Jul 17 06:38:21 PM PDT 24
Peak memory 287164 kb
Host smart-bfacd89e-cc1e-4a10-a769-b5d7c55cd9b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429263158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2429263158
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4099257696
Short name T132
Test name
Test status
Simulation time 15532215728 ps
CPU time 648.12 seconds
Started Jul 17 05:18:42 PM PDT 24
Finished Jul 17 05:29:31 PM PDT 24
Peak memory 265844 kb
Host smart-997111b3-631e-4729-b3a6-97556e279aa1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099257696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.4099257696
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.822415364
Short name T17
Test name
Test status
Simulation time 229013520642 ps
CPU time 3392.76 seconds
Started Jul 17 06:10:22 PM PDT 24
Finished Jul 17 07:06:57 PM PDT 24
Peak memory 289296 kb
Host smart-aba404b3-f956-4a45-bb33-b70d2c65e112
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822415364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.822415364
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1373240982
Short name T296
Test name
Test status
Simulation time 50050350332 ps
CPU time 482.76 seconds
Started Jul 17 06:07:47 PM PDT 24
Finished Jul 17 06:15:56 PM PDT 24
Peak memory 248760 kb
Host smart-00355476-d8bb-427b-827a-4bcc262bb5da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373240982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1373240982
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3120550926
Short name T146
Test name
Test status
Simulation time 5283872257 ps
CPU time 350.64 seconds
Started Jul 17 05:18:50 PM PDT 24
Finished Jul 17 05:24:43 PM PDT 24
Peak memory 265872 kb
Host smart-1a85ad92-e50c-441e-b5db-6d380fcabc6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3120550926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3120550926
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1783892486
Short name T56
Test name
Test status
Simulation time 47425517295 ps
CPU time 2702.87 seconds
Started Jul 17 06:08:51 PM PDT 24
Finished Jul 17 06:53:59 PM PDT 24
Peak memory 288948 kb
Host smart-2a1edc99-7cba-4c10-83d4-3b42fec0ee00
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783892486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1783892486
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1032679173
Short name T142
Test name
Test status
Simulation time 17560508735 ps
CPU time 302.82 seconds
Started Jul 17 05:18:51 PM PDT 24
Finished Jul 17 05:23:55 PM PDT 24
Peak memory 265800 kb
Host smart-fe1146ab-d9f8-4407-8bb6-d3e40dfc2aac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1032679173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1032679173
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.743969793
Short name T37
Test name
Test status
Simulation time 148181425532 ps
CPU time 2512.68 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:50:28 PM PDT 24
Peak memory 283620 kb
Host smart-8050e8d6-f1ce-4793-a73c-62b9c4d06a4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743969793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.743969793
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4022757666
Short name T335
Test name
Test status
Simulation time 12388585 ps
CPU time 1.33 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:19:18 PM PDT 24
Peak memory 237128 kb
Host smart-bbd79ef4-7e19-41c7-90bf-4a606325d26f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4022757666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4022757666
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.788554547
Short name T127
Test name
Test status
Simulation time 19041723231 ps
CPU time 660.61 seconds
Started Jul 17 05:18:34 PM PDT 24
Finished Jul 17 05:29:37 PM PDT 24
Peak memory 273408 kb
Host smart-1e61abc5-c31a-4875-9e54-d22be12fc481
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788554547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.788554547
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3887654927
Short name T65
Test name
Test status
Simulation time 8359633421 ps
CPU time 352.73 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:14:35 PM PDT 24
Peak memory 248592 kb
Host smart-8596d5c4-791f-4f06-88f2-28ffbee6d26f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887654927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3887654927
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1215533526
Short name T133
Test name
Test status
Simulation time 4294348700 ps
CPU time 603.62 seconds
Started Jul 17 05:18:25 PM PDT 24
Finished Jul 17 05:28:29 PM PDT 24
Peak memory 265812 kb
Host smart-4848299e-30bd-4e53-91ad-afaaf16e9ae1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215533526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1215533526
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2164219253
Short name T323
Test name
Test status
Simulation time 37770066740 ps
CPU time 2267.24 seconds
Started Jul 17 06:09:32 PM PDT 24
Finished Jul 17 06:47:20 PM PDT 24
Peak memory 289792 kb
Host smart-b5dc8e75-5b15-4935-b4b5-e472ed203775
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164219253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2164219253
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2263210277
Short name T18
Test name
Test status
Simulation time 42369552007 ps
CPU time 2332.67 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:47:35 PM PDT 24
Peak memory 285556 kb
Host smart-7cefc26d-3b19-48ab-a3cb-157698d21964
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263210277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2263210277
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1196662593
Short name T139
Test name
Test status
Simulation time 4563101911 ps
CPU time 320.43 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:24:35 PM PDT 24
Peak memory 266424 kb
Host smart-cd329584-a906-4cda-a7f0-a3aca327fe93
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1196662593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1196662593
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.389074019
Short name T270
Test name
Test status
Simulation time 63677838889 ps
CPU time 552.25 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:17:44 PM PDT 24
Peak memory 255192 kb
Host smart-d3fd11f6-82d1-4994-892e-0e4a76827e41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389074019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.389074019
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.500811880
Short name T308
Test name
Test status
Simulation time 13943563855 ps
CPU time 1392.76 seconds
Started Jul 17 06:07:47 PM PDT 24
Finished Jul 17 06:31:06 PM PDT 24
Peak memory 288380 kb
Host smart-24ddab5d-3520-44de-9763-2189267bfd1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500811880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.500811880
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.573158593
Short name T138
Test name
Test status
Simulation time 5332988622 ps
CPU time 370.54 seconds
Started Jul 17 05:19:06 PM PDT 24
Finished Jul 17 05:25:18 PM PDT 24
Peak memory 274088 kb
Host smart-85f3d3ca-a6a2-4519-886d-0d40bbcc575a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=573158593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.573158593
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1549794918
Short name T82
Test name
Test status
Simulation time 67534994049 ps
CPU time 880.83 seconds
Started Jul 17 06:09:38 PM PDT 24
Finished Jul 17 06:24:19 PM PDT 24
Peak memory 270300 kb
Host smart-c228bf02-ffdd-4021-9cdf-b2df5b88e136
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549794918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1549794918
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2892224358
Short name T304
Test name
Test status
Simulation time 56945460433 ps
CPU time 627.04 seconds
Started Jul 17 06:09:19 PM PDT 24
Finished Jul 17 06:19:48 PM PDT 24
Peak memory 248780 kb
Host smart-e9a3dcca-8eb2-437c-8de8-e110032cc835
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892224358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2892224358
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2387647148
Short name T121
Test name
Test status
Simulation time 123077480441 ps
CPU time 984.97 seconds
Started Jul 17 05:18:16 PM PDT 24
Finished Jul 17 05:34:43 PM PDT 24
Peak memory 265892 kb
Host smart-7cffb2d4-5a21-427b-8aba-4dfd085648fb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387647148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2387647148
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2460063854
Short name T181
Test name
Test status
Simulation time 116342526441 ps
CPU time 3531.83 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 07:07:30 PM PDT 24
Peak memory 306312 kb
Host smart-61952ac5-49a4-476b-913f-03407b019bdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460063854 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2460063854
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.602434083
Short name T573
Test name
Test status
Simulation time 53664260981 ps
CPU time 2966.93 seconds
Started Jul 17 06:08:39 PM PDT 24
Finished Jul 17 06:58:16 PM PDT 24
Peak memory 286372 kb
Host smart-0e12c9b3-ddac-467e-8f56-45ab26f52df9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602434083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.602434083
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.577944693
Short name T242
Test name
Test status
Simulation time 708803503 ps
CPU time 49.99 seconds
Started Jul 17 06:09:11 PM PDT 24
Finished Jul 17 06:10:02 PM PDT 24
Peak memory 256844 kb
Host smart-ae6e4f8f-22e6-466f-8be6-64abadcd64ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57794
4693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.577944693
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1513026402
Short name T122
Test name
Test status
Simulation time 17722010915 ps
CPU time 338.29 seconds
Started Jul 17 05:18:32 PM PDT 24
Finished Jul 17 05:24:13 PM PDT 24
Peak memory 265840 kb
Host smart-0e219693-4872-4187-99d1-570166960a5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1513026402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1513026402
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1982541267
Short name T648
Test name
Test status
Simulation time 52239615479 ps
CPU time 491.22 seconds
Started Jul 17 06:09:02 PM PDT 24
Finished Jul 17 06:17:15 PM PDT 24
Peak memory 256676 kb
Host smart-d7fb21cc-2ad3-4db7-ada2-a82b91a3810f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982541267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1982541267
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.261642055
Short name T151
Test name
Test status
Simulation time 73297201848 ps
CPU time 1077.71 seconds
Started Jul 17 05:19:37 PM PDT 24
Finished Jul 17 05:37:36 PM PDT 24
Peak memory 265804 kb
Host smart-ab14c961-67d1-4761-8d0a-108ca60a30ff
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261642055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.261642055
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.297896606
Short name T86
Test name
Test status
Simulation time 106870857361 ps
CPU time 4964.77 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 07:31:27 PM PDT 24
Peak memory 318936 kb
Host smart-8285f1e9-e648-4ba7-9ff4-1d8c506807c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297896606 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.297896606
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3081734204
Short name T85
Test name
Test status
Simulation time 71780838789 ps
CPU time 1852.66 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:39:23 PM PDT 24
Peak memory 289828 kb
Host smart-1948a60b-099e-4c20-b731-347e333c317a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081734204 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3081734204
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3464552493
Short name T330
Test name
Test status
Simulation time 156981005717 ps
CPU time 2514.63 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 06:49:54 PM PDT 24
Peak memory 286380 kb
Host smart-6a7f8d04-9348-4cfb-8d29-916187dda21f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464552493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3464552493
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1545537870
Short name T278
Test name
Test status
Simulation time 11832453079 ps
CPU time 467.99 seconds
Started Jul 17 06:08:23 PM PDT 24
Finished Jul 17 06:16:12 PM PDT 24
Peak memory 248704 kb
Host smart-7378dfb1-b97d-4e17-931f-e02f380b0a18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545537870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1545537870
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3294365427
Short name T7
Test name
Test status
Simulation time 23404607540 ps
CPU time 268.69 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:13:13 PM PDT 24
Peak memory 247672 kb
Host smart-2d71ba45-8407-4e7c-b461-ffdd424271b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294365427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3294365427
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2709372083
Short name T159
Test name
Test status
Simulation time 2420130745 ps
CPU time 89.73 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:20:18 PM PDT 24
Peak memory 238100 kb
Host smart-d72da0c7-5254-478e-aabc-f5bf7cce7b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2709372083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2709372083
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2687524911
Short name T236
Test name
Test status
Simulation time 11866925 ps
CPU time 1.6 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:14 PM PDT 24
Peak memory 238036 kb
Host smart-162e1e28-a4e5-4ece-b54a-bcf8c02127b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2687524911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2687524911
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3047334170
Short name T281
Test name
Test status
Simulation time 21429250495 ps
CPU time 1304.1 seconds
Started Jul 17 06:08:10 PM PDT 24
Finished Jul 17 06:29:55 PM PDT 24
Peak memory 273300 kb
Host smart-320a2dfa-af4a-4ab9-a0f6-dd9a57e19d30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047334170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3047334170
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2687070740
Short name T243
Test name
Test status
Simulation time 82701088445 ps
CPU time 2622.1 seconds
Started Jul 17 06:08:49 PM PDT 24
Finished Jul 17 06:52:37 PM PDT 24
Peak memory 288844 kb
Host smart-45e5a74c-0ea7-419e-b6c1-0d001f3ae4da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687070740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2687070740
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.697718602
Short name T84
Test name
Test status
Simulation time 624280741 ps
CPU time 19.48 seconds
Started Jul 17 06:08:25 PM PDT 24
Finished Jul 17 06:08:46 PM PDT 24
Peak memory 248084 kb
Host smart-f98484b0-d785-4445-b27c-569f59f5dcd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69771
8602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.697718602
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2033513423
Short name T170
Test name
Test status
Simulation time 202967269 ps
CPU time 4.21 seconds
Started Jul 17 05:20:08 PM PDT 24
Finished Jul 17 05:20:14 PM PDT 24
Peak memory 238496 kb
Host smart-5d440347-d985-4286-9878-a7daf2641ebf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2033513423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2033513423
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2379511431
Short name T204
Test name
Test status
Simulation time 35523186 ps
CPU time 3.43 seconds
Started Jul 17 06:07:46 PM PDT 24
Finished Jul 17 06:07:55 PM PDT 24
Peak memory 248920 kb
Host smart-7091590d-6b3d-4e6c-bf2d-7c0aa77a05fa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2379511431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2379511431
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3961690782
Short name T197
Test name
Test status
Simulation time 51826106 ps
CPU time 3.71 seconds
Started Jul 17 06:07:46 PM PDT 24
Finished Jul 17 06:07:56 PM PDT 24
Peak memory 248872 kb
Host smart-972178ad-cb83-4b23-9d0e-376a2c2e9e6a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3961690782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3961690782
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.529667191
Short name T21
Test name
Test status
Simulation time 21130508 ps
CPU time 3.24 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:36 PM PDT 24
Peak memory 248852 kb
Host smart-de732327-7299-4cb7-987f-23838d0b5ef4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=529667191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.529667191
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.275999047
Short name T110
Test name
Test status
Simulation time 130082253 ps
CPU time 3.42 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:08:33 PM PDT 24
Peak memory 248972 kb
Host smart-7e3eda10-57ec-41d1-ad06-6c3751efb22f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=275999047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.275999047
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2790534160
Short name T260
Test name
Test status
Simulation time 1176467387 ps
CPU time 27.74 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:09:10 PM PDT 24
Peak memory 248028 kb
Host smart-97e8b232-96c5-489d-b77d-3baa2ffb01da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27905
34160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2790534160
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2042478802
Short name T302
Test name
Test status
Simulation time 11255939603 ps
CPU time 479.28 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:16:45 PM PDT 24
Peak memory 248820 kb
Host smart-bdc15d29-3f5a-4b61-af6a-3fa747c140ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042478802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2042478802
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3123156221
Short name T274
Test name
Test status
Simulation time 9063004326 ps
CPU time 786.64 seconds
Started Jul 17 06:08:47 PM PDT 24
Finished Jul 17 06:22:01 PM PDT 24
Peak memory 273404 kb
Host smart-d53fa2df-b4fc-46b9-b3b0-c50fc22d1407
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123156221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3123156221
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3325115215
Short name T320
Test name
Test status
Simulation time 68175514084 ps
CPU time 2199.39 seconds
Started Jul 17 06:08:45 PM PDT 24
Finished Jul 17 06:45:32 PM PDT 24
Peak memory 283540 kb
Host smart-08acf69a-13a9-4588-8ed7-aebcc3e34f5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325115215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3325115215
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1960923842
Short name T256
Test name
Test status
Simulation time 19348712704 ps
CPU time 1208.31 seconds
Started Jul 17 06:09:02 PM PDT 24
Finished Jul 17 06:29:11 PM PDT 24
Peak memory 265452 kb
Host smart-73cb1cc7-7c9e-4e1c-8421-c3c7191e2d54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960923842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1960923842
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.4232111131
Short name T298
Test name
Test status
Simulation time 3624034079 ps
CPU time 137.75 seconds
Started Jul 17 06:07:59 PM PDT 24
Finished Jul 17 06:10:18 PM PDT 24
Peak memory 248200 kb
Host smart-360482b4-1ba0-4ed7-aa44-a602856b45f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232111131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.4232111131
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.14357188
Short name T129
Test name
Test status
Simulation time 20818459294 ps
CPU time 326.78 seconds
Started Jul 17 05:19:07 PM PDT 24
Finished Jul 17 05:24:36 PM PDT 24
Peak memory 273216 kb
Host smart-a9b2b970-62b0-48c1-81d3-510664f091eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=14357188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_error
s.14357188
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1695250247
Short name T131
Test name
Test status
Simulation time 16189612040 ps
CPU time 153.72 seconds
Started Jul 17 05:18:28 PM PDT 24
Finished Jul 17 05:21:03 PM PDT 24
Peak memory 265916 kb
Host smart-8fe4da76-8183-4f6f-ae91-93c2e9d19beb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1695250247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1695250247
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2182672069
Short name T165
Test name
Test status
Simulation time 894938399 ps
CPU time 70.51 seconds
Started Jul 17 05:19:11 PM PDT 24
Finished Jul 17 05:20:28 PM PDT 24
Peak memory 240980 kb
Host smart-1c85d4fa-6404-4147-9b41-4051fbb1eb08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2182672069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2182672069
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2218628195
Short name T249
Test name
Test status
Simulation time 498008655 ps
CPU time 32.1 seconds
Started Jul 17 06:07:49 PM PDT 24
Finished Jul 17 06:08:27 PM PDT 24
Peak memory 248716 kb
Host smart-57eabe7e-260d-4227-af65-3fe51040cb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22186
28195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2218628195
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.4161557979
Short name T262
Test name
Test status
Simulation time 108613706597 ps
CPU time 1553.95 seconds
Started Jul 17 06:07:44 PM PDT 24
Finished Jul 17 06:33:44 PM PDT 24
Peak memory 289712 kb
Host smart-ab6424f8-b11e-4381-ba21-5cc5d80b6f8b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161557979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.4161557979
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1976203332
Short name T241
Test name
Test status
Simulation time 793205228 ps
CPU time 51.58 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:09:29 PM PDT 24
Peak memory 256884 kb
Host smart-bd81830d-26ec-41cf-b054-55ad1a0940ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19762
03332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1976203332
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3524111069
Short name T183
Test name
Test status
Simulation time 152945999538 ps
CPU time 6668.56 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 07:59:47 PM PDT 24
Peak memory 370436 kb
Host smart-2ff52a0f-0d03-4c27-aeab-85dd77ca6f57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524111069 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3524111069
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.823139753
Short name T254
Test name
Test status
Simulation time 109016120516 ps
CPU time 559.29 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:18:04 PM PDT 24
Peak memory 273072 kb
Host smart-b8214ab6-5ab2-4e38-9d7c-121bea01f17b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823139753 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.823139753
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.710638684
Short name T55
Test name
Test status
Simulation time 128797027128 ps
CPU time 1542.95 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:34:21 PM PDT 24
Peak memory 289336 kb
Host smart-a4c0303c-e349-4293-aae2-46f495a185b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710638684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.710638684
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1294914709
Short name T98
Test name
Test status
Simulation time 33950761603 ps
CPU time 2317.29 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:47:10 PM PDT 24
Peak memory 289472 kb
Host smart-0aed6fdb-7cfa-476a-822a-27714ba943d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294914709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1294914709
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1666448946
Short name T435
Test name
Test status
Simulation time 398607742 ps
CPU time 8.11 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:08:48 PM PDT 24
Peak memory 248640 kb
Host smart-240ddd5e-c275-4d01-aa4a-49d9d96de1b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16664
48946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1666448946
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1102862127
Short name T250
Test name
Test status
Simulation time 21782871635 ps
CPU time 1759.97 seconds
Started Jul 17 06:07:47 PM PDT 24
Finished Jul 17 06:37:15 PM PDT 24
Peak memory 305632 kb
Host smart-9a221e5c-0ee2-472b-b83a-6657b10c929b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102862127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1102862127
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1584269829
Short name T184
Test name
Test status
Simulation time 176405277110 ps
CPU time 5647.08 seconds
Started Jul 17 06:08:46 PM PDT 24
Finished Jul 17 07:43:01 PM PDT 24
Peak memory 320812 kb
Host smart-2304f2e6-ccb5-4377-9b32-aa6d7846876a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584269829 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1584269829
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1401130192
Short name T67
Test name
Test status
Simulation time 11069221188 ps
CPU time 1005.9 seconds
Started Jul 17 06:09:08 PM PDT 24
Finished Jul 17 06:25:55 PM PDT 24
Peak memory 273396 kb
Host smart-8add5050-63b2-40b3-912a-055084e69632
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401130192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1401130192
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1621567693
Short name T81
Test name
Test status
Simulation time 76920521866 ps
CPU time 1101.01 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:27:12 PM PDT 24
Peak memory 289884 kb
Host smart-a2a7a2f6-922d-4a87-a9dc-04c11ef06636
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621567693 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1621567693
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1603729748
Short name T280
Test name
Test status
Simulation time 10921924103 ps
CPU time 584.75 seconds
Started Jul 17 06:10:09 PM PDT 24
Finished Jul 17 06:19:55 PM PDT 24
Peak memory 265156 kb
Host smart-f1c1cf52-f7c1-4b39-844f-bd7aa795208a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603729748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1603729748
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3196400347
Short name T286
Test name
Test status
Simulation time 20841782189 ps
CPU time 1026.19 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:25:36 PM PDT 24
Peak memory 284272 kb
Host smart-aebedd99-c08b-492e-8a62-3e81f2724b85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196400347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3196400347
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.957434327
Short name T167
Test name
Test status
Simulation time 68666514 ps
CPU time 4.94 seconds
Started Jul 17 05:18:42 PM PDT 24
Finished Jul 17 05:18:47 PM PDT 24
Peak memory 237984 kb
Host smart-f9aa422d-0bd3-4186-a1bf-04583dcd423b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=957434327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.957434327
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.4156594562
Short name T123
Test name
Test status
Simulation time 4035689479 ps
CPU time 99.66 seconds
Started Jul 17 05:18:25 PM PDT 24
Finished Jul 17 05:20:06 PM PDT 24
Peak memory 265928 kb
Host smart-387b8ff1-8f66-4ea2-bbfd-d2f9b635c6b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4156594562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.4156594562
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3610920664
Short name T154
Test name
Test status
Simulation time 3717797391 ps
CPU time 90.4 seconds
Started Jul 17 05:18:33 PM PDT 24
Finished Jul 17 05:20:06 PM PDT 24
Peak memory 265852 kb
Host smart-aab93c94-dd21-450f-bdb3-6c41c3894328
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3610920664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3610920664
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.189899896
Short name T164
Test name
Test status
Simulation time 943467333 ps
CPU time 63.25 seconds
Started Jul 17 05:18:29 PM PDT 24
Finished Jul 17 05:19:33 PM PDT 24
Peak memory 240936 kb
Host smart-0b4d3f85-389e-45ac-bc8d-a2319c7bb394
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=189899896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.189899896
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3319027367
Short name T171
Test name
Test status
Simulation time 458730339 ps
CPU time 33.95 seconds
Started Jul 17 05:18:35 PM PDT 24
Finished Jul 17 05:19:11 PM PDT 24
Peak memory 246548 kb
Host smart-b741ffba-2a51-4960-88a2-8f5c58e5fe68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3319027367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3319027367
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4193596220
Short name T166
Test name
Test status
Simulation time 49766896 ps
CPU time 3.36 seconds
Started Jul 17 05:18:43 PM PDT 24
Finished Jul 17 05:18:47 PM PDT 24
Peak memory 237020 kb
Host smart-01a50e7f-c28a-4695-96fc-0ca30ad10d27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4193596220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.4193596220
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2076196036
Short name T179
Test name
Test status
Simulation time 1828118636 ps
CPU time 33.49 seconds
Started Jul 17 05:18:45 PM PDT 24
Finished Jul 17 05:19:20 PM PDT 24
Peak memory 238000 kb
Host smart-21d0992d-d0de-483a-933a-4f27a824d920
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2076196036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2076196036
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3672059792
Short name T153
Test name
Test status
Simulation time 2151782278 ps
CPU time 142.33 seconds
Started Jul 17 05:18:27 PM PDT 24
Finished Jul 17 05:20:50 PM PDT 24
Peak memory 265976 kb
Host smart-cf85bf5f-d121-4e89-b007-53e608b50383
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3672059792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3672059792
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.329586998
Short name T173
Test name
Test status
Simulation time 23084215 ps
CPU time 2.49 seconds
Started Jul 17 05:18:27 PM PDT 24
Finished Jul 17 05:18:31 PM PDT 24
Peak memory 238520 kb
Host smart-1e35a362-452e-4447-8a96-da1c83a0ada4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=329586998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.329586998
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3644404941
Short name T160
Test name
Test status
Simulation time 52904373 ps
CPU time 2.59 seconds
Started Jul 17 05:18:29 PM PDT 24
Finished Jul 17 05:18:33 PM PDT 24
Peak memory 237116 kb
Host smart-23358368-126f-4a2f-9cde-f67db930f077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3644404941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3644404941
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1263337716
Short name T174
Test name
Test status
Simulation time 106540946 ps
CPU time 6.09 seconds
Started Jul 17 05:18:31 PM PDT 24
Finished Jul 17 05:18:38 PM PDT 24
Peak memory 237992 kb
Host smart-d7f81e7d-3c77-4fc5-8c75-943c056bea5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1263337716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1263337716
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3923045265
Short name T168
Test name
Test status
Simulation time 62044614 ps
CPU time 4.16 seconds
Started Jul 17 05:18:29 PM PDT 24
Finished Jul 17 05:18:34 PM PDT 24
Peak memory 238080 kb
Host smart-53416233-b0f0-42da-b371-84feb55df84d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3923045265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3923045265
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2080022873
Short name T172
Test name
Test status
Simulation time 4048657032 ps
CPU time 80.07 seconds
Started Jul 17 05:18:33 PM PDT 24
Finished Jul 17 05:19:56 PM PDT 24
Peak memory 239120 kb
Host smart-045e1abf-54b3-46ed-8ca1-1cfcdcf5cb03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2080022873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2080022873
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.225599627
Short name T169
Test name
Test status
Simulation time 464570437 ps
CPU time 35.66 seconds
Started Jul 17 05:18:10 PM PDT 24
Finished Jul 17 05:18:49 PM PDT 24
Peak memory 238212 kb
Host smart-429364cd-a698-4c80-a606-136501866684
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=225599627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.225599627
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2202153971
Short name T178
Test name
Test status
Simulation time 204074434 ps
CPU time 18.59 seconds
Started Jul 17 05:19:06 PM PDT 24
Finished Jul 17 05:19:26 PM PDT 24
Peak memory 249140 kb
Host smart-a99378fd-fb44-4438-9f2f-e4e5f46df4d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2202153971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2202153971
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2527288108
Short name T763
Test name
Test status
Simulation time 1108908227 ps
CPU time 72.18 seconds
Started Jul 17 05:18:34 PM PDT 24
Finished Jul 17 05:19:48 PM PDT 24
Peak memory 237796 kb
Host smart-9c0bc98e-1e42-4003-86e9-df641b488498
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2527288108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2527288108
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3477333148
Short name T769
Test name
Test status
Simulation time 7102085039 ps
CPU time 202.93 seconds
Started Jul 17 05:18:33 PM PDT 24
Finished Jul 17 05:21:59 PM PDT 24
Peak memory 241000 kb
Host smart-491d9425-aaf1-4aa2-bf10-eb09fdae8d8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3477333148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3477333148
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.4005003608
Short name T800
Test name
Test status
Simulation time 102427885 ps
CPU time 9.28 seconds
Started Jul 17 05:18:31 PM PDT 24
Finished Jul 17 05:18:41 PM PDT 24
Peak memory 249648 kb
Host smart-2b1d9a27-6b5c-4ed2-9814-34ce99840ede
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4005003608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.4005003608
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2893913717
Short name T789
Test name
Test status
Simulation time 100449764 ps
CPU time 9.27 seconds
Started Jul 17 05:18:33 PM PDT 24
Finished Jul 17 05:18:44 PM PDT 24
Peak memory 241160 kb
Host smart-8ff62fc5-d882-4dba-912d-1831785e0ca6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893913717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2893913717
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.974591295
Short name T764
Test name
Test status
Simulation time 345871584 ps
CPU time 7.49 seconds
Started Jul 17 05:18:32 PM PDT 24
Finished Jul 17 05:18:42 PM PDT 24
Peak memory 241000 kb
Host smart-ec2bdb0a-e108-4082-a57a-7e4e2c5a1b12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=974591295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.974591295
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2007745754
Short name T794
Test name
Test status
Simulation time 18189192 ps
CPU time 1.56 seconds
Started Jul 17 05:18:27 PM PDT 24
Finished Jul 17 05:18:30 PM PDT 24
Peak memory 238080 kb
Host smart-a6f76497-37fa-4d9a-838e-dd0f65974672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2007745754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2007745754
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1710464803
Short name T726
Test name
Test status
Simulation time 595608173 ps
CPU time 37.8 seconds
Started Jul 17 05:18:28 PM PDT 24
Finished Jul 17 05:19:07 PM PDT 24
Peak memory 246224 kb
Host smart-f011e7a6-5b9e-4bff-88c0-eec82465bf2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1710464803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1710464803
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3939384754
Short name T141
Test name
Test status
Simulation time 3561349023 ps
CPU time 132.74 seconds
Started Jul 17 05:18:15 PM PDT 24
Finished Jul 17 05:20:30 PM PDT 24
Peak memory 265772 kb
Host smart-73d2f6de-2450-4c15-b809-43d0c1048e33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3939384754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3939384754
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3129337646
Short name T798
Test name
Test status
Simulation time 641419151 ps
CPU time 12.68 seconds
Started Jul 17 05:18:11 PM PDT 24
Finished Jul 17 05:18:27 PM PDT 24
Peak memory 249228 kb
Host smart-777dd5de-96a2-4a9b-acde-7b4a17f50dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3129337646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3129337646
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3744959853
Short name T801
Test name
Test status
Simulation time 6174459884 ps
CPU time 124.91 seconds
Started Jul 17 05:18:31 PM PDT 24
Finished Jul 17 05:20:38 PM PDT 24
Peak memory 238164 kb
Host smart-c03cfb6e-1252-4c1a-bedc-3adc0fbf7248
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3744959853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3744959853
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2657955509
Short name T732
Test name
Test status
Simulation time 17086181919 ps
CPU time 241.89 seconds
Started Jul 17 05:18:28 PM PDT 24
Finished Jul 17 05:22:31 PM PDT 24
Peak memory 238044 kb
Host smart-4ff5fd75-705f-4161-ba0a-7f0c79379a09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2657955509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2657955509
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1477296354
Short name T829
Test name
Test status
Simulation time 781513510 ps
CPU time 8.58 seconds
Started Jul 17 05:18:27 PM PDT 24
Finished Jul 17 05:18:37 PM PDT 24
Peak memory 249192 kb
Host smart-0428f102-9ffb-4f22-baf6-8324901da3c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1477296354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1477296354
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3646364461
Short name T812
Test name
Test status
Simulation time 37517602 ps
CPU time 6.48 seconds
Started Jul 17 05:24:24 PM PDT 24
Finished Jul 17 05:24:32 PM PDT 24
Peak memory 249284 kb
Host smart-51742a82-9949-434e-b626-caf844e83770
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646364461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3646364461
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1997645728
Short name T750
Test name
Test status
Simulation time 1077172977 ps
CPU time 4.83 seconds
Started Jul 17 05:18:34 PM PDT 24
Finished Jul 17 05:18:41 PM PDT 24
Peak memory 240032 kb
Host smart-e0d520bf-0224-44c7-ad58-e2fed6468840
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1997645728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1997645728
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2378319570
Short name T790
Test name
Test status
Simulation time 8711538 ps
CPU time 1.53 seconds
Started Jul 17 05:18:30 PM PDT 24
Finished Jul 17 05:18:32 PM PDT 24
Peak memory 238008 kb
Host smart-8d447d50-f3bd-4a55-9739-361b47deed38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2378319570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2378319570
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.131965537
Short name T742
Test name
Test status
Simulation time 2793621514 ps
CPU time 54.47 seconds
Started Jul 17 05:18:38 PM PDT 24
Finished Jul 17 05:19:34 PM PDT 24
Peak memory 246104 kb
Host smart-183e50de-3603-442a-af4a-4fd3c384ae23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=131965537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.131965537
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.327786587
Short name T147
Test name
Test status
Simulation time 51487265268 ps
CPU time 518.22 seconds
Started Jul 17 05:18:26 PM PDT 24
Finished Jul 17 05:27:05 PM PDT 24
Peak memory 265836 kb
Host smart-4f9ae0d0-e9d6-4a00-87e2-7f0ce84ce8de
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327786587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.327786587
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3344390440
Short name T719
Test name
Test status
Simulation time 82275410 ps
CPU time 9.94 seconds
Started Jul 17 05:18:32 PM PDT 24
Finished Jul 17 05:18:44 PM PDT 24
Peak memory 248872 kb
Host smart-4b620cd7-597d-41a7-865d-061f612656d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3344390440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3344390440
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2135396554
Short name T191
Test name
Test status
Simulation time 250930539 ps
CPU time 9.96 seconds
Started Jul 17 05:18:49 PM PDT 24
Finished Jul 17 05:19:00 PM PDT 24
Peak memory 256780 kb
Host smart-5222830d-c690-49be-a33d-8abb9b9ee711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135396554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2135396554
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3507485027
Short name T774
Test name
Test status
Simulation time 66753898 ps
CPU time 3.81 seconds
Started Jul 17 05:18:52 PM PDT 24
Finished Jul 17 05:18:57 PM PDT 24
Peak memory 237088 kb
Host smart-5784eab6-1d3a-4f30-a46e-3ce8ab502ef3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3507485027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3507485027
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3877314366
Short name T822
Test name
Test status
Simulation time 11286824 ps
CPU time 1.64 seconds
Started Jul 17 05:18:46 PM PDT 24
Finished Jul 17 05:18:49 PM PDT 24
Peak memory 236116 kb
Host smart-ec9d3123-4d99-4e46-86a1-27ca18b18c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3877314366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3877314366
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3025188068
Short name T187
Test name
Test status
Simulation time 685570398 ps
CPU time 22.07 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:19:10 PM PDT 24
Peak memory 246232 kb
Host smart-99ee9e63-5e58-46e1-b840-71ded048f091
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3025188068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3025188068
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1847718557
Short name T126
Test name
Test status
Simulation time 1724464328 ps
CPU time 126.21 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:20:55 PM PDT 24
Peak memory 257656 kb
Host smart-6d05e3d0-eae8-4230-9e96-79d1b4236927
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1847718557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1847718557
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1012171989
Short name T145
Test name
Test status
Simulation time 19571226356 ps
CPU time 1017.81 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:35:46 PM PDT 24
Peak memory 265840 kb
Host smart-277af503-4a0e-4c49-892a-3e52a42d4d34
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012171989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1012171989
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3060245140
Short name T782
Test name
Test status
Simulation time 198611247 ps
CPU time 9.48 seconds
Started Jul 17 05:18:45 PM PDT 24
Finished Jul 17 05:18:56 PM PDT 24
Peak memory 248292 kb
Host smart-78e34bf9-17ea-46a7-b712-1d1dacfff08e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3060245140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3060245140
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3688911641
Short name T791
Test name
Test status
Simulation time 67000431 ps
CPU time 5.29 seconds
Started Jul 17 05:18:48 PM PDT 24
Finished Jul 17 05:18:55 PM PDT 24
Peak memory 240972 kb
Host smart-f72b8545-f98f-4faa-836c-35ece58cfc18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688911641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3688911641
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.849157590
Short name T776
Test name
Test status
Simulation time 22558197 ps
CPU time 3.42 seconds
Started Jul 17 05:18:44 PM PDT 24
Finished Jul 17 05:18:48 PM PDT 24
Peak memory 240944 kb
Host smart-e1d6e040-def5-44b0-8eb0-2b0641fe65a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=849157590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.849157590
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.272019917
Short name T811
Test name
Test status
Simulation time 8123449 ps
CPU time 1.34 seconds
Started Jul 17 05:18:44 PM PDT 24
Finished Jul 17 05:18:46 PM PDT 24
Peak memory 238012 kb
Host smart-10f36dd9-16dd-49e5-b4eb-64e09ea126f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=272019917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.272019917
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3768798530
Short name T753
Test name
Test status
Simulation time 11264224292 ps
CPU time 54.78 seconds
Started Jul 17 05:18:42 PM PDT 24
Finished Jul 17 05:19:38 PM PDT 24
Peak memory 249260 kb
Host smart-8951442e-4bf5-49b4-be22-4376562c3460
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3768798530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3768798530
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2899938537
Short name T128
Test name
Test status
Simulation time 3113129223 ps
CPU time 170.85 seconds
Started Jul 17 05:18:50 PM PDT 24
Finished Jul 17 05:21:43 PM PDT 24
Peak memory 265864 kb
Host smart-14f42c9f-2118-49bc-95e7-0841eca955b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2899938537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2899938537
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2556407142
Short name T806
Test name
Test status
Simulation time 213038929 ps
CPU time 7.82 seconds
Started Jul 17 05:18:43 PM PDT 24
Finished Jul 17 05:18:51 PM PDT 24
Peak memory 250284 kb
Host smart-26a9aacb-ba50-4dd5-a960-620b357476e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2556407142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2556407142
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3353761060
Short name T813
Test name
Test status
Simulation time 86763072 ps
CPU time 7.85 seconds
Started Jul 17 05:18:51 PM PDT 24
Finished Jul 17 05:19:01 PM PDT 24
Peak memory 241572 kb
Host smart-28a9bb94-35de-4276-b63b-cf6f17848b7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353761060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3353761060
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.556223645
Short name T816
Test name
Test status
Simulation time 111075305 ps
CPU time 8.64 seconds
Started Jul 17 05:18:43 PM PDT 24
Finished Jul 17 05:18:52 PM PDT 24
Peak memory 240948 kb
Host smart-0297fa77-aab3-4091-8785-9b69b6f3bd39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=556223645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.556223645
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2818070205
Short name T759
Test name
Test status
Simulation time 11106250 ps
CPU time 1.66 seconds
Started Jul 17 05:18:49 PM PDT 24
Finished Jul 17 05:18:53 PM PDT 24
Peak memory 238088 kb
Host smart-018635c3-045b-49bd-93f9-999a3ec462aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2818070205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2818070205
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.687528543
Short name T772
Test name
Test status
Simulation time 2724210589 ps
CPU time 48.36 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:19:37 PM PDT 24
Peak memory 246272 kb
Host smart-0facec1a-4326-4c36-816f-6b7a1f7c8e60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=687528543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.687528543
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1236834618
Short name T148
Test name
Test status
Simulation time 3079270889 ps
CPU time 183.28 seconds
Started Jul 17 05:18:49 PM PDT 24
Finished Jul 17 05:21:54 PM PDT 24
Peak memory 265900 kb
Host smart-8c292915-b2d0-44b2-8365-a780509c6fb9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1236834618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1236834618
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.68057080
Short name T152
Test name
Test status
Simulation time 9056824456 ps
CPU time 341.86 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:24:30 PM PDT 24
Peak memory 265916 kb
Host smart-114c5eda-0e1f-4880-869f-711d243a4dda
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68057080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.68057080
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.445179500
Short name T718
Test name
Test status
Simulation time 121307207 ps
CPU time 9.37 seconds
Started Jul 17 05:18:44 PM PDT 24
Finished Jul 17 05:18:55 PM PDT 24
Peak memory 248828 kb
Host smart-468089c5-0e88-4426-beba-530c40e2c73b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=445179500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.445179500
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.475856833
Short name T821
Test name
Test status
Simulation time 218119853 ps
CPU time 8.9 seconds
Started Jul 17 05:18:52 PM PDT 24
Finished Jul 17 05:19:02 PM PDT 24
Peak memory 252336 kb
Host smart-d03f26e5-0692-4997-8536-fa0e81b62ae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475856833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.475856833
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2344387753
Short name T175
Test name
Test status
Simulation time 399001583 ps
CPU time 8.7 seconds
Started Jul 17 05:18:49 PM PDT 24
Finished Jul 17 05:19:00 PM PDT 24
Peak memory 240924 kb
Host smart-1478844e-651d-451c-b41a-33102a6c8bf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2344387753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2344387753
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.761633983
Short name T744
Test name
Test status
Simulation time 37784697 ps
CPU time 1.32 seconds
Started Jul 17 05:18:46 PM PDT 24
Finished Jul 17 05:18:48 PM PDT 24
Peak memory 237000 kb
Host smart-c1c75a22-dbc6-4c10-a6a4-778f5e174199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=761633983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.761633983
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2915486322
Short name T746
Test name
Test status
Simulation time 533972374 ps
CPU time 40.96 seconds
Started Jul 17 05:18:44 PM PDT 24
Finished Jul 17 05:19:26 PM PDT 24
Peak memory 246268 kb
Host smart-2a6888c9-f0e7-4bae-a12e-6e2619e77cc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2915486322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2915486322
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3217048840
Short name T756
Test name
Test status
Simulation time 256680716 ps
CPU time 17.39 seconds
Started Jul 17 05:18:46 PM PDT 24
Finished Jul 17 05:19:04 PM PDT 24
Peak memory 254260 kb
Host smart-7acdc285-dfc1-406c-8d2f-0ce3068cb13e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3217048840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3217048840
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1094308403
Short name T722
Test name
Test status
Simulation time 59226821 ps
CPU time 9.64 seconds
Started Jul 17 05:18:50 PM PDT 24
Finished Jul 17 05:19:01 PM PDT 24
Peak memory 252432 kb
Host smart-6df68e45-8644-4b6d-90e2-269098c8d7de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094308403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1094308403
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2330247244
Short name T740
Test name
Test status
Simulation time 48621347 ps
CPU time 5.14 seconds
Started Jul 17 05:18:51 PM PDT 24
Finished Jul 17 05:18:58 PM PDT 24
Peak memory 238068 kb
Host smart-2bfb5546-9013-4bbd-b725-6277db8157e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2330247244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2330247244
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2560367462
Short name T752
Test name
Test status
Simulation time 8665415 ps
CPU time 1.32 seconds
Started Jul 17 05:18:51 PM PDT 24
Finished Jul 17 05:18:54 PM PDT 24
Peak memory 237136 kb
Host smart-cd7ac072-510b-4617-b584-e8fa4279af56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2560367462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2560367462
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4204611438
Short name T737
Test name
Test status
Simulation time 2246831832 ps
CPU time 44.13 seconds
Started Jul 17 05:18:50 PM PDT 24
Finished Jul 17 05:19:36 PM PDT 24
Peak memory 246324 kb
Host smart-ed43b9a8-60bc-4b78-ba12-cd0560983b72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4204611438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.4204611438
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2913436044
Short name T157
Test name
Test status
Simulation time 70173873166 ps
CPU time 320.91 seconds
Started Jul 17 05:18:51 PM PDT 24
Finished Jul 17 05:24:14 PM PDT 24
Peak memory 273396 kb
Host smart-be1c150f-49a4-47ea-b931-509ab5663219
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2913436044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2913436044
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3457503757
Short name T124
Test name
Test status
Simulation time 12117473896 ps
CPU time 454.42 seconds
Started Jul 17 05:18:44 PM PDT 24
Finished Jul 17 05:26:20 PM PDT 24
Peak memory 265948 kb
Host smart-72b26db6-69ea-4024-911c-291a2abc13b3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457503757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3457503757
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1005859385
Short name T751
Test name
Test status
Simulation time 60626900 ps
CPU time 8.89 seconds
Started Jul 17 05:18:49 PM PDT 24
Finished Jul 17 05:19:00 PM PDT 24
Peak memory 248972 kb
Host smart-3eb78882-1796-49b5-88b7-c27f29053c34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1005859385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1005859385
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1932831382
Short name T730
Test name
Test status
Simulation time 132055727 ps
CPU time 10.85 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:24 PM PDT 24
Peak memory 240264 kb
Host smart-9ad9ed54-b281-45af-8e5a-f33af6e3f9cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932831382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1932831382
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1312129693
Short name T177
Test name
Test status
Simulation time 370609965 ps
CPU time 7.62 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:18:56 PM PDT 24
Peak memory 240920 kb
Host smart-610b7158-4101-4323-b23a-a2767e0a0c28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1312129693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1312129693
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3866878162
Short name T713
Test name
Test status
Simulation time 24408837 ps
CPU time 1.29 seconds
Started Jul 17 05:18:50 PM PDT 24
Finished Jul 17 05:18:53 PM PDT 24
Peak memory 238068 kb
Host smart-145dd186-1bd5-4f1d-a897-03eb666b8d08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3866878162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3866878162
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2665315400
Short name T743
Test name
Test status
Simulation time 510255518 ps
CPU time 32.61 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:45 PM PDT 24
Peak memory 245256 kb
Host smart-9fa17c34-133c-406f-9688-7b407a303ec7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2665315400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2665315400
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3653600842
Short name T156
Test name
Test status
Simulation time 6125247683 ps
CPU time 162.83 seconds
Started Jul 17 05:18:49 PM PDT 24
Finished Jul 17 05:21:34 PM PDT 24
Peak memory 265912 kb
Host smart-c1b177db-e61b-430a-9b64-5948bf573922
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3653600842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3653600842
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1488531351
Short name T339
Test name
Test status
Simulation time 13184666358 ps
CPU time 281.2 seconds
Started Jul 17 05:18:50 PM PDT 24
Finished Jul 17 05:23:33 PM PDT 24
Peak memory 266132 kb
Host smart-bc0b193e-8d55-465e-968e-06bb0b4ad02f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488531351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1488531351
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1098282774
Short name T720
Test name
Test status
Simulation time 294883746 ps
CPU time 13.1 seconds
Started Jul 17 05:18:50 PM PDT 24
Finished Jul 17 05:19:05 PM PDT 24
Peak memory 249220 kb
Host smart-388387f1-d255-412f-83e8-9672229ef41a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1098282774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1098282774
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2097053653
Short name T255
Test name
Test status
Simulation time 179612265 ps
CPU time 8.12 seconds
Started Jul 17 05:18:51 PM PDT 24
Finished Jul 17 05:19:01 PM PDT 24
Peak memory 238020 kb
Host smart-eb4aeec0-fa9b-4d06-a6c8-5794985c426f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2097053653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2097053653
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2021981249
Short name T824
Test name
Test status
Simulation time 1077045655 ps
CPU time 13.82 seconds
Started Jul 17 05:19:07 PM PDT 24
Finished Jul 17 05:19:23 PM PDT 24
Peak memory 252352 kb
Host smart-59e31aec-8c1b-400f-982b-519236602eee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021981249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2021981249
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1210605325
Short name T189
Test name
Test status
Simulation time 121468501 ps
CPU time 8.13 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:19:24 PM PDT 24
Peak memory 241004 kb
Host smart-a1cf44cb-8b07-44da-8a25-0903e9c64721
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1210605325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1210605325
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1066898684
Short name T729
Test name
Test status
Simulation time 18205182 ps
CPU time 1.21 seconds
Started Jul 17 05:19:07 PM PDT 24
Finished Jul 17 05:19:10 PM PDT 24
Peak memory 238072 kb
Host smart-64061d80-7486-4327-b3b9-1daffbacead8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1066898684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1066898684
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1450663607
Short name T768
Test name
Test status
Simulation time 1319239083 ps
CPU time 21.6 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:33 PM PDT 24
Peak memory 246220 kb
Host smart-afe9dc00-1123-4f05-afc4-e93d3815fd61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1450663607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1450663607
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.418196872
Short name T130
Test name
Test status
Simulation time 15296774687 ps
CPU time 550.79 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:28:23 PM PDT 24
Peak memory 269868 kb
Host smart-8422a3e7-b171-4fbb-a381-ab5923b435ac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418196872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.418196872
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.272527561
Short name T710
Test name
Test status
Simulation time 201030969 ps
CPU time 6.66 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:20 PM PDT 24
Peak memory 249040 kb
Host smart-71117f92-fefd-4e04-a4f3-89f9cd9d5e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=272527561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.272527561
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1496926062
Short name T714
Test name
Test status
Simulation time 43272824 ps
CPU time 5.96 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:17 PM PDT 24
Peak memory 257392 kb
Host smart-e5cc4861-ce88-4a7a-83cf-bd4cdbb22c8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496926062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1496926062
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.569970438
Short name T715
Test name
Test status
Simulation time 96631631 ps
CPU time 4.82 seconds
Started Jul 17 05:19:05 PM PDT 24
Finished Jul 17 05:19:11 PM PDT 24
Peak memory 238064 kb
Host smart-0de3814d-abfa-42d9-89f7-43a7ed1022dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=569970438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.569970438
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3712579533
Short name T721
Test name
Test status
Simulation time 7266015 ps
CPU time 1.42 seconds
Started Jul 17 05:19:06 PM PDT 24
Finished Jul 17 05:19:09 PM PDT 24
Peak memory 238072 kb
Host smart-08c44b69-7b16-4f89-ba60-63462c88dd89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3712579533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3712579533
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2896508845
Short name T738
Test name
Test status
Simulation time 690791238 ps
CPU time 43.45 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:19:59 PM PDT 24
Peak memory 246264 kb
Host smart-dfe3de52-bdef-488b-bb8e-93ecfe74e099
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2896508845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2896508845
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2664167592
Short name T136
Test name
Test status
Simulation time 5529578048 ps
CPU time 330.07 seconds
Started Jul 17 05:19:06 PM PDT 24
Finished Jul 17 05:24:38 PM PDT 24
Peak memory 270148 kb
Host smart-e8b78a6e-5857-4fa3-8efb-d6dfab8f538f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664167592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2664167592
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3829690726
Short name T780
Test name
Test status
Simulation time 132952919 ps
CPU time 9.33 seconds
Started Jul 17 05:19:09 PM PDT 24
Finished Jul 17 05:19:23 PM PDT 24
Peak memory 254304 kb
Host smart-eb3f3ba0-4cb2-4042-9b12-489dc911f4ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3829690726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3829690726
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3689050146
Short name T180
Test name
Test status
Simulation time 234846757 ps
CPU time 23.46 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:19:40 PM PDT 24
Peak memory 238128 kb
Host smart-e01d575f-fff1-47d5-b3aa-46aab4d52010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3689050146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3689050146
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.706887986
Short name T741
Test name
Test status
Simulation time 55345497 ps
CPU time 5.11 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:17 PM PDT 24
Peak memory 257308 kb
Host smart-892dd0b2-1791-4bc5-b254-6034e6bc67e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706887986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.706887986
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2077709938
Short name T340
Test name
Test status
Simulation time 559190372 ps
CPU time 4.83 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:18 PM PDT 24
Peak memory 236980 kb
Host smart-2d92d150-16a2-4f58-992c-15912dd144ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2077709938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2077709938
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.177149963
Short name T163
Test name
Test status
Simulation time 6232389 ps
CPU time 1.5 seconds
Started Jul 17 05:19:06 PM PDT 24
Finished Jul 17 05:19:08 PM PDT 24
Peak memory 238076 kb
Host smart-21d070ff-52be-48b2-91e1-015d19ad4ee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=177149963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.177149963
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3538609840
Short name T767
Test name
Test status
Simulation time 86789979 ps
CPU time 11.55 seconds
Started Jul 17 05:19:07 PM PDT 24
Finished Jul 17 05:19:21 PM PDT 24
Peak memory 240940 kb
Host smart-40a45897-8181-4de7-a7c8-4c21a9ffd3c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3538609840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3538609840
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2378756904
Short name T786
Test name
Test status
Simulation time 1234642863 ps
CPU time 6.67 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:19 PM PDT 24
Peak memory 248960 kb
Host smart-7b902e79-360c-48df-967c-f0e173f16e63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2378756904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2378756904
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3196747883
Short name T807
Test name
Test status
Simulation time 133174678 ps
CPU time 5.92 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:19:22 PM PDT 24
Peak memory 249236 kb
Host smart-0c444d4b-599c-4a7c-a3e2-6b12ce916a2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196747883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3196747883
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.412878570
Short name T827
Test name
Test status
Simulation time 252056393 ps
CPU time 10.53 seconds
Started Jul 17 05:19:05 PM PDT 24
Finished Jul 17 05:19:16 PM PDT 24
Peak memory 240960 kb
Host smart-71852e61-8cf4-4884-a50d-8b43aa90385b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=412878570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.412878570
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1966821853
Short name T775
Test name
Test status
Simulation time 10395116 ps
CPU time 1.27 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:13 PM PDT 24
Peak memory 236064 kb
Host smart-10641475-a8a0-4a3f-84f2-9c2e8b83c3e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1966821853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1966821853
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1485702988
Short name T810
Test name
Test status
Simulation time 530462876 ps
CPU time 31.38 seconds
Started Jul 17 05:19:09 PM PDT 24
Finished Jul 17 05:19:45 PM PDT 24
Peak memory 249156 kb
Host smart-bd572b0f-60d1-416d-9451-8ec3ee4264fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1485702988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1485702988
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.178380733
Short name T119
Test name
Test status
Simulation time 4782703564 ps
CPU time 364.89 seconds
Started Jul 17 05:19:06 PM PDT 24
Finished Jul 17 05:25:13 PM PDT 24
Peak memory 265912 kb
Host smart-28a2fa15-1991-4bbf-9f14-e185b90873cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=178380733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.178380733
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3253308090
Short name T149
Test name
Test status
Simulation time 2782770335 ps
CPU time 334.91 seconds
Started Jul 17 05:19:07 PM PDT 24
Finished Jul 17 05:24:44 PM PDT 24
Peak memory 265900 kb
Host smart-df2a57ed-8451-4597-b6ec-ea6bfa4753ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253308090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3253308090
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1692038846
Short name T766
Test name
Test status
Simulation time 1388039112 ps
CPU time 28.07 seconds
Started Jul 17 05:19:07 PM PDT 24
Finished Jul 17 05:19:38 PM PDT 24
Peak memory 248028 kb
Host smart-5c3cde69-845e-4a94-b738-69fe142c0daf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1692038846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1692038846
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3965138541
Short name T783
Test name
Test status
Simulation time 373922112 ps
CPU time 15.91 seconds
Started Jul 17 05:19:06 PM PDT 24
Finished Jul 17 05:19:23 PM PDT 24
Peak memory 238064 kb
Host smart-006cc0e1-8f4c-41f5-905d-2220623ba100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3965138541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3965138541
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1039191722
Short name T338
Test name
Test status
Simulation time 4631224475 ps
CPU time 160.5 seconds
Started Jul 17 05:18:28 PM PDT 24
Finished Jul 17 05:21:09 PM PDT 24
Peak memory 241532 kb
Host smart-0e7d0f7f-bfc8-4071-a9e9-138b974cbbc1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1039191722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1039191722
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.271961653
Short name T803
Test name
Test status
Simulation time 14331314771 ps
CPU time 214.51 seconds
Started Jul 17 05:18:31 PM PDT 24
Finished Jul 17 05:22:07 PM PDT 24
Peak memory 238076 kb
Host smart-4704c935-52e6-418c-9eb9-9ecc5ab8be73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=271961653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.271961653
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3040592174
Short name T770
Test name
Test status
Simulation time 76577150 ps
CPU time 5.77 seconds
Started Jul 17 05:18:31 PM PDT 24
Finished Jul 17 05:18:39 PM PDT 24
Peak memory 240912 kb
Host smart-262934d3-052b-4d60-8431-b8966cfe5419
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3040592174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3040592174
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2827264316
Short name T818
Test name
Test status
Simulation time 514306015 ps
CPU time 9.12 seconds
Started Jul 17 05:18:27 PM PDT 24
Finished Jul 17 05:18:38 PM PDT 24
Peak memory 240836 kb
Host smart-2ce70b32-56bd-46d9-b41d-86c60c8bc507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827264316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2827264316
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.222248075
Short name T805
Test name
Test status
Simulation time 264235954 ps
CPU time 5.53 seconds
Started Jul 17 05:18:33 PM PDT 24
Finished Jul 17 05:18:41 PM PDT 24
Peak memory 238068 kb
Host smart-b62a2b5c-8fbf-440d-b0be-86ad57827def
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=222248075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.222248075
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.74919320
Short name T739
Test name
Test status
Simulation time 11931190 ps
CPU time 1.31 seconds
Started Jul 17 05:18:30 PM PDT 24
Finished Jul 17 05:18:32 PM PDT 24
Peak memory 237152 kb
Host smart-c84962f3-62be-486b-bc42-d955f6359e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=74919320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.74919320
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.824032078
Short name T785
Test name
Test status
Simulation time 1046680011 ps
CPU time 37.6 seconds
Started Jul 17 05:18:32 PM PDT 24
Finished Jul 17 05:19:12 PM PDT 24
Peak memory 246272 kb
Host smart-d8d80a89-95a7-42f4-bb17-a8fe01db9f56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=824032078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.824032078
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.400540051
Short name T143
Test name
Test status
Simulation time 2227202081 ps
CPU time 338.55 seconds
Started Jul 17 05:18:33 PM PDT 24
Finished Jul 17 05:24:14 PM PDT 24
Peak memory 266008 kb
Host smart-798f6473-5300-4361-bb0c-190dac9abca6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400540051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.400540051
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4199791912
Short name T708
Test name
Test status
Simulation time 289540050 ps
CPU time 8.35 seconds
Started Jul 17 05:18:25 PM PDT 24
Finished Jul 17 05:18:35 PM PDT 24
Peak memory 257352 kb
Host smart-21153a3a-a1a9-45da-9c20-e5ac596ae30f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4199791912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.4199791912
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.359121843
Short name T336
Test name
Test status
Simulation time 19244437 ps
CPU time 1.55 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:14 PM PDT 24
Peak memory 238016 kb
Host smart-ddc50e52-23b7-4682-b7a1-4df3a49c6f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=359121843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.359121843
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1166745030
Short name T815
Test name
Test status
Simulation time 9300878 ps
CPU time 1.23 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:14 PM PDT 24
Peak memory 237992 kb
Host smart-264f376a-3c40-46e8-a936-212e39409709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1166745030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1166745030
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3376443996
Short name T162
Test name
Test status
Simulation time 12124893 ps
CPU time 1.3 seconds
Started Jul 17 05:19:11 PM PDT 24
Finished Jul 17 05:19:19 PM PDT 24
Peak memory 238052 kb
Host smart-35c86e3b-43c8-4606-b787-476b3e63527f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3376443996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3376443996
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3490728795
Short name T778
Test name
Test status
Simulation time 10499565 ps
CPU time 1.3 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:13 PM PDT 24
Peak memory 238068 kb
Host smart-c53b5b0c-11ad-4e39-815c-69bc71d2aaba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3490728795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3490728795
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1438931377
Short name T235
Test name
Test status
Simulation time 11980018 ps
CPU time 1.65 seconds
Started Jul 17 05:19:07 PM PDT 24
Finished Jul 17 05:19:12 PM PDT 24
Peak memory 238080 kb
Host smart-3a3db7fd-8d3f-4e8a-9c86-d5507505a67d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1438931377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1438931377
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4113616393
Short name T334
Test name
Test status
Simulation time 8911873 ps
CPU time 1.43 seconds
Started Jul 17 05:19:05 PM PDT 24
Finished Jul 17 05:19:07 PM PDT 24
Peak memory 237084 kb
Host smart-bd1631f7-907c-43c1-8434-ec8f762f7ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4113616393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.4113616393
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3307381995
Short name T333
Test name
Test status
Simulation time 9230557 ps
CPU time 1.3 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:19:16 PM PDT 24
Peak memory 237172 kb
Host smart-af06ce39-b257-4f45-a88c-0e6d570160b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3307381995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3307381995
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2894826853
Short name T734
Test name
Test status
Simulation time 12738266 ps
CPU time 1.48 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:12 PM PDT 24
Peak memory 237156 kb
Host smart-82bd9282-ed5c-4c4c-9da5-99bf32452f20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2894826853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2894826853
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3258487848
Short name T755
Test name
Test status
Simulation time 570089674 ps
CPU time 81.15 seconds
Started Jul 17 05:18:23 PM PDT 24
Finished Jul 17 05:19:45 PM PDT 24
Peak memory 241148 kb
Host smart-956e79b7-fbd1-4ad1-a0c6-3ea572f0dfff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3258487848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3258487848
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4210048314
Short name T828
Test name
Test status
Simulation time 2854216898 ps
CPU time 172.86 seconds
Started Jul 17 05:18:28 PM PDT 24
Finished Jul 17 05:21:22 PM PDT 24
Peak memory 237112 kb
Host smart-015289b8-c6bc-44d3-b26a-6d87e6871da9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4210048314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.4210048314
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3038448823
Short name T808
Test name
Test status
Simulation time 83099524 ps
CPU time 5.21 seconds
Started Jul 17 05:18:32 PM PDT 24
Finished Jul 17 05:18:40 PM PDT 24
Peak memory 249208 kb
Host smart-9505abcd-ec6f-4874-8814-732b6da4b82d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3038448823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3038448823
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.453153885
Short name T777
Test name
Test status
Simulation time 113341049 ps
CPU time 9.11 seconds
Started Jul 17 05:18:30 PM PDT 24
Finished Jul 17 05:18:40 PM PDT 24
Peak memory 257240 kb
Host smart-f1c84ab3-447f-4d1c-88ee-b66e0a6b63a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453153885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.453153885
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2108534854
Short name T758
Test name
Test status
Simulation time 19644309 ps
CPU time 3.37 seconds
Started Jul 17 05:18:36 PM PDT 24
Finished Jul 17 05:18:42 PM PDT 24
Peak memory 241016 kb
Host smart-1c52f92b-c790-4f5e-a6a2-2470c58ed4d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2108534854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2108534854
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3461830479
Short name T747
Test name
Test status
Simulation time 8802862 ps
CPU time 1.59 seconds
Started Jul 17 05:18:32 PM PDT 24
Finished Jul 17 05:18:36 PM PDT 24
Peak memory 238072 kb
Host smart-c928582c-7fa3-494d-b101-27f448172545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3461830479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3461830479
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3488136248
Short name T814
Test name
Test status
Simulation time 163081724 ps
CPU time 25.68 seconds
Started Jul 17 05:18:31 PM PDT 24
Finished Jul 17 05:18:59 PM PDT 24
Peak memory 246276 kb
Host smart-f1e28299-4c70-4456-80ad-68764661ffcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3488136248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3488136248
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2804535420
Short name T825
Test name
Test status
Simulation time 1164967342 ps
CPU time 26.4 seconds
Started Jul 17 05:18:37 PM PDT 24
Finished Jul 17 05:19:06 PM PDT 24
Peak memory 257144 kb
Host smart-8f4c8d87-3a4f-43ed-bae7-51268460fcd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2804535420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2804535420
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2012917625
Short name T712
Test name
Test status
Simulation time 10131170 ps
CPU time 1.49 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:14 PM PDT 24
Peak memory 237988 kb
Host smart-af7f0581-29b9-4c6c-8cc8-0f8ccf5e5980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2012917625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2012917625
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.474262923
Short name T735
Test name
Test status
Simulation time 14948923 ps
CPU time 1.42 seconds
Started Jul 17 05:19:11 PM PDT 24
Finished Jul 17 05:19:19 PM PDT 24
Peak memory 238040 kb
Host smart-57f28b48-0aed-46df-abfb-44bf14e973ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=474262923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.474262923
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3912717168
Short name T762
Test name
Test status
Simulation time 10529492 ps
CPU time 1.58 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:14 PM PDT 24
Peak memory 237980 kb
Host smart-366398db-c5f7-4a9f-8a2d-21bc7b815afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3912717168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3912717168
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3728090099
Short name T749
Test name
Test status
Simulation time 10958074 ps
CPU time 1.65 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:19:16 PM PDT 24
Peak memory 237156 kb
Host smart-46496bad-b9fd-4449-9372-24c4bd26b8aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3728090099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3728090099
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.624508485
Short name T731
Test name
Test status
Simulation time 9480346 ps
CPU time 1.46 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:19:17 PM PDT 24
Peak memory 236140 kb
Host smart-55bc51a3-61eb-4bf8-ba84-b1d7a8787a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=624508485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.624508485
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3039939805
Short name T337
Test name
Test status
Simulation time 11965808 ps
CPU time 1.29 seconds
Started Jul 17 05:19:07 PM PDT 24
Finished Jul 17 05:19:11 PM PDT 24
Peak memory 238008 kb
Host smart-84b9a540-8cad-4e37-927e-189c6c74d487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3039939805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3039939805
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1829835627
Short name T795
Test name
Test status
Simulation time 16462579 ps
CPU time 1.25 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:19:17 PM PDT 24
Peak memory 238080 kb
Host smart-afed9865-7d64-48a4-b80f-12b584ad13d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1829835627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1829835627
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1679302288
Short name T792
Test name
Test status
Simulation time 8982086 ps
CPU time 1.53 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:19:16 PM PDT 24
Peak memory 238080 kb
Host smart-c63559fc-e31a-4c25-b0e7-8b01ec1489cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1679302288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1679302288
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1441209234
Short name T809
Test name
Test status
Simulation time 8678281 ps
CPU time 1.56 seconds
Started Jul 17 05:19:11 PM PDT 24
Finished Jul 17 05:19:19 PM PDT 24
Peak memory 238156 kb
Host smart-37e033d3-2e10-4978-93de-7f7997b7c90d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1441209234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1441209234
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.455251509
Short name T727
Test name
Test status
Simulation time 7002724 ps
CPU time 1.45 seconds
Started Jul 17 05:19:09 PM PDT 24
Finished Jul 17 05:19:15 PM PDT 24
Peak memory 237124 kb
Host smart-ec28181d-68b3-4cd3-bb35-f353eb5633fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=455251509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.455251509
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2814487798
Short name T188
Test name
Test status
Simulation time 1134057380 ps
CPU time 174.86 seconds
Started Jul 17 05:18:35 PM PDT 24
Finished Jul 17 05:21:32 PM PDT 24
Peak memory 240960 kb
Host smart-68ae79f1-abf3-4601-9e59-cbf34df64500
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2814487798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2814487798
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.854264696
Short name T226
Test name
Test status
Simulation time 7733590525 ps
CPU time 427.41 seconds
Started Jul 17 05:18:36 PM PDT 24
Finished Jul 17 05:25:45 PM PDT 24
Peak memory 241020 kb
Host smart-01cd4ca3-66b1-4941-b973-b78fd7e37b79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=854264696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.854264696
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1197792513
Short name T733
Test name
Test status
Simulation time 204134643 ps
CPU time 5.56 seconds
Started Jul 17 05:18:28 PM PDT 24
Finished Jul 17 05:18:35 PM PDT 24
Peak memory 249204 kb
Host smart-b82503c6-4678-4b40-b514-e50828df3a28
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1197792513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1197792513
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.4114550440
Short name T820
Test name
Test status
Simulation time 99258582 ps
CPU time 7.64 seconds
Started Jul 17 05:18:33 PM PDT 24
Finished Jul 17 05:18:43 PM PDT 24
Peak memory 238944 kb
Host smart-3a7650b4-35ed-4313-8929-fd7ac205e44b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114550440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.4114550440
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3130369841
Short name T788
Test name
Test status
Simulation time 89957496 ps
CPU time 3.2 seconds
Started Jul 17 05:18:29 PM PDT 24
Finished Jul 17 05:18:33 PM PDT 24
Peak memory 241008 kb
Host smart-7e0bdb6d-ada3-4037-8512-7f67c823f9c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3130369841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3130369841
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.80376094
Short name T793
Test name
Test status
Simulation time 6296569 ps
CPU time 1.46 seconds
Started Jul 17 05:18:26 PM PDT 24
Finished Jul 17 05:18:28 PM PDT 24
Peak memory 236188 kb
Host smart-3e052e25-1800-4990-b332-ac7967012ae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=80376094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.80376094
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3933037859
Short name T802
Test name
Test status
Simulation time 174297315 ps
CPU time 20.25 seconds
Started Jul 17 05:18:31 PM PDT 24
Finished Jul 17 05:18:53 PM PDT 24
Peak memory 249124 kb
Host smart-0e3dfede-af14-4890-8abc-1837e42031fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3933037859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3933037859
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2062622029
Short name T135
Test name
Test status
Simulation time 849306986 ps
CPU time 108.46 seconds
Started Jul 17 05:18:25 PM PDT 24
Finished Jul 17 05:20:14 PM PDT 24
Peak memory 265956 kb
Host smart-a6518fb1-0e9d-4493-8f81-bf0ad1578bb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2062622029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2062622029
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1414858307
Short name T144
Test name
Test status
Simulation time 2191461724 ps
CPU time 339.8 seconds
Started Jul 17 05:18:32 PM PDT 24
Finished Jul 17 05:24:14 PM PDT 24
Peak memory 269772 kb
Host smart-6b6faf80-335c-48b7-84d4-2c61138b578f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414858307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1414858307
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.227281139
Short name T234
Test name
Test status
Simulation time 251924814 ps
CPU time 9.79 seconds
Started Jul 17 05:18:38 PM PDT 24
Finished Jul 17 05:18:50 PM PDT 24
Peak memory 250044 kb
Host smart-30ac1bec-070f-471e-9cc6-e7ce4c886237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=227281139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.227281139
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.107602854
Short name T796
Test name
Test status
Simulation time 7593944 ps
CPU time 1.47 seconds
Started Jul 17 05:19:07 PM PDT 24
Finished Jul 17 05:19:12 PM PDT 24
Peak memory 236964 kb
Host smart-c26db2a3-eb2a-48e4-a80b-0e12d85cad0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=107602854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.107602854
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.869641836
Short name T161
Test name
Test status
Simulation time 12540817 ps
CPU time 1.29 seconds
Started Jul 17 05:19:17 PM PDT 24
Finished Jul 17 05:19:23 PM PDT 24
Peak memory 238028 kb
Host smart-cdf6cea7-130e-4444-9f95-70b73a48bcfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=869641836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.869641836
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2829487548
Short name T711
Test name
Test status
Simulation time 9055776 ps
CPU time 1.53 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:14 PM PDT 24
Peak memory 237040 kb
Host smart-dab35dbc-e4df-407c-a95d-500d19531533
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2829487548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2829487548
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3860835499
Short name T709
Test name
Test status
Simulation time 14701995 ps
CPU time 1.59 seconds
Started Jul 17 05:19:10 PM PDT 24
Finished Jul 17 05:19:17 PM PDT 24
Peak memory 238076 kb
Host smart-3fd0a998-4228-43cb-927f-3ef4989c5ac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3860835499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3860835499
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3409267550
Short name T716
Test name
Test status
Simulation time 12147757 ps
CPU time 1.44 seconds
Started Jul 17 05:19:11 PM PDT 24
Finished Jul 17 05:19:18 PM PDT 24
Peak memory 237088 kb
Host smart-d4785c89-a4a8-4ab2-9296-a531b0093e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3409267550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3409267550
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3528334427
Short name T725
Test name
Test status
Simulation time 9299139 ps
CPU time 1.58 seconds
Started Jul 17 05:19:11 PM PDT 24
Finished Jul 17 05:19:19 PM PDT 24
Peak memory 238160 kb
Host smart-0c928ca6-843b-40b4-804f-a6ab492c515f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3528334427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3528334427
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4110240375
Short name T787
Test name
Test status
Simulation time 21955652 ps
CPU time 1.44 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:14 PM PDT 24
Peak memory 238080 kb
Host smart-cfb0525c-1039-456c-badf-7f1ca5b58eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4110240375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4110240375
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2733665441
Short name T799
Test name
Test status
Simulation time 8181478 ps
CPU time 1.5 seconds
Started Jul 17 05:19:07 PM PDT 24
Finished Jul 17 05:19:10 PM PDT 24
Peak memory 238012 kb
Host smart-08dfcf42-98f3-4109-859c-cbad2da60938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2733665441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2733665441
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1630541146
Short name T771
Test name
Test status
Simulation time 16126476 ps
CPU time 1.22 seconds
Started Jul 17 05:19:09 PM PDT 24
Finished Jul 17 05:19:15 PM PDT 24
Peak memory 238080 kb
Host smart-83dffd38-8279-4544-ae6f-8742290b0b59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1630541146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1630541146
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.828642986
Short name T757
Test name
Test status
Simulation time 25079045 ps
CPU time 1.46 seconds
Started Jul 17 05:19:08 PM PDT 24
Finished Jul 17 05:19:14 PM PDT 24
Peak memory 237080 kb
Host smart-65b15df8-cd47-49fd-a08d-a4cf687dd2e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=828642986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.828642986
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3756534482
Short name T817
Test name
Test status
Simulation time 30445802 ps
CPU time 4.9 seconds
Started Jul 17 05:18:28 PM PDT 24
Finished Jul 17 05:18:34 PM PDT 24
Peak memory 241048 kb
Host smart-9c8e080a-4035-4023-b68b-56ac0476b8ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756534482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3756534482
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.184160279
Short name T754
Test name
Test status
Simulation time 64433537 ps
CPU time 5.18 seconds
Started Jul 17 05:18:36 PM PDT 24
Finished Jul 17 05:18:43 PM PDT 24
Peak memory 238072 kb
Host smart-cbb2b458-29f7-4918-bf02-6abd70f28e60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=184160279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.184160279
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.4084662000
Short name T723
Test name
Test status
Simulation time 7550978 ps
CPU time 1.4 seconds
Started Jul 17 05:18:31 PM PDT 24
Finished Jul 17 05:18:33 PM PDT 24
Peak memory 235988 kb
Host smart-a62e1ff5-a60f-4406-a6fc-6e7129027d99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4084662000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.4084662000
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.922022100
Short name T228
Test name
Test status
Simulation time 319232541 ps
CPU time 21.35 seconds
Started Jul 17 05:18:27 PM PDT 24
Finished Jul 17 05:18:50 PM PDT 24
Peak memory 245324 kb
Host smart-ddea2579-d5ec-4054-848d-ff0b58449d30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=922022100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.922022100
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3014456960
Short name T797
Test name
Test status
Simulation time 443893691 ps
CPU time 14.72 seconds
Started Jul 17 05:18:27 PM PDT 24
Finished Jul 17 05:18:43 PM PDT 24
Peak memory 249404 kb
Host smart-7086f844-d7e3-4e2e-93e2-cf7c074a68af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3014456960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3014456960
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.60025007
Short name T227
Test name
Test status
Simulation time 374726071 ps
CPU time 7.59 seconds
Started Jul 17 05:18:31 PM PDT 24
Finished Jul 17 05:18:40 PM PDT 24
Peak memory 240788 kb
Host smart-518b4a02-25ec-4e0c-90c2-b74ea6011472
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60025007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.alert_handler_csr_mem_rw_with_rand_reset.60025007
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1166305732
Short name T185
Test name
Test status
Simulation time 179958734 ps
CPU time 4.37 seconds
Started Jul 17 05:18:26 PM PDT 24
Finished Jul 17 05:18:32 PM PDT 24
Peak memory 238012 kb
Host smart-4cdf6a45-a40e-43f1-a1b5-6fc0f1966c06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1166305732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1166305732
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1729903784
Short name T781
Test name
Test status
Simulation time 8557630 ps
CPU time 1.42 seconds
Started Jul 17 05:18:34 PM PDT 24
Finished Jul 17 05:18:38 PM PDT 24
Peak memory 237124 kb
Host smart-984119f8-491b-4363-a744-bed6269c2805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1729903784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1729903784
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1318406395
Short name T728
Test name
Test status
Simulation time 273897757 ps
CPU time 21.52 seconds
Started Jul 17 05:18:33 PM PDT 24
Finished Jul 17 05:18:57 PM PDT 24
Peak memory 246244 kb
Host smart-8e86b1f0-a1dd-4b3f-8b2a-fbf55fcd4bd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1318406395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1318406395
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1681447399
Short name T125
Test name
Test status
Simulation time 6102246843 ps
CPU time 455.01 seconds
Started Jul 17 05:18:26 PM PDT 24
Finished Jul 17 05:26:02 PM PDT 24
Peak memory 265860 kb
Host smart-cc0b131f-983f-44cf-ad58-dd332f7daca6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681447399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1681447399
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2726342869
Short name T724
Test name
Test status
Simulation time 262026802 ps
CPU time 18.26 seconds
Started Jul 17 05:18:27 PM PDT 24
Finished Jul 17 05:18:47 PM PDT 24
Peak memory 249240 kb
Host smart-ca8b837e-936a-458b-ac32-c76554534ed7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2726342869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2726342869
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3744904459
Short name T760
Test name
Test status
Simulation time 173507630 ps
CPU time 6.87 seconds
Started Jul 17 05:18:51 PM PDT 24
Finished Jul 17 05:18:59 PM PDT 24
Peak memory 249156 kb
Host smart-5bb97d4c-39c2-41f5-9b01-4efcbfda09e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744904459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3744904459
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3475680321
Short name T804
Test name
Test status
Simulation time 121176354 ps
CPU time 5.97 seconds
Started Jul 17 05:18:33 PM PDT 24
Finished Jul 17 05:18:42 PM PDT 24
Peak memory 240968 kb
Host smart-7df4f5ba-4d6b-40c1-818b-d8693d5aa081
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3475680321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3475680321
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.850417676
Short name T717
Test name
Test status
Simulation time 16579382 ps
CPU time 1.31 seconds
Started Jul 17 05:18:36 PM PDT 24
Finished Jul 17 05:18:40 PM PDT 24
Peak memory 237076 kb
Host smart-615872e1-9f41-4504-9d25-a1bb7bc35df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=850417676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.850417676
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.793714475
Short name T745
Test name
Test status
Simulation time 1094839214 ps
CPU time 21.09 seconds
Started Jul 17 05:18:49 PM PDT 24
Finished Jul 17 05:19:12 PM PDT 24
Peak memory 246288 kb
Host smart-36a6b70c-6685-4aca-8d10-0cef1a0de335
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=793714475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.793714475
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.624066821
Short name T137
Test name
Test status
Simulation time 2397843724 ps
CPU time 170.69 seconds
Started Jul 17 05:18:33 PM PDT 24
Finished Jul 17 05:21:26 PM PDT 24
Peak memory 265876 kb
Host smart-27748c53-4e78-43ed-a3b9-322fabc0648a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=624066821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.624066821
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4218403268
Short name T150
Test name
Test status
Simulation time 113453031202 ps
CPU time 441.63 seconds
Started Jul 17 05:18:32 PM PDT 24
Finished Jul 17 05:25:57 PM PDT 24
Peak memory 265800 kb
Host smart-40ee9374-a7f4-4d3e-8f9c-dfcd0253b574
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218403268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.4218403268
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1155911944
Short name T736
Test name
Test status
Simulation time 524725037 ps
CPU time 10.96 seconds
Started Jul 17 05:18:34 PM PDT 24
Finished Jul 17 05:18:47 PM PDT 24
Peak memory 253240 kb
Host smart-46fcb519-b926-429b-9568-6f4347d4708c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1155911944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1155911944
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4110242694
Short name T765
Test name
Test status
Simulation time 56378546 ps
CPU time 4.89 seconds
Started Jul 17 05:18:45 PM PDT 24
Finished Jul 17 05:18:51 PM PDT 24
Peak memory 241040 kb
Host smart-7d8a7826-f205-4ef5-b248-6d8428de4e28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110242694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.4110242694
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2690056827
Short name T784
Test name
Test status
Simulation time 124255554 ps
CPU time 10.12 seconds
Started Jul 17 05:18:52 PM PDT 24
Finished Jul 17 05:19:03 PM PDT 24
Peak memory 238048 kb
Host smart-3a0ca62f-b099-4d34-a98b-5f9a9eff8a96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2690056827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2690056827
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3326776332
Short name T748
Test name
Test status
Simulation time 12850045 ps
CPU time 1.55 seconds
Started Jul 17 05:18:45 PM PDT 24
Finished Jul 17 05:18:48 PM PDT 24
Peak memory 237072 kb
Host smart-9cce4928-c951-4bf4-bb17-46f2714ae8b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3326776332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3326776332
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2280411660
Short name T186
Test name
Test status
Simulation time 264521577 ps
CPU time 23.46 seconds
Started Jul 17 05:18:44 PM PDT 24
Finished Jul 17 05:19:08 PM PDT 24
Peak memory 246228 kb
Host smart-fee91df4-0425-4f54-8466-2c36cd0d28ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2280411660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2280411660
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.868437448
Short name T140
Test name
Test status
Simulation time 902779382 ps
CPU time 110.26 seconds
Started Jul 17 05:18:45 PM PDT 24
Finished Jul 17 05:20:36 PM PDT 24
Peak memory 268940 kb
Host smart-8bdf8006-cdee-4284-a07b-57c7f53f1334
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=868437448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.868437448
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.470394525
Short name T155
Test name
Test status
Simulation time 24434238647 ps
CPU time 455.57 seconds
Started Jul 17 05:18:50 PM PDT 24
Finished Jul 17 05:26:27 PM PDT 24
Peak memory 265836 kb
Host smart-c600b851-c9a6-4b2d-8723-e34c18a2758f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470394525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.470394525
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1734359881
Short name T823
Test name
Test status
Simulation time 1441074201 ps
CPU time 21.03 seconds
Started Jul 17 05:18:44 PM PDT 24
Finished Jul 17 05:19:05 PM PDT 24
Peak memory 254820 kb
Host smart-419957bc-2178-4fb5-9c69-c25d9d34f296
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1734359881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1734359881
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3262339402
Short name T761
Test name
Test status
Simulation time 164176839 ps
CPU time 7.19 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:18:56 PM PDT 24
Peak memory 239788 kb
Host smart-bc9bf07f-d586-478a-9105-30befe6525b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262339402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3262339402
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1274255729
Short name T176
Test name
Test status
Simulation time 366719421 ps
CPU time 7.41 seconds
Started Jul 17 05:18:42 PM PDT 24
Finished Jul 17 05:18:51 PM PDT 24
Peak memory 237112 kb
Host smart-b79a6cae-be46-4d08-aa0f-eda608c1f4da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1274255729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1274255729
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2156627597
Short name T773
Test name
Test status
Simulation time 10512311 ps
CPU time 1.74 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:18:50 PM PDT 24
Peak memory 238072 kb
Host smart-07597b9a-55c7-4066-b5ba-1e90b9cdf993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2156627597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2156627597
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3919958786
Short name T819
Test name
Test status
Simulation time 366456550 ps
CPU time 11.13 seconds
Started Jul 17 05:18:46 PM PDT 24
Finished Jul 17 05:18:58 PM PDT 24
Peak memory 245252 kb
Host smart-c690db0b-4386-41bf-9358-8b9dcace0a2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3919958786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3919958786
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2632591207
Short name T134
Test name
Test status
Simulation time 15487406719 ps
CPU time 986.59 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:35:15 PM PDT 24
Peak memory 265884 kb
Host smart-4d94d076-dad6-4973-bffc-aa156b4228bb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632591207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2632591207
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4008192062
Short name T826
Test name
Test status
Simulation time 553283866 ps
CPU time 19.19 seconds
Started Jul 17 05:18:47 PM PDT 24
Finished Jul 17 05:19:08 PM PDT 24
Peak memory 254500 kb
Host smart-7ed33db2-5865-4e2e-a1e8-eaa03738dc83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4008192062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4008192062
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2556655625
Short name T779
Test name
Test status
Simulation time 565267199 ps
CPU time 36.29 seconds
Started Jul 17 05:18:48 PM PDT 24
Finished Jul 17 05:19:25 PM PDT 24
Peak memory 246464 kb
Host smart-9a30080c-be25-4eab-9b27-14df4e671b50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2556655625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2556655625
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3675455433
Short name T602
Test name
Test status
Simulation time 132206496433 ps
CPU time 1973.83 seconds
Started Jul 17 06:07:48 PM PDT 24
Finished Jul 17 06:40:47 PM PDT 24
Peak memory 287608 kb
Host smart-f5c33d0f-ce45-4e1a-b590-30ac3b6eff3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675455433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3675455433
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3686609837
Short name T221
Test name
Test status
Simulation time 627092139 ps
CPU time 9.47 seconds
Started Jul 17 06:07:49 PM PDT 24
Finished Jul 17 06:08:04 PM PDT 24
Peak memory 248660 kb
Host smart-f021d062-8747-437d-8996-ff58a08ff885
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3686609837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3686609837
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1170102587
Short name T598
Test name
Test status
Simulation time 1583595361 ps
CPU time 24.65 seconds
Started Jul 17 06:08:00 PM PDT 24
Finished Jul 17 06:08:27 PM PDT 24
Peak memory 256192 kb
Host smart-8d2e5a19-c904-4ba5-9edb-7e874ec5d5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11701
02587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1170102587
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.10695361
Short name T388
Test name
Test status
Simulation time 159814179 ps
CPU time 10.24 seconds
Started Jul 17 06:07:49 PM PDT 24
Finished Jul 17 06:08:05 PM PDT 24
Peak memory 248044 kb
Host smart-8170c258-6eb5-48e0-bd5a-fc66f49255f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10695
361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.10695361
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.140685522
Short name T554
Test name
Test status
Simulation time 409155505463 ps
CPU time 2523.98 seconds
Started Jul 17 06:07:55 PM PDT 24
Finished Jul 17 06:50:00 PM PDT 24
Peak memory 289164 kb
Host smart-b269ccb5-6514-433a-8c79-e5babd713a1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140685522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.140685522
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.889235598
Short name T101
Test name
Test status
Simulation time 18529538395 ps
CPU time 982.67 seconds
Started Jul 17 06:07:49 PM PDT 24
Finished Jul 17 06:24:17 PM PDT 24
Peak memory 284296 kb
Host smart-4e8fad52-b0da-4f41-a856-3425ea00da31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889235598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.889235598
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2864218286
Short name T658
Test name
Test status
Simulation time 93509785 ps
CPU time 4.71 seconds
Started Jul 17 06:07:51 PM PDT 24
Finished Jul 17 06:08:04 PM PDT 24
Peak memory 248644 kb
Host smart-23433966-8ac2-4502-b24d-c7ebf133a8b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28642
18286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2864218286
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2127655027
Short name T579
Test name
Test status
Simulation time 1073030739 ps
CPU time 22.35 seconds
Started Jul 17 06:07:50 PM PDT 24
Finished Jul 17 06:08:17 PM PDT 24
Peak memory 256368 kb
Host smart-e1d093d4-4bcc-4aa9-976e-ea0eca96ecbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21276
55027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2127655027
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.713954257
Short name T30
Test name
Test status
Simulation time 3954786560 ps
CPU time 66.88 seconds
Started Jul 17 06:07:55 PM PDT 24
Finished Jul 17 06:09:04 PM PDT 24
Peak memory 277200 kb
Host smart-389faa63-d30a-4ed5-b4b6-2f2b7a451278
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=713954257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.713954257
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.702878897
Short name T343
Test name
Test status
Simulation time 1761261720 ps
CPU time 52.26 seconds
Started Jul 17 06:07:46 PM PDT 24
Finished Jul 17 06:08:44 PM PDT 24
Peak memory 248860 kb
Host smart-b129073c-fbfa-4642-ac78-eb076253cb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70287
8897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.702878897
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2315171637
Short name T613
Test name
Test status
Simulation time 145141654763 ps
CPU time 2428.81 seconds
Started Jul 17 06:07:59 PM PDT 24
Finished Jul 17 06:48:30 PM PDT 24
Peak memory 289492 kb
Host smart-ba0ad3cc-9063-4320-aaac-345d1ff50aa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315171637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2315171637
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1660555351
Short name T652
Test name
Test status
Simulation time 1105242045 ps
CPU time 15.57 seconds
Started Jul 17 06:07:46 PM PDT 24
Finished Jul 17 06:08:08 PM PDT 24
Peak memory 248688 kb
Host smart-19af9927-3e93-4665-93f1-659fe4fa1f1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1660555351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1660555351
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1986165552
Short name T622
Test name
Test status
Simulation time 27646614956 ps
CPU time 299.21 seconds
Started Jul 17 06:07:47 PM PDT 24
Finished Jul 17 06:12:52 PM PDT 24
Peak memory 257016 kb
Host smart-f32d5f32-af00-4a1e-bf70-d7e95da56a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19861
65552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1986165552
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1155554122
Short name T389
Test name
Test status
Simulation time 708068146 ps
CPU time 21.55 seconds
Started Jul 17 06:07:55 PM PDT 24
Finished Jul 17 06:08:18 PM PDT 24
Peak memory 248208 kb
Host smart-d7603760-a392-43ac-8993-74c550043942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11555
54122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1155554122
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3580445760
Short name T28
Test name
Test status
Simulation time 39119898690 ps
CPU time 2346.37 seconds
Started Jul 17 06:07:45 PM PDT 24
Finished Jul 17 06:46:58 PM PDT 24
Peak memory 289536 kb
Host smart-e63fab57-490f-469a-8812-5ee2c3fa139e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580445760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3580445760
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1515804021
Short name T64
Test name
Test status
Simulation time 25275414584 ps
CPU time 260.68 seconds
Started Jul 17 06:07:50 PM PDT 24
Finished Jul 17 06:12:15 PM PDT 24
Peak memory 248812 kb
Host smart-f202c6a1-7c04-44e5-99ee-19fd11e9010c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515804021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1515804021
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.125485847
Short name T606
Test name
Test status
Simulation time 732924493 ps
CPU time 46.79 seconds
Started Jul 17 06:07:49 PM PDT 24
Finished Jul 17 06:08:41 PM PDT 24
Peak memory 248616 kb
Host smart-d0d34798-766e-4f51-9131-1e58503cd035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12548
5847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.125485847
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3325927771
Short name T619
Test name
Test status
Simulation time 295302080 ps
CPU time 27.79 seconds
Started Jul 17 06:07:45 PM PDT 24
Finished Jul 17 06:08:18 PM PDT 24
Peak memory 248200 kb
Host smart-9e389af6-f566-4ad7-bb8d-6a78b7ac9632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33259
27771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3325927771
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1331855037
Short name T267
Test name
Test status
Simulation time 272560098 ps
CPU time 26.93 seconds
Started Jul 17 06:07:45 PM PDT 24
Finished Jul 17 06:08:18 PM PDT 24
Peak memory 248624 kb
Host smart-441130a5-a792-4e79-b604-1b1981674672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13318
55037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1331855037
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1663849548
Short name T413
Test name
Test status
Simulation time 1298440880 ps
CPU time 44.14 seconds
Started Jul 17 06:07:49 PM PDT 24
Finished Jul 17 06:08:38 PM PDT 24
Peak memory 248596 kb
Host smart-622d8df7-be60-4d33-b9c1-70f7690f75b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16638
49548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1663849548
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.335342654
Short name T258
Test name
Test status
Simulation time 33498584900 ps
CPU time 1816.52 seconds
Started Jul 17 06:07:46 PM PDT 24
Finished Jul 17 06:38:08 PM PDT 24
Peak memory 284532 kb
Host smart-e4a234d5-d648-4965-83ed-7ce8169b3107
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335342654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.335342654
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3225250474
Short name T195
Test name
Test status
Simulation time 31982905 ps
CPU time 2.87 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:37 PM PDT 24
Peak memory 248964 kb
Host smart-35244fee-a11f-45ac-8110-7a32e9ac0820
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3225250474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3225250474
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3215187039
Short name T371
Test name
Test status
Simulation time 70704907123 ps
CPU time 1233.41 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:29:01 PM PDT 24
Peak memory 284644 kb
Host smart-0cb0bfa5-11f2-44a5-9bd1-d9b82b0ccaf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215187039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3215187039
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1616450122
Short name T499
Test name
Test status
Simulation time 3889884002 ps
CPU time 17.66 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:08:58 PM PDT 24
Peak memory 248824 kb
Host smart-c732d8bf-19b1-4c42-8c80-89e36f90c926
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1616450122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1616450122
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.4238596301
Short name T40
Test name
Test status
Simulation time 4091113662 ps
CPU time 142.13 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:11:06 PM PDT 24
Peak memory 257012 kb
Host smart-8294b49d-c410-42b0-bfd8-b1b6cf2eac09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42385
96301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.4238596301
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3141744809
Short name T358
Test name
Test status
Simulation time 877116355 ps
CPU time 9.8 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:08:54 PM PDT 24
Peak memory 248204 kb
Host smart-596c5912-a4e5-47ff-a5fc-5c861b464d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31417
44809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3141744809
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2292084794
Short name T316
Test name
Test status
Simulation time 32595672381 ps
CPU time 2086.1 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:43:18 PM PDT 24
Peak memory 287120 kb
Host smart-45cf2f55-f68b-4739-9736-f108531922b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292084794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2292084794
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.126476667
Short name T600
Test name
Test status
Simulation time 188161366764 ps
CPU time 1602.69 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:35:10 PM PDT 24
Peak memory 289592 kb
Host smart-7324ee57-5b47-4569-a6d8-e82d8ade1665
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126476667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.126476667
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3714203839
Short name T303
Test name
Test status
Simulation time 85666460213 ps
CPU time 249.98 seconds
Started Jul 17 06:08:08 PM PDT 24
Finished Jul 17 06:12:19 PM PDT 24
Peak memory 248708 kb
Host smart-5a0288de-0b80-442f-94f0-56034ef607a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714203839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3714203839
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.602458076
Short name T363
Test name
Test status
Simulation time 314093927 ps
CPU time 18.02 seconds
Started Jul 17 06:08:13 PM PDT 24
Finished Jul 17 06:08:32 PM PDT 24
Peak memory 248740 kb
Host smart-88de5627-8992-4a57-8d67-efdfd4cfe045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60245
8076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.602458076
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.976056670
Short name T429
Test name
Test status
Simulation time 3742282523 ps
CPU time 36.05 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:09:08 PM PDT 24
Peak memory 248408 kb
Host smart-6f227320-a6e7-4af5-af02-3a3707a57eaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97605
6670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.976056670
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.4082557592
Short name T460
Test name
Test status
Simulation time 168195033 ps
CPU time 5.72 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:08:33 PM PDT 24
Peak memory 248172 kb
Host smart-dfd6b23b-6a93-4db0-9ca6-df7af879e228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40825
57592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4082557592
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.878535825
Short name T552
Test name
Test status
Simulation time 1749211990 ps
CPU time 18.76 seconds
Started Jul 17 06:08:25 PM PDT 24
Finished Jul 17 06:08:45 PM PDT 24
Peak memory 256140 kb
Host smart-b7da2719-c4d9-49c6-9442-4153cd93b059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87853
5825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.878535825
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1140066531
Short name T553
Test name
Test status
Simulation time 114977988116 ps
CPU time 1883.88 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:39:56 PM PDT 24
Peak memory 289636 kb
Host smart-d6204a6d-a1e3-4203-bc86-bc243736f821
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140066531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1140066531
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1401841771
Short name T202
Test name
Test status
Simulation time 88403271 ps
CPU time 3.67 seconds
Started Jul 17 06:08:38 PM PDT 24
Finished Jul 17 06:08:51 PM PDT 24
Peak memory 248828 kb
Host smart-2a242873-cba5-432c-b515-79d8a9e94a5b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1401841771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1401841771
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.506606554
Short name T475
Test name
Test status
Simulation time 59620131909 ps
CPU time 1525.05 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:34:11 PM PDT 24
Peak memory 289724 kb
Host smart-b0c65f8b-fb29-4f8e-ab02-11440f84b577
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506606554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.506606554
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.4217853346
Short name T530
Test name
Test status
Simulation time 215132128 ps
CPU time 11.69 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:08:52 PM PDT 24
Peak memory 248684 kb
Host smart-50396571-dc42-48b5-a9a8-651a947adda4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4217853346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.4217853346
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1445289314
Short name T546
Test name
Test status
Simulation time 1062608015 ps
CPU time 32.62 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:09:14 PM PDT 24
Peak memory 255992 kb
Host smart-9355015d-9920-4e12-b618-5d3c3b333471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14452
89314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1445289314
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1852857151
Short name T405
Test name
Test status
Simulation time 564797654 ps
CPU time 31.42 seconds
Started Jul 17 06:08:25 PM PDT 24
Finished Jul 17 06:08:57 PM PDT 24
Peak memory 256924 kb
Host smart-ef20b789-b82a-49f8-b509-a1b04e8bdb1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18528
57151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1852857151
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.4192370820
Short name T72
Test name
Test status
Simulation time 23639607775 ps
CPU time 528.37 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:17:28 PM PDT 24
Peak memory 273064 kb
Host smart-cdedfd6b-086e-445a-96c0-567508b690f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192370820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.4192370820
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1576504388
Short name T297
Test name
Test status
Simulation time 190761087656 ps
CPU time 532.15 seconds
Started Jul 17 06:08:13 PM PDT 24
Finished Jul 17 06:17:06 PM PDT 24
Peak memory 255032 kb
Host smart-47414a8b-ec26-496a-a391-63f1ca929ae3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576504388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1576504388
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.4045236786
Short name T651
Test name
Test status
Simulation time 842637060 ps
CPU time 32.66 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:09:01 PM PDT 24
Peak memory 248640 kb
Host smart-c1906e6e-5601-4697-8d0b-f5d086924838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40452
36786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.4045236786
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1806922005
Short name T632
Test name
Test status
Simulation time 798177648 ps
CPU time 59.08 seconds
Started Jul 17 06:08:25 PM PDT 24
Finished Jul 17 06:09:24 PM PDT 24
Peak memory 248424 kb
Host smart-229ed905-1408-4781-9c2a-659973777500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18069
22005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1806922005
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.433987685
Short name T211
Test name
Test status
Simulation time 1401986058 ps
CPU time 26.16 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:08:55 PM PDT 24
Peak memory 248628 kb
Host smart-773530f8-1e2b-4afa-9a78-dc0ebc50f753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43398
7685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.433987685
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3005827248
Short name T673
Test name
Test status
Simulation time 531232391719 ps
CPU time 1528.64 seconds
Started Jul 17 06:11:48 PM PDT 24
Finished Jul 17 06:37:18 PM PDT 24
Peak memory 273412 kb
Host smart-467355d5-118c-418d-b568-042c2d8e630d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005827248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3005827248
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1676790089
Short name T54
Test name
Test status
Simulation time 104852022825 ps
CPU time 1527.37 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:34:12 PM PDT 24
Peak memory 284280 kb
Host smart-776490b6-6247-4c9a-a448-a6a7d42229d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676790089 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1676790089
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2910430685
Short name T646
Test name
Test status
Simulation time 202919628936 ps
CPU time 1462.91 seconds
Started Jul 17 06:08:20 PM PDT 24
Finished Jul 17 06:32:45 PM PDT 24
Peak memory 273500 kb
Host smart-a9503c8c-1f4f-4e29-8ed5-736af5c61a4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910430685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2910430685
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3949564954
Short name T662
Test name
Test status
Simulation time 1429019281 ps
CPU time 14.89 seconds
Started Jul 17 06:08:19 PM PDT 24
Finished Jul 17 06:08:36 PM PDT 24
Peak memory 248628 kb
Host smart-d1570f9f-678e-4c6a-83a0-ee864d543e54
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3949564954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3949564954
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1797238476
Short name T458
Test name
Test status
Simulation time 13358607134 ps
CPU time 111.93 seconds
Started Jul 17 06:08:23 PM PDT 24
Finished Jul 17 06:10:16 PM PDT 24
Peak memory 250884 kb
Host smart-f551f000-62c2-44c5-87f5-4b9d3e254173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17972
38476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1797238476
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1790656164
Short name T89
Test name
Test status
Simulation time 1801014841 ps
CPU time 28.41 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:09:07 PM PDT 24
Peak memory 248072 kb
Host smart-17ae3256-79da-434c-a460-9b0ea18871bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17906
56164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1790656164
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1908526353
Short name T686
Test name
Test status
Simulation time 105300846349 ps
CPU time 1755.4 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:37:43 PM PDT 24
Peak memory 273448 kb
Host smart-4d919fde-7c20-4637-b567-1e59b91a2abc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908526353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1908526353
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.58965289
Short name T467
Test name
Test status
Simulation time 47124802815 ps
CPU time 1290.73 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:30:09 PM PDT 24
Peak memory 289512 kb
Host smart-bd4b3059-83b0-4018-9b20-3a2613b84010
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58965289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.58965289
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.497993462
Short name T24
Test name
Test status
Simulation time 645799035 ps
CPU time 42.33 seconds
Started Jul 17 06:08:18 PM PDT 24
Finished Jul 17 06:09:02 PM PDT 24
Peak memory 255936 kb
Host smart-fc21a389-b71a-4a41-80d7-c5e2f81d8974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49799
3462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.497993462
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.516352860
Short name T36
Test name
Test status
Simulation time 161109118 ps
CPU time 3.86 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:08:50 PM PDT 24
Peak memory 240436 kb
Host smart-aea7853a-d071-4018-92da-781a14fe1587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51635
2860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.516352860
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.231641188
Short name T112
Test name
Test status
Simulation time 327493462 ps
CPU time 15.8 seconds
Started Jul 17 06:08:20 PM PDT 24
Finished Jul 17 06:08:37 PM PDT 24
Peak memory 256668 kb
Host smart-6c807c17-d239-47d6-aac7-1c5bd03c2dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23164
1188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.231641188
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.968254986
Short name T574
Test name
Test status
Simulation time 8878310024 ps
CPU time 258.72 seconds
Started Jul 17 06:08:23 PM PDT 24
Finished Jul 17 06:12:43 PM PDT 24
Peak memory 257024 kb
Host smart-840f23ec-e7b2-4e9c-9480-0846381d22d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968254986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.968254986
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2627046477
Short name T252
Test name
Test status
Simulation time 11969842452 ps
CPU time 755.51 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:21:14 PM PDT 24
Peak memory 270744 kb
Host smart-6d5c8686-bb97-4273-9c6d-72c20ad67bdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627046477 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2627046477
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.59656299
Short name T660
Test name
Test status
Simulation time 38291051867 ps
CPU time 1064.95 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:26:15 PM PDT 24
Peak memory 283744 kb
Host smart-a48dd619-416f-4815-bf73-b1ef0c7fdd5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59656299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.59656299
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.578729591
Short name T596
Test name
Test status
Simulation time 3905346385 ps
CPU time 13.33 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:08:43 PM PDT 24
Peak memory 248760 kb
Host smart-a07c59a9-cdf2-477a-b6a4-121369420592
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=578729591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.578729591
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1707836787
Short name T637
Test name
Test status
Simulation time 24157430899 ps
CPU time 225.35 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:12:15 PM PDT 24
Peak memory 256312 kb
Host smart-87020307-1488-437d-8910-a8e46b336c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17078
36787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1707836787
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3861897088
Short name T382
Test name
Test status
Simulation time 159761714 ps
CPU time 15.55 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:08:46 PM PDT 24
Peak memory 248276 kb
Host smart-7adb867a-1ae9-433f-8459-62c12c727d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38618
97088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3861897088
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.223365697
Short name T292
Test name
Test status
Simulation time 110435541800 ps
CPU time 3189.62 seconds
Started Jul 17 06:08:25 PM PDT 24
Finished Jul 17 07:01:36 PM PDT 24
Peak memory 281556 kb
Host smart-10f1a42b-5903-4565-b637-3fb75aeb7e36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223365697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.223365697
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.4116128829
Short name T550
Test name
Test status
Simulation time 90317468433 ps
CPU time 2383.91 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:48:13 PM PDT 24
Peak memory 281612 kb
Host smart-682066f8-0819-446d-9bbb-b6e5558d6223
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116128829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.4116128829
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2312016437
Short name T313
Test name
Test status
Simulation time 6657414136 ps
CPU time 261.09 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:12:52 PM PDT 24
Peak memory 255180 kb
Host smart-296a5d9b-3302-4c52-9471-67c7c21ed9f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312016437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2312016437
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.247731872
Short name T535
Test name
Test status
Simulation time 572070024 ps
CPU time 39.78 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:09:17 PM PDT 24
Peak memory 256212 kb
Host smart-035e9912-61b1-4e7d-a35b-c5fc7c3feb44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24773
1872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.247731872
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2375237642
Short name T80
Test name
Test status
Simulation time 115206918 ps
CPU time 11.56 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:08:50 PM PDT 24
Peak memory 248664 kb
Host smart-a895ca44-d815-4802-b197-f08dde158bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23752
37642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2375237642
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1793334193
Short name T514
Test name
Test status
Simulation time 226865623 ps
CPU time 4.3 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:38 PM PDT 24
Peak memory 240416 kb
Host smart-d45a15d5-d4f3-4ce1-a060-1a422dd4198e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17933
34193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1793334193
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.4211541174
Short name T538
Test name
Test status
Simulation time 62615282 ps
CPU time 4.16 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:08:36 PM PDT 24
Peak memory 251012 kb
Host smart-dcf4a0f7-54e7-4e1d-897e-c7c6eb012aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42115
41174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.4211541174
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.24945668
Short name T625
Test name
Test status
Simulation time 518353376069 ps
CPU time 2879.28 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:56:27 PM PDT 24
Peak memory 297440 kb
Host smart-f31597b4-378b-4112-969f-e89d214c073f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24945668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_hand
ler_stress_all.24945668
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3445164845
Short name T206
Test name
Test status
Simulation time 56722222 ps
CPU time 2.6 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:08:30 PM PDT 24
Peak memory 248936 kb
Host smart-699126c4-acfd-4e63-93f7-8acb52066d08
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3445164845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3445164845
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3440865742
Short name T478
Test name
Test status
Simulation time 14109041333 ps
CPU time 1351.01 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:31:07 PM PDT 24
Peak memory 284388 kb
Host smart-cb6d033f-9f06-4e2d-a2ca-5322d3d30d65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440865742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3440865742
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2646076179
Short name T215
Test name
Test status
Simulation time 818651350 ps
CPU time 20.02 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:08:48 PM PDT 24
Peak memory 248684 kb
Host smart-15322f3b-c6d0-4491-96cc-66b99f5a6fe1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2646076179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2646076179
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2633971653
Short name T422
Test name
Test status
Simulation time 15334619236 ps
CPU time 228.19 seconds
Started Jul 17 06:08:16 PM PDT 24
Finished Jul 17 06:12:05 PM PDT 24
Peak memory 256552 kb
Host smart-b7dd49ae-d4ed-44e6-bc09-c28f1fdf3daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26339
71653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2633971653
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3490700379
Short name T364
Test name
Test status
Simulation time 626258852 ps
CPU time 10.69 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:43 PM PDT 24
Peak memory 248720 kb
Host smart-53a1ac00-a00d-4b1f-983d-bce71b0fdc16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34907
00379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3490700379
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2343457018
Short name T496
Test name
Test status
Simulation time 6524002952 ps
CPU time 594.85 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:18:39 PM PDT 24
Peak memory 268260 kb
Host smart-3727bedd-c29f-4dbb-b00e-ce712ea29c91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343457018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2343457018
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1440514546
Short name T564
Test name
Test status
Simulation time 10258199281 ps
CPU time 402.55 seconds
Started Jul 17 06:08:22 PM PDT 24
Finished Jul 17 06:15:06 PM PDT 24
Peak memory 255516 kb
Host smart-5d414bb6-1373-41ea-ab58-65b071838c2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440514546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1440514546
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2168433856
Short name T562
Test name
Test status
Simulation time 772416887 ps
CPU time 51.49 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:09:21 PM PDT 24
Peak memory 248716 kb
Host smart-17f80429-f0e9-4372-843e-f38965c7840c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21684
33856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2168433856
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.338752000
Short name T628
Test name
Test status
Simulation time 1509355533 ps
CPU time 22.68 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:08:58 PM PDT 24
Peak memory 254880 kb
Host smart-62bc5eb3-f518-4538-aa21-b371fa3945a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33875
2000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.338752000
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.4044306377
Short name T481
Test name
Test status
Simulation time 276749713 ps
CPU time 19.62 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:53 PM PDT 24
Peak memory 256392 kb
Host smart-fa96e9b5-9365-481a-a7c1-b3a2081a2c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40443
06377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.4044306377
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3747372043
Short name T259
Test name
Test status
Simulation time 17064096560 ps
CPU time 72.1 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:09:44 PM PDT 24
Peak memory 256064 kb
Host smart-300ac028-f78a-406e-b9cd-44ca9450cd09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37473
72043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3747372043
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.139753509
Short name T580
Test name
Test status
Simulation time 343350747 ps
CPU time 12.18 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:08:50 PM PDT 24
Peak memory 254912 kb
Host smart-4867d868-8f79-4c38-92e7-22936f203b51
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139753509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.139753509
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1624145838
Short name T205
Test name
Test status
Simulation time 58894452 ps
CPU time 4.75 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:08:40 PM PDT 24
Peak memory 248920 kb
Host smart-ee3422ef-d5f6-421e-a033-25c3e149643d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1624145838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1624145838
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2379906521
Short name T611
Test name
Test status
Simulation time 173796297574 ps
CPU time 2554.42 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:51:12 PM PDT 24
Peak memory 286828 kb
Host smart-47ca229f-d12c-479d-beab-9cd36044a2f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379906521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2379906521
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.719685677
Short name T420
Test name
Test status
Simulation time 901249510 ps
CPU time 10.95 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:08:39 PM PDT 24
Peak memory 248628 kb
Host smart-014f0d47-ddc5-4ce8-b1d1-289bac2a4ac8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=719685677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.719685677
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.4055981612
Short name T617
Test name
Test status
Simulation time 781584735 ps
CPU time 30.92 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:09:01 PM PDT 24
Peak memory 256500 kb
Host smart-dcb157b8-6e77-40f4-9097-fa8e1290002b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40559
81612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.4055981612
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1163115173
Short name T88
Test name
Test status
Simulation time 3815759557 ps
CPU time 49.99 seconds
Started Jul 17 06:08:25 PM PDT 24
Finished Jul 17 06:09:17 PM PDT 24
Peak memory 248708 kb
Host smart-b94d22fa-ef7f-400a-9280-c1510324f110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11631
15173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1163115173
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3355196466
Short name T4
Test name
Test status
Simulation time 39128022677 ps
CPU time 2374.61 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:48:06 PM PDT 24
Peak memory 287176 kb
Host smart-b9432fb3-fc70-4eff-97ea-5da7c3d30c8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355196466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3355196466
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1131063839
Short name T216
Test name
Test status
Simulation time 147162080756 ps
CPU time 2556.54 seconds
Started Jul 17 06:08:25 PM PDT 24
Finished Jul 17 06:51:02 PM PDT 24
Peak memory 289804 kb
Host smart-46ddea4e-291f-449f-a95f-dc2a4e435fd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131063839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1131063839
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3130705466
Short name T571
Test name
Test status
Simulation time 438078978 ps
CPU time 27.33 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:09:07 PM PDT 24
Peak memory 248620 kb
Host smart-9b3c629e-ea48-4ec4-b226-48929ab8f60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31307
05466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3130705466
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.4071158584
Short name T487
Test name
Test status
Simulation time 111681413 ps
CPU time 7.19 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:08:38 PM PDT 24
Peak memory 251584 kb
Host smart-eb75d785-c5d1-4cd7-9e92-45d5362abaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40711
58584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.4071158584
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3926794870
Short name T680
Test name
Test status
Simulation time 258692221 ps
CPU time 15.85 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:08:52 PM PDT 24
Peak memory 254704 kb
Host smart-39d31b25-313f-417a-b64d-0b3c9e57260c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39267
94870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3926794870
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.948028218
Short name T655
Test name
Test status
Simulation time 206657746392 ps
CPU time 3373.82 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 07:04:45 PM PDT 24
Peak memory 305236 kb
Host smart-0a7b91b9-c287-4415-86ed-11cf27920b55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948028218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.948028218
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.715024768
Short name T198
Test name
Test status
Simulation time 17409663 ps
CPU time 2.49 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:08:48 PM PDT 24
Peak memory 248928 kb
Host smart-fe3c8e09-1ff9-4a9a-b7e8-670f44e2302a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=715024768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.715024768
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2227059437
Short name T502
Test name
Test status
Simulation time 45354314954 ps
CPU time 1054.72 seconds
Started Jul 17 06:08:22 PM PDT 24
Finished Jul 17 06:25:58 PM PDT 24
Peak memory 281612 kb
Host smart-2ca2adae-186b-44c5-86b1-a08a9107cb6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227059437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2227059437
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1228540250
Short name T434
Test name
Test status
Simulation time 625243677 ps
CPU time 27.28 seconds
Started Jul 17 06:08:21 PM PDT 24
Finished Jul 17 06:08:49 PM PDT 24
Peak memory 248644 kb
Host smart-e35f3b35-9f7f-4b7d-832a-33a79d490f64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1228540250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1228540250
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1517788238
Short name T691
Test name
Test status
Simulation time 1954415272 ps
CPU time 106.27 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:10:22 PM PDT 24
Peak memory 257064 kb
Host smart-98794166-01f2-418c-99f1-17c5ffc56827
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15177
88238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1517788238
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.85302039
Short name T347
Test name
Test status
Simulation time 1515875606 ps
CPU time 37.2 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:09:15 PM PDT 24
Peak memory 256812 kb
Host smart-927dfc40-5d23-4603-b3ef-a8634e677bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85302
039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.85302039
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.4030518536
Short name T332
Test name
Test status
Simulation time 21183663288 ps
CPU time 1060.37 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:26:23 PM PDT 24
Peak memory 285460 kb
Host smart-a3d7a692-0f36-4063-9f76-de7f9c1aa85e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030518536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4030518536
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3549256317
Short name T607
Test name
Test status
Simulation time 116922484209 ps
CPU time 1472.39 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:33:19 PM PDT 24
Peak memory 273424 kb
Host smart-4dbf68c1-750e-46cc-a82c-1904b5e13c27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549256317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3549256317
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3618645284
Short name T8
Test name
Test status
Simulation time 5210694771 ps
CPU time 201.68 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:11:59 PM PDT 24
Peak memory 248804 kb
Host smart-7a81ae89-6cdd-4f58-929b-ca83b405484b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618645284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3618645284
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1160443208
Short name T500
Test name
Test status
Simulation time 475439434 ps
CPU time 29.72 seconds
Started Jul 17 06:08:23 PM PDT 24
Finished Jul 17 06:08:53 PM PDT 24
Peak memory 256048 kb
Host smart-0e6c521d-f400-4317-a8d3-6e4779d9a3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11604
43208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1160443208
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1135915821
Short name T457
Test name
Test status
Simulation time 971355846 ps
CPU time 16.89 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:08:47 PM PDT 24
Peak memory 248264 kb
Host smart-708e7462-cfcd-4b1a-b764-60ad317bd89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11359
15821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1135915821
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.600678909
Short name T692
Test name
Test status
Simulation time 533609635 ps
CPU time 14.07 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:08:46 PM PDT 24
Peak memory 248676 kb
Host smart-6ac01286-799d-4259-ad87-39e714c13853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60067
8909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.600678909
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1981413182
Short name T418
Test name
Test status
Simulation time 1879051739 ps
CPU time 55.93 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:09:25 PM PDT 24
Peak memory 249176 kb
Host smart-69e5053a-671a-440b-a5fa-218e666c41be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19814
13182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1981413182
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2772465776
Short name T476
Test name
Test status
Simulation time 16155571201 ps
CPU time 944.08 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:24:18 PM PDT 24
Peak memory 267232 kb
Host smart-e07ac57b-8a4e-4576-b96b-e352dd573132
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772465776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2772465776
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.396801980
Short name T193
Test name
Test status
Simulation time 165171983 ps
CPU time 3.74 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:08:34 PM PDT 24
Peak memory 248896 kb
Host smart-d8d16e34-8d2c-453d-80e8-5bab40891282
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=396801980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.396801980
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3195431048
Short name T448
Test name
Test status
Simulation time 45069986678 ps
CPU time 2456.97 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:49:33 PM PDT 24
Peak memory 285480 kb
Host smart-d894c88a-16d7-446c-9fbe-c199505ce92b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195431048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3195431048
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2707919290
Short name T385
Test name
Test status
Simulation time 382663961 ps
CPU time 11.3 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:08:47 PM PDT 24
Peak memory 248604 kb
Host smart-64fe3a60-0e11-4cfc-8fc1-9df673f728be
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2707919290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2707919290
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.4030901649
Short name T682
Test name
Test status
Simulation time 953262463 ps
CPU time 64.74 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:09:46 PM PDT 24
Peak memory 256464 kb
Host smart-ddfbaaa0-eec0-43fe-89f5-02abc34ff2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40309
01649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.4030901649
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3950775862
Short name T392
Test name
Test status
Simulation time 119310693 ps
CPU time 8.27 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:08:50 PM PDT 24
Peak memory 248736 kb
Host smart-55c5768f-970e-4dd7-acf7-fe427b74e318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39507
75862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3950775862
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2266573058
Short name T591
Test name
Test status
Simulation time 22014477035 ps
CPU time 956.43 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:24:35 PM PDT 24
Peak memory 272780 kb
Host smart-39b96b20-d49e-445e-8ab5-73840fd28531
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266573058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2266573058
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3701511723
Short name T403
Test name
Test status
Simulation time 12946443057 ps
CPU time 977.39 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:24:55 PM PDT 24
Peak memory 282476 kb
Host smart-b90feecb-5804-4533-956d-178669bde2b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701511723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3701511723
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.368376785
Short name T479
Test name
Test status
Simulation time 288131484 ps
CPU time 6.57 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:08:47 PM PDT 24
Peak memory 248636 kb
Host smart-5f27cbb3-123b-466b-9ef7-0a10cd23d9d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36837
6785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.368376785
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.4279105800
Short name T386
Test name
Test status
Simulation time 452880094 ps
CPU time 26.72 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:09:05 PM PDT 24
Peak memory 255352 kb
Host smart-50f70210-c4d8-4b3a-95a2-bc35620d6c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42791
05800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4279105800
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3463151841
Short name T3
Test name
Test status
Simulation time 772004183 ps
CPU time 18.66 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:08:57 PM PDT 24
Peak memory 256048 kb
Host smart-6f9c44ad-6cde-467c-8169-77215ac3f7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34631
51841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3463151841
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.990608257
Short name T341
Test name
Test status
Simulation time 53824838 ps
CPU time 6.62 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:39 PM PDT 24
Peak memory 254828 kb
Host smart-06097f9c-3c20-42ea-a265-761c66b36d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99060
8257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.990608257
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.379140328
Short name T459
Test name
Test status
Simulation time 58799472232 ps
CPU time 3134.5 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 07:00:46 PM PDT 24
Peak memory 298844 kb
Host smart-4a0640e9-3ef6-4b1b-9ea0-1656471edc31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379140328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.379140328
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2668928964
Short name T201
Test name
Test status
Simulation time 164832677 ps
CPU time 3.76 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:08:44 PM PDT 24
Peak memory 248912 kb
Host smart-87d1298d-8e91-424a-a3d8-b7bd1b06eeb4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2668928964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2668928964
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2975701486
Short name T97
Test name
Test status
Simulation time 14441503392 ps
CPU time 501.98 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:16:54 PM PDT 24
Peak memory 272528 kb
Host smart-0a464004-ec5f-46ec-b10f-6957b556cf9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975701486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2975701486
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1224148946
Short name T493
Test name
Test status
Simulation time 436642404 ps
CPU time 6.74 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:41 PM PDT 24
Peak memory 248704 kb
Host smart-6fa334f2-8459-4ed5-a276-a796164a2868
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1224148946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1224148946
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.669338924
Short name T257
Test name
Test status
Simulation time 2704519243 ps
CPU time 108.86 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:10:18 PM PDT 24
Peak memory 256780 kb
Host smart-711b8509-bc7a-4800-86b0-3677588682d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66933
8924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.669338924
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.875586361
Short name T699
Test name
Test status
Simulation time 244253443 ps
CPU time 16.46 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:09:00 PM PDT 24
Peak memory 254732 kb
Host smart-4fc88644-c23f-4e9a-9125-2c19a221434f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87558
6361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.875586361
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.93364770
Short name T642
Test name
Test status
Simulation time 41168781656 ps
CPU time 758 seconds
Started Jul 17 06:08:38 PM PDT 24
Finished Jul 17 06:21:26 PM PDT 24
Peak memory 265228 kb
Host smart-848005b3-b502-4a23-812e-e8c5ddc975a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93364770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.93364770
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1625473095
Short name T707
Test name
Test status
Simulation time 86396268259 ps
CPU time 1514.85 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:34:00 PM PDT 24
Peak memory 271280 kb
Host smart-dc63b414-9932-4729-9394-b9f3e8ecc1f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625473095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1625473095
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3503905561
Short name T477
Test name
Test status
Simulation time 159486709 ps
CPU time 3.68 seconds
Started Jul 17 06:08:58 PM PDT 24
Finished Jul 17 06:09:03 PM PDT 24
Peak memory 240464 kb
Host smart-a5c1fb00-bf78-48d4-94a1-27fbf8e7638c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35039
05561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3503905561
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1119472711
Short name T442
Test name
Test status
Simulation time 447392087 ps
CPU time 12.48 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:08:49 PM PDT 24
Peak memory 253204 kb
Host smart-aa87218e-2c1f-4710-922f-0aa2ffaf7abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11194
72711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1119472711
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3254150468
Short name T117
Test name
Test status
Simulation time 485363113 ps
CPU time 16.48 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:09:07 PM PDT 24
Peak memory 248188 kb
Host smart-8a84bd41-e9e7-409e-8f22-46f76697dab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32541
50468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3254150468
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1044129803
Short name T497
Test name
Test status
Simulation time 129663552 ps
CPU time 9.17 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:08:56 PM PDT 24
Peak memory 254516 kb
Host smart-b4e36fd9-bf98-4608-a320-7cb49c0972c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10441
29803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1044129803
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3720919271
Short name T192
Test name
Test status
Simulation time 131917759 ps
CPU time 2.35 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:08:41 PM PDT 24
Peak memory 248876 kb
Host smart-9ad21ffb-e359-463f-9174-04ffc5b33828
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3720919271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3720919271
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2416292326
Short name T566
Test name
Test status
Simulation time 4437530063 ps
CPU time 11.39 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:45 PM PDT 24
Peak memory 248700 kb
Host smart-7a97b7a9-8e31-4ccf-9f33-6285c0f2b5e5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2416292326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2416292326
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1307438177
Short name T498
Test name
Test status
Simulation time 1520889116 ps
CPU time 56.62 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:09:29 PM PDT 24
Peak memory 256484 kb
Host smart-1cbe79f2-2f77-4a92-8c66-a120ca30d751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13074
38177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1307438177
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2174778229
Short name T443
Test name
Test status
Simulation time 3406993299 ps
CPU time 56.08 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:09:28 PM PDT 24
Peak memory 256596 kb
Host smart-71a0fde1-c43a-495d-9f1c-c7968673056d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21747
78229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2174778229
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.388584609
Short name T315
Test name
Test status
Simulation time 33248370822 ps
CPU time 687.3 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:20:14 PM PDT 24
Peak memory 270640 kb
Host smart-8cc1195d-4a38-445b-af42-7e2f6a7ea480
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388584609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.388584609
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2621308804
Short name T276
Test name
Test status
Simulation time 446055224483 ps
CPU time 2529.74 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:50:44 PM PDT 24
Peak memory 282236 kb
Host smart-214a80e3-69e1-4fb5-b17d-af843068cb22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621308804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2621308804
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.122831928
Short name T219
Test name
Test status
Simulation time 17745939615 ps
CPU time 96.61 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:10:08 PM PDT 24
Peak memory 248804 kb
Host smart-4ec3df85-8c93-4c62-8a12-1582a1b4049a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122831928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.122831928
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3543983858
Short name T463
Test name
Test status
Simulation time 1639730631 ps
CPU time 61.98 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:09:34 PM PDT 24
Peak memory 255988 kb
Host smart-c0b295a8-ae6e-4d92-83c1-a1c3f9eff288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35439
83858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3543983858
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.314722944
Short name T361
Test name
Test status
Simulation time 161880383 ps
CPU time 4.53 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:08:45 PM PDT 24
Peak memory 240436 kb
Host smart-11df4df9-8ffa-403e-b076-d7c0ede70224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31472
2944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.314722944
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2764165871
Short name T544
Test name
Test status
Simulation time 359788578 ps
CPU time 11.39 seconds
Started Jul 17 06:08:39 PM PDT 24
Finished Jul 17 06:09:00 PM PDT 24
Peak memory 255940 kb
Host smart-4ca925a3-d7e4-4908-a0a2-52f0350053cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27641
65871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2764165871
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3894044119
Short name T630
Test name
Test status
Simulation time 1210909382 ps
CPU time 20.05 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:09:07 PM PDT 24
Peak memory 256792 kb
Host smart-47c16f40-54dd-4801-8752-3b2da9ab8a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38940
44119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3894044119
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2454584650
Short name T95
Test name
Test status
Simulation time 90793684789 ps
CPU time 1511.01 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:33:53 PM PDT 24
Peak memory 289432 kb
Host smart-2119fa02-40e0-4ec6-a87b-e0abba1ca02d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454584650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2454584650
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.153316235
Short name T69
Test name
Test status
Simulation time 69015971 ps
CPU time 2.66 seconds
Started Jul 17 06:07:59 PM PDT 24
Finished Jul 17 06:08:03 PM PDT 24
Peak memory 248808 kb
Host smart-571bbb9b-0132-4aaa-b9c8-3502562c890a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=153316235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.153316235
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2353906384
Short name T75
Test name
Test status
Simulation time 40772035589 ps
CPU time 2371.83 seconds
Started Jul 17 06:08:16 PM PDT 24
Finished Jul 17 06:47:49 PM PDT 24
Peak memory 288784 kb
Host smart-8b996522-28bf-426d-898a-5a0c245fbb01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353906384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2353906384
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2280371422
Short name T556
Test name
Test status
Simulation time 307308466 ps
CPU time 8.47 seconds
Started Jul 17 06:07:47 PM PDT 24
Finished Jul 17 06:08:02 PM PDT 24
Peak memory 248652 kb
Host smart-022633ba-fafa-4cb6-b62d-08369896c778
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2280371422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2280371422
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2678413266
Short name T461
Test name
Test status
Simulation time 1314561096 ps
CPU time 117.07 seconds
Started Jul 17 06:07:47 PM PDT 24
Finished Jul 17 06:09:50 PM PDT 24
Peak memory 256400 kb
Host smart-ed86bd4c-ef66-42c9-98e8-81faa20e7235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26784
13266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2678413266
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.477599833
Short name T490
Test name
Test status
Simulation time 1652390265 ps
CPU time 28.49 seconds
Started Jul 17 06:07:47 PM PDT 24
Finished Jul 17 06:08:29 PM PDT 24
Peak memory 256848 kb
Host smart-48b35577-d2d4-4089-86f5-1f8e3a2165bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47759
9833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.477599833
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.4131331059
Short name T321
Test name
Test status
Simulation time 123811645063 ps
CPU time 2110.06 seconds
Started Jul 17 06:07:48 PM PDT 24
Finished Jul 17 06:43:04 PM PDT 24
Peak memory 289712 kb
Host smart-8ba95d05-297f-434a-bb86-05c1a1dbd2da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131331059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.4131331059
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2928546497
Short name T610
Test name
Test status
Simulation time 50469625688 ps
CPU time 1094.17 seconds
Started Jul 17 06:08:17 PM PDT 24
Finished Jul 17 06:26:33 PM PDT 24
Peak memory 271364 kb
Host smart-36256539-313c-4291-b49d-77e73c910a52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928546497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2928546497
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4044368121
Short name T9
Test name
Test status
Simulation time 16349488316 ps
CPU time 173.55 seconds
Started Jul 17 06:07:44 PM PDT 24
Finished Jul 17 06:10:43 PM PDT 24
Peak memory 256216 kb
Host smart-4150a6ac-dfe3-4552-b1d7-658043d2c763
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044368121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4044368121
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2526365128
Short name T277
Test name
Test status
Simulation time 443938938 ps
CPU time 18.43 seconds
Started Jul 17 06:07:49 PM PDT 24
Finished Jul 17 06:08:13 PM PDT 24
Peak memory 248640 kb
Host smart-86bf2d2e-33d8-48cb-aa7a-80eb465eddc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25263
65128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2526365128
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1215340014
Short name T480
Test name
Test status
Simulation time 861858524 ps
CPU time 53.21 seconds
Started Jul 17 06:07:49 PM PDT 24
Finished Jul 17 06:08:47 PM PDT 24
Peak memory 256192 kb
Host smart-f2677871-99f1-42b3-9e61-c8fb4d06b82e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12153
40014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1215340014
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3917599820
Short name T11
Test name
Test status
Simulation time 5180671842 ps
CPU time 193.21 seconds
Started Jul 17 06:07:48 PM PDT 24
Finished Jul 17 06:11:07 PM PDT 24
Peak memory 278720 kb
Host smart-d10e0fde-a9a1-431b-b8fc-03f46b869e7a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3917599820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3917599820
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1609284898
Short name T401
Test name
Test status
Simulation time 4586285745 ps
CPU time 67.5 seconds
Started Jul 17 06:07:47 PM PDT 24
Finished Jul 17 06:09:01 PM PDT 24
Peak memory 248784 kb
Host smart-23784ac9-272e-4515-856a-d021fd7fd9df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16092
84898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1609284898
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3856448874
Short name T355
Test name
Test status
Simulation time 1497119995 ps
CPU time 22.26 seconds
Started Jul 17 06:08:15 PM PDT 24
Finished Jul 17 06:08:37 PM PDT 24
Peak memory 256356 kb
Host smart-be779d1c-86ec-4b29-9252-072ab7940a80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38564
48874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3856448874
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.4138911685
Short name T247
Test name
Test status
Simulation time 193778445781 ps
CPU time 3089.91 seconds
Started Jul 17 06:07:46 PM PDT 24
Finished Jul 17 06:59:22 PM PDT 24
Peak memory 302832 kb
Host smart-59fd3384-87fd-4dc2-9a21-a7700d543d4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138911685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.4138911685
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2271201651
Short name T182
Test name
Test status
Simulation time 81075048535 ps
CPU time 7275.51 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 08:09:16 PM PDT 24
Peak memory 394636 kb
Host smart-7901e9b8-b0a6-433f-96f5-5d54c1d272ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271201651 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2271201651
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.430065185
Short name T501
Test name
Test status
Simulation time 52493059397 ps
CPU time 1213.64 seconds
Started Jul 17 06:08:41 PM PDT 24
Finished Jul 17 06:29:04 PM PDT 24
Peak memory 285348 kb
Host smart-de3a5dd5-072b-4d9e-9676-c306deb36705
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430065185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.430065185
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2007447327
Short name T592
Test name
Test status
Simulation time 6038574735 ps
CPU time 78.05 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:09:58 PM PDT 24
Peak memory 249764 kb
Host smart-8334e46b-c7c5-4a2f-b707-ed1b7670c773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20074
47327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2007447327
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.601312686
Short name T35
Test name
Test status
Simulation time 966068536 ps
CPU time 52.71 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:09:39 PM PDT 24
Peak memory 248716 kb
Host smart-fb0331e0-922b-4157-9d97-2b8e29c76a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60131
2686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.601312686
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.435644304
Short name T643
Test name
Test status
Simulation time 33773211619 ps
CPU time 765.69 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:21:17 PM PDT 24
Peak memory 265192 kb
Host smart-1d9f3f0d-62b0-4828-97e7-997caf90a653
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435644304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.435644304
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2317819463
Short name T515
Test name
Test status
Simulation time 98760276911 ps
CPU time 1672.24 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:36:36 PM PDT 24
Peak memory 273392 kb
Host smart-8afd8c94-f175-41b8-8570-528f119c9671
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317819463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2317819463
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.795056781
Short name T704
Test name
Test status
Simulation time 57563445269 ps
CPU time 433.03 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:15:47 PM PDT 24
Peak memory 248648 kb
Host smart-769e32bb-e734-42ac-a06f-7805e65ccae6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795056781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.795056781
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1663834669
Short name T393
Test name
Test status
Simulation time 847444132 ps
CPU time 53.12 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:09:35 PM PDT 24
Peak memory 256104 kb
Host smart-fddac324-d78e-46c9-b556-4d3ff8d93b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16638
34669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1663834669
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1140635058
Short name T229
Test name
Test status
Simulation time 569517514 ps
CPU time 24.65 seconds
Started Jul 17 06:08:39 PM PDT 24
Finished Jul 17 06:09:13 PM PDT 24
Peak memory 248640 kb
Host smart-d5a1f494-df5b-45f3-bf58-0bc00b405fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11406
35058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1140635058
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2982704900
Short name T350
Test name
Test status
Simulation time 141602060 ps
CPU time 15.78 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:08:48 PM PDT 24
Peak memory 256256 kb
Host smart-82174585-bcff-4a05-84fc-5c92329543cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29827
04900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2982704900
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.266795777
Short name T473
Test name
Test status
Simulation time 433339887 ps
CPU time 32.31 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:09:17 PM PDT 24
Peak memory 249068 kb
Host smart-1f4a542b-a0a2-49a7-a7c5-f2c8f295757d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26679
5777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.266795777
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2233206635
Short name T261
Test name
Test status
Simulation time 11377365739 ps
CPU time 869.36 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:23:09 PM PDT 24
Peak memory 289184 kb
Host smart-4763fbb5-7b8a-46ae-9598-dfa4356d4594
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233206635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2233206635
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2465804443
Short name T485
Test name
Test status
Simulation time 85572548972 ps
CPU time 2242.96 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:46:10 PM PDT 24
Peak memory 305760 kb
Host smart-3fd346a3-9585-45ca-b1b5-41e34f96a692
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465804443 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2465804443
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1122378716
Short name T218
Test name
Test status
Simulation time 183136844347 ps
CPU time 2261 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:46:23 PM PDT 24
Peak memory 288864 kb
Host smart-c2eb8eab-d26f-4eef-8de1-837da4bc9b68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122378716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1122378716
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.401699561
Short name T379
Test name
Test status
Simulation time 5595988206 ps
CPU time 302.69 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:13:48 PM PDT 24
Peak memory 256304 kb
Host smart-9089174a-6346-4ef8-9a58-b6269b0f24c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40169
9561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.401699561
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.919893167
Short name T415
Test name
Test status
Simulation time 387711887 ps
CPU time 32.84 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:09:14 PM PDT 24
Peak memory 256480 kb
Host smart-a7d6f845-ca54-4708-b823-4946e0e19925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91989
3167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.919893167
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2647381442
Short name T327
Test name
Test status
Simulation time 17482494744 ps
CPU time 1361.93 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:31:28 PM PDT 24
Peak memory 288976 kb
Host smart-74429f3b-2447-407e-8db7-b8f3f01e1195
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647381442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2647381442
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1932624867
Short name T345
Test name
Test status
Simulation time 44318015325 ps
CPU time 821.7 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:22:28 PM PDT 24
Peak memory 268244 kb
Host smart-df983c21-99ff-4021-859b-7f2c01c0d6c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932624867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1932624867
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2207467395
Short name T293
Test name
Test status
Simulation time 13714209364 ps
CPU time 133.6 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:10:54 PM PDT 24
Peak memory 248784 kb
Host smart-881227c8-9a0a-4665-bfd3-b35228aecb53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207467395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2207467395
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3251204132
Short name T462
Test name
Test status
Simulation time 342184528 ps
CPU time 29.91 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:09:15 PM PDT 24
Peak memory 248664 kb
Host smart-b0b8f5de-627a-446f-bee0-434be93f89ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32512
04132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3251204132
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1530867829
Short name T522
Test name
Test status
Simulation time 600495086 ps
CPU time 11.28 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:08:57 PM PDT 24
Peak memory 248728 kb
Host smart-c0e9d213-697c-4843-bd9b-c2407769ca1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15308
67829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1530867829
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1108234396
Short name T609
Test name
Test status
Simulation time 672855073 ps
CPU time 9.18 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:08:51 PM PDT 24
Peak memory 254956 kb
Host smart-f1ce107c-764d-4de7-bb68-395bcc1a9613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11082
34396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1108234396
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1548998068
Short name T677
Test name
Test status
Simulation time 1167914096 ps
CPU time 16.5 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:08:48 PM PDT 24
Peak memory 249008 kb
Host smart-7a763833-c710-429c-9aa0-db88359c8f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15489
98068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1548998068
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1016640920
Short name T703
Test name
Test status
Simulation time 34517487911 ps
CPU time 1377.72 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:31:40 PM PDT 24
Peak memory 289572 kb
Host smart-b48a1b06-a32c-41fa-8c87-99e9e2c49b43
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016640920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1016640920
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1086035536
Short name T360
Test name
Test status
Simulation time 45219933280 ps
CPU time 869.14 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:23:05 PM PDT 24
Peak memory 272556 kb
Host smart-f70b2cc7-c6e0-47ff-9337-6a88a3d0a015
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086035536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1086035536
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2043574576
Short name T540
Test name
Test status
Simulation time 1049086425 ps
CPU time 99.29 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:10:25 PM PDT 24
Peak memory 256172 kb
Host smart-6df934d1-989d-40e9-8444-5627264b822a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20435
74576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2043574576
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4061563940
Short name T381
Test name
Test status
Simulation time 639207343 ps
CPU time 11.56 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:08:55 PM PDT 24
Peak memory 255804 kb
Host smart-e9f0175e-95c2-440d-a51c-f932cadda204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40615
63940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4061563940
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3618805159
Short name T284
Test name
Test status
Simulation time 36782903005 ps
CPU time 2384.89 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:48:23 PM PDT 24
Peak memory 288088 kb
Host smart-3997c5d0-36be-4a98-871c-b00118ac7b04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618805159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3618805159
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.498689875
Short name T690
Test name
Test status
Simulation time 19552783379 ps
CPU time 1072.93 seconds
Started Jul 17 06:08:39 PM PDT 24
Finished Jul 17 06:26:42 PM PDT 24
Peak memory 289380 kb
Host smart-094f0470-a410-430b-9112-07c993fc511f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498689875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.498689875
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3186622957
Short name T647
Test name
Test status
Simulation time 6546012667 ps
CPU time 260.34 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:12:55 PM PDT 24
Peak memory 255464 kb
Host smart-1f1cd178-99e9-4147-9487-34562839ecab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186622957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3186622957
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3894087478
Short name T641
Test name
Test status
Simulation time 276919815 ps
CPU time 19.62 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:09:06 PM PDT 24
Peak memory 255972 kb
Host smart-e3c470cd-6884-4194-94b0-0fb762b668a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38940
87478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3894087478
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3198888108
Short name T701
Test name
Test status
Simulation time 141255445 ps
CPU time 15.05 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:08:55 PM PDT 24
Peak memory 256704 kb
Host smart-c22838d9-1691-4fb5-8fcd-f066f59aa464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31988
88108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3198888108
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.4177987075
Short name T656
Test name
Test status
Simulation time 128514093 ps
CPU time 15.69 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:08:58 PM PDT 24
Peak memory 247968 kb
Host smart-30c82471-3dc3-4b1e-95c9-17c18793a371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41779
87075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4177987075
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4039667935
Short name T584
Test name
Test status
Simulation time 198236348 ps
CPU time 13.75 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:47 PM PDT 24
Peak memory 254728 kb
Host smart-c711abd9-7534-4f0c-a67d-c9622ea916ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40396
67935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4039667935
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1209901630
Short name T581
Test name
Test status
Simulation time 127054768519 ps
CPU time 1999.83 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:42:02 PM PDT 24
Peak memory 289084 kb
Host smart-639c6ca0-0d84-4ff5-b98e-571d5fd5dc4e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209901630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1209901630
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.535406445
Short name T595
Test name
Test status
Simulation time 7485065807 ps
CPU time 740.2 seconds
Started Jul 17 06:09:02 PM PDT 24
Finished Jul 17 06:21:24 PM PDT 24
Peak memory 270404 kb
Host smart-ea40d9ef-2973-4345-943b-167969a24644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535406445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.535406445
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1288134554
Short name T390
Test name
Test status
Simulation time 325035372 ps
CPU time 11.11 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:08:56 PM PDT 24
Peak memory 253672 kb
Host smart-072ddaf0-1dd3-4cfc-a4e8-c17c47eb85ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12881
34554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1288134554
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3078129312
Short name T76
Test name
Test status
Simulation time 1293378968 ps
CPU time 26.12 seconds
Started Jul 17 06:08:59 PM PDT 24
Finished Jul 17 06:09:26 PM PDT 24
Peak memory 248600 kb
Host smart-c5d34e9c-0433-4954-9516-5fca5e0c1bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30781
29312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3078129312
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1008984244
Short name T328
Test name
Test status
Simulation time 214148942652 ps
CPU time 2938.02 seconds
Started Jul 17 06:08:38 PM PDT 24
Finished Jul 17 06:57:46 PM PDT 24
Peak memory 287356 kb
Host smart-ed075053-8db8-4a48-b2e9-9f6d1aca1f6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008984244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1008984244
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.720920268
Short name T391
Test name
Test status
Simulation time 19691291356 ps
CPU time 1057.93 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:26:20 PM PDT 24
Peak memory 288776 kb
Host smart-f41a9582-4a6a-4228-a2a6-11b29f61af30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720920268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.720920268
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3381386558
Short name T288
Test name
Test status
Simulation time 10616781613 ps
CPU time 223.54 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:12:26 PM PDT 24
Peak memory 248768 kb
Host smart-01528760-f60a-4fc2-8b10-eaaa197477ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381386558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3381386558
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.400338006
Short name T524
Test name
Test status
Simulation time 294393305 ps
CPU time 10.45 seconds
Started Jul 17 06:08:44 PM PDT 24
Finished Jul 17 06:09:02 PM PDT 24
Peak memory 253336 kb
Host smart-9adff40b-02a1-4f02-b882-7801ae080e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033
8006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.400338006
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3347845340
Short name T375
Test name
Test status
Simulation time 206534607 ps
CPU time 16.74 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:08:51 PM PDT 24
Peak memory 256232 kb
Host smart-12ca3d3b-c330-4379-be8f-e8322f642842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33478
45340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3347845340
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.452905644
Short name T491
Test name
Test status
Simulation time 734750321 ps
CPU time 45.22 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:09:20 PM PDT 24
Peak memory 248620 kb
Host smart-9e2edc5c-91eb-483f-a4b6-741c0b81b9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45290
5644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.452905644
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2671747745
Short name T693
Test name
Test status
Simulation time 1072061969 ps
CPU time 17.09 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:08:55 PM PDT 24
Peak memory 248568 kb
Host smart-d3921ca9-681f-4e53-b8e2-ff4d40669808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26717
47745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2671747745
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2403919421
Short name T426
Test name
Test status
Simulation time 42850014286 ps
CPU time 2405.34 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:48:46 PM PDT 24
Peak memory 289528 kb
Host smart-f819bcea-dd55-45fc-88e1-3da8cb8cdc02
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403919421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2403919421
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2377913368
Short name T636
Test name
Test status
Simulation time 79241733691 ps
CPU time 1314.64 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:30:37 PM PDT 24
Peak memory 289484 kb
Host smart-9de90ea6-9df0-4e69-b89f-fc5a54868f0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377913368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2377913368
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2677433854
Short name T653
Test name
Test status
Simulation time 116590927 ps
CPU time 4.99 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:08:49 PM PDT 24
Peak memory 251536 kb
Host smart-73a323cc-553b-4ea6-8d41-2552c93f923b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26774
33854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2677433854
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3348379887
Short name T685
Test name
Test status
Simulation time 489368868 ps
CPU time 27.63 seconds
Started Jul 17 06:08:59 PM PDT 24
Finished Jul 17 06:09:27 PM PDT 24
Peak memory 255268 kb
Host smart-5f70902d-c608-4b2e-9195-959852714e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33483
79887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3348379887
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1297893340
Short name T631
Test name
Test status
Simulation time 14616691940 ps
CPU time 1571.59 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:34:59 PM PDT 24
Peak memory 289072 kb
Host smart-71bb8a5d-ae57-4c5f-aa16-d3cb5eab1c84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297893340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1297893340
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1415003344
Short name T106
Test name
Test status
Simulation time 71523135213 ps
CPU time 2563.42 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:51:24 PM PDT 24
Peak memory 287812 kb
Host smart-ada7655b-64c0-4b1a-982e-88d26cb79d2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415003344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1415003344
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1921676797
Short name T577
Test name
Test status
Simulation time 43791912817 ps
CPU time 454.17 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:16:06 PM PDT 24
Peak memory 248800 kb
Host smart-bb750964-31fa-4497-9ea6-64cf4a9816eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921676797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1921676797
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1728789768
Short name T436
Test name
Test status
Simulation time 2280029507 ps
CPU time 21.14 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:09:06 PM PDT 24
Peak memory 255404 kb
Host smart-84f76bba-adee-4247-82ac-f5059608961c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17287
89768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1728789768
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3336062182
Short name T456
Test name
Test status
Simulation time 1006935358 ps
CPU time 11.04 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:08:58 PM PDT 24
Peak memory 253216 kb
Host smart-05417f6e-85a6-4cad-9d08-34c975d3f89e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33360
62182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3336062182
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3825497558
Short name T244
Test name
Test status
Simulation time 973507206 ps
CPU time 33.6 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:09:17 PM PDT 24
Peak memory 255736 kb
Host smart-6e46a796-73c1-4cfd-bf97-8aa62691f42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38254
97558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3825497558
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2880938841
Short name T570
Test name
Test status
Simulation time 546652836 ps
CPU time 35.17 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:09:17 PM PDT 24
Peak memory 256740 kb
Host smart-ba772e3e-7218-432b-85f7-bec910bb3155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28809
38841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2880938841
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.432350390
Short name T474
Test name
Test status
Simulation time 111132737760 ps
CPU time 5093.54 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 07:33:41 PM PDT 24
Peak memory 355216 kb
Host smart-73e0ec32-3b34-4f9b-baa5-69e44d0f449e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432350390 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.432350390
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3878654863
Short name T583
Test name
Test status
Simulation time 44225673614 ps
CPU time 2383.03 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:48:22 PM PDT 24
Peak memory 289228 kb
Host smart-ff5bc8b6-1296-48d3-a352-a5d6c53e5208
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878654863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3878654863
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2017069288
Short name T68
Test name
Test status
Simulation time 16218429035 ps
CPU time 218.24 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:12:22 PM PDT 24
Peak memory 256300 kb
Host smart-e4356895-f1e5-4212-93a7-fb3519d95461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20170
69288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2017069288
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3345924488
Short name T635
Test name
Test status
Simulation time 4295151465 ps
CPU time 59.97 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:09:33 PM PDT 24
Peak memory 248780 kb
Host smart-e300c560-88eb-421e-a701-c3ed6cbbfa87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33459
24488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3345924488
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.955095814
Short name T314
Test name
Test status
Simulation time 30014226055 ps
CPU time 1709.95 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:37:09 PM PDT 24
Peak memory 272824 kb
Host smart-37d478f5-3bff-4db9-85e4-e68cd65e95a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955095814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.955095814
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1643226541
Short name T455
Test name
Test status
Simulation time 17532607755 ps
CPU time 1029.07 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:25:51 PM PDT 24
Peak memory 286340 kb
Host smart-85a7b21d-a558-4d3c-92ce-14c4336ed3a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643226541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1643226541
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.459092156
Short name T626
Test name
Test status
Simulation time 6143249470 ps
CPU time 187.47 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:11:51 PM PDT 24
Peak memory 248812 kb
Host smart-9157cca3-7bb0-4237-9ae6-46fcf6149c3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459092156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.459092156
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2105158176
Short name T39
Test name
Test status
Simulation time 437229807 ps
CPU time 42.52 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:09:23 PM PDT 24
Peak memory 248704 kb
Host smart-f35f2c64-8efd-4ed6-9056-c63481cd5177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21051
58176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2105158176
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3231175861
Short name T446
Test name
Test status
Simulation time 538634585 ps
CPU time 12.64 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:45 PM PDT 24
Peak memory 247968 kb
Host smart-0d0c781c-613d-47fc-8329-15ba3ace245e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32311
75861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3231175861
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3265016856
Short name T545
Test name
Test status
Simulation time 828745345 ps
CPU time 49.5 seconds
Started Jul 17 06:08:33 PM PDT 24
Finished Jul 17 06:09:30 PM PDT 24
Peak memory 248288 kb
Host smart-96d7b72e-539a-47ba-9f1f-4c3858a807c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32650
16856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3265016856
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.333821120
Short name T509
Test name
Test status
Simulation time 1469454881 ps
CPU time 27.89 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:09:13 PM PDT 24
Peak memory 256872 kb
Host smart-a01c24e6-5fa1-4ab4-9a88-c3e6935d8926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33382
1120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.333821120
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3297685793
Short name T272
Test name
Test status
Simulation time 39619825818 ps
CPU time 596.05 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:18:41 PM PDT 24
Peak memory 265148 kb
Host smart-7eea701c-f1b5-4ca8-8d25-05856c7a3835
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297685793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3297685793
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1024915618
Short name T90
Test name
Test status
Simulation time 26460817694 ps
CPU time 1212.56 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:28:50 PM PDT 24
Peak memory 289000 kb
Host smart-59a61933-23f0-42ae-aa21-032fe2cea1ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024915618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1024915618
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2558013438
Short name T521
Test name
Test status
Simulation time 14654814879 ps
CPU time 221.26 seconds
Started Jul 17 06:08:40 PM PDT 24
Finished Jul 17 06:12:30 PM PDT 24
Peak memory 256492 kb
Host smart-c8ad4d5a-56a1-4009-aff7-dcd64510d8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25580
13438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2558013438
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1314646456
Short name T696
Test name
Test status
Simulation time 1429520359 ps
CPU time 34.78 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:09:22 PM PDT 24
Peak memory 256888 kb
Host smart-d47acf71-1bbb-484b-8858-1addddef5254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13146
46456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1314646456
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.762038351
Short name T331
Test name
Test status
Simulation time 132241007981 ps
CPU time 1853.8 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:39:32 PM PDT 24
Peak memory 273320 kb
Host smart-87f57a7c-a0e2-49d0-bfd6-5e27cb772293
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762038351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.762038351
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.322336700
Short name T220
Test name
Test status
Simulation time 40684242577 ps
CPU time 2510.92 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:50:25 PM PDT 24
Peak memory 289072 kb
Host smart-50035146-e47b-4b27-81cc-eb8c9a8ad6f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322336700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.322336700
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1848966031
Short name T294
Test name
Test status
Simulation time 70741130952 ps
CPU time 381.46 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:14:56 PM PDT 24
Peak memory 248676 kb
Host smart-5e8c289c-c478-4ae6-bb12-2e8bd15f6fd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848966031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1848966031
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.848356185
Short name T507
Test name
Test status
Simulation time 212831941 ps
CPU time 16.53 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:08:51 PM PDT 24
Peak memory 256524 kb
Host smart-7192ff30-c8b2-4f00-9873-4c9a2399b3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84835
6185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.848356185
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3826514499
Short name T624
Test name
Test status
Simulation time 575714092 ps
CPU time 8.89 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:42 PM PDT 24
Peak memory 248240 kb
Host smart-82f9864d-ea1e-4d8e-a249-80cde0c6d28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38265
14499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3826514499
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1159187522
Short name T513
Test name
Test status
Simulation time 1254738759 ps
CPU time 29.53 seconds
Started Jul 17 06:08:31 PM PDT 24
Finished Jul 17 06:09:07 PM PDT 24
Peak memory 256864 kb
Host smart-0f660dcc-c5e6-4201-8d01-e56f7b18d817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11591
87522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1159187522
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.4231330936
Short name T531
Test name
Test status
Simulation time 11990819464 ps
CPU time 1252.25 seconds
Started Jul 17 06:08:40 PM PDT 24
Finished Jul 17 06:29:41 PM PDT 24
Peak memory 281496 kb
Host smart-ef11a7e1-0543-4f0c-b8b0-1385ecaccaff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231330936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.4231330936
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.809247618
Short name T223
Test name
Test status
Simulation time 179109898227 ps
CPU time 2570.75 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:51:37 PM PDT 24
Peak memory 281040 kb
Host smart-0ee0af5c-931e-4f08-b611-76b8bd272a93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809247618 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.809247618
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.445051784
Short name T560
Test name
Test status
Simulation time 78095859315 ps
CPU time 2304.05 seconds
Started Jul 17 06:09:03 PM PDT 24
Finished Jul 17 06:47:29 PM PDT 24
Peak memory 289128 kb
Host smart-ba563092-b705-4558-9fc3-e1dd2a5be39f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445051784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.445051784
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.143368718
Short name T38
Test name
Test status
Simulation time 4628512343 ps
CPU time 95.84 seconds
Started Jul 17 06:08:40 PM PDT 24
Finished Jul 17 06:10:25 PM PDT 24
Peak memory 256896 kb
Host smart-92c81f6e-ea72-4c03-90f0-8ad0209fa0af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14336
8718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.143368718
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1420604315
Short name T672
Test name
Test status
Simulation time 3184566659 ps
CPU time 49.11 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:09:33 PM PDT 24
Peak memory 248808 kb
Host smart-40c2e8df-b964-4d73-8889-92c229b95415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14206
04315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1420604315
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1305094823
Short name T645
Test name
Test status
Simulation time 20254294246 ps
CPU time 923.84 seconds
Started Jul 17 06:08:48 PM PDT 24
Finished Jul 17 06:24:19 PM PDT 24
Peak memory 273184 kb
Host smart-2b9bee34-8f48-4c22-a982-68d15946d1e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305094823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1305094823
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1947293384
Short name T589
Test name
Test status
Simulation time 160285145722 ps
CPU time 2762.11 seconds
Started Jul 17 06:08:38 PM PDT 24
Finished Jul 17 06:54:50 PM PDT 24
Peak memory 289776 kb
Host smart-ef875116-450c-4acb-b9ce-de16e8abf396
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947293384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1947293384
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.648239639
Short name T307
Test name
Test status
Simulation time 32162502747 ps
CPU time 244.75 seconds
Started Jul 17 06:08:43 PM PDT 24
Finished Jul 17 06:12:56 PM PDT 24
Peak memory 248828 kb
Host smart-a045da01-33da-4d2d-ace5-97f9b1a971c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648239639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.648239639
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1651146906
Short name T667
Test name
Test status
Simulation time 219163617 ps
CPU time 7.37 seconds
Started Jul 17 06:08:41 PM PDT 24
Finished Jul 17 06:08:57 PM PDT 24
Peak memory 248708 kb
Host smart-3daf6b25-2ca8-43fc-b80d-aa9617a70f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16511
46906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1651146906
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.942759571
Short name T421
Test name
Test status
Simulation time 775943633 ps
CPU time 44.51 seconds
Started Jul 17 06:08:39 PM PDT 24
Finished Jul 17 06:09:33 PM PDT 24
Peak memory 247836 kb
Host smart-4d6dc998-5b87-41c6-9a8e-f759a37ebc87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94275
9571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.942759571
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.1093255844
Short name T486
Test name
Test status
Simulation time 171369681 ps
CPU time 10.94 seconds
Started Jul 17 06:09:02 PM PDT 24
Finished Jul 17 06:09:15 PM PDT 24
Peak memory 254148 kb
Host smart-107337cb-995a-4a33-8231-792e611a39e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10932
55844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.1093255844
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.787492921
Short name T705
Test name
Test status
Simulation time 16753022 ps
CPU time 2.84 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:08:47 PM PDT 24
Peak memory 250548 kb
Host smart-f73da07d-2a20-40a3-a52b-234683f2374e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78749
2921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.787492921
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1485478535
Short name T268
Test name
Test status
Simulation time 52400215884 ps
CPU time 805.99 seconds
Started Jul 17 06:08:41 PM PDT 24
Finished Jul 17 06:22:16 PM PDT 24
Peak memory 265228 kb
Host smart-b5973cae-e122-4dd4-8c34-49462acaf305
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485478535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1485478535
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.614932067
Short name T108
Test name
Test status
Simulation time 56444299940 ps
CPU time 1588.34 seconds
Started Jul 17 06:09:02 PM PDT 24
Finished Jul 17 06:35:32 PM PDT 24
Peak memory 289648 kb
Host smart-45b668d0-af76-4ca2-afff-43daa0435025
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614932067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.614932067
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1352598410
Short name T238
Test name
Test status
Simulation time 8612536665 ps
CPU time 135.98 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:11:07 PM PDT 24
Peak memory 257000 kb
Host smart-d35d988c-5c52-47b4-a415-6bfbf558a17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13525
98410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1352598410
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3024459775
Short name T601
Test name
Test status
Simulation time 625888829 ps
CPU time 19.71 seconds
Started Jul 17 06:09:07 PM PDT 24
Finished Jul 17 06:09:29 PM PDT 24
Peak memory 248504 kb
Host smart-6a7934ab-c131-4e35-91de-928b113e53cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244
59775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3024459775
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2793808465
Short name T324
Test name
Test status
Simulation time 18578477246 ps
CPU time 1113.53 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:27:25 PM PDT 24
Peak memory 273360 kb
Host smart-9afc4ee8-9b93-4aac-bf85-d93a064a7182
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793808465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2793808465
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.732418359
Short name T1
Test name
Test status
Simulation time 102641176294 ps
CPU time 2594.85 seconds
Started Jul 17 06:08:52 PM PDT 24
Finished Jul 17 06:52:11 PM PDT 24
Peak memory 289484 kb
Host smart-de6b3d5e-2b44-4169-857e-916b7de5aecf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732418359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.732418359
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2430646773
Short name T526
Test name
Test status
Simulation time 9357434269 ps
CPU time 399.43 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:15:30 PM PDT 24
Peak memory 248668 kb
Host smart-6b851b90-1a19-4604-9eed-b41df42f8968
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430646773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2430646773
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.302145646
Short name T384
Test name
Test status
Simulation time 1131906280 ps
CPU time 40.98 seconds
Started Jul 17 06:08:40 PM PDT 24
Finished Jul 17 06:09:30 PM PDT 24
Peak memory 256876 kb
Host smart-8a5e0b50-570a-4965-8f4f-f3b0a149066f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30214
5646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.302145646
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2940595144
Short name T99
Test name
Test status
Simulation time 750393310 ps
CPU time 53.32 seconds
Started Jul 17 06:08:35 PM PDT 24
Finished Jul 17 06:09:42 PM PDT 24
Peak memory 256268 kb
Host smart-1f8a418f-1db4-4fea-9d1b-761b922c1c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29405
95144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2940595144
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.232271154
Short name T572
Test name
Test status
Simulation time 241534438 ps
CPU time 15.87 seconds
Started Jul 17 06:08:46 PM PDT 24
Finished Jul 17 06:09:09 PM PDT 24
Peak memory 248328 kb
Host smart-9b30ce78-513c-4485-97b8-fc9cec68ac19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23227
1154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.232271154
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.158939119
Short name T52
Test name
Test status
Simulation time 824591293 ps
CPU time 48.89 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:09:40 PM PDT 24
Peak memory 256872 kb
Host smart-90d2aff2-d478-42dd-a617-d41e2b786bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15893
9119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.158939119
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2186859382
Short name T472
Test name
Test status
Simulation time 17020426326 ps
CPU time 1509.37 seconds
Started Jul 17 06:08:39 PM PDT 24
Finished Jul 17 06:33:58 PM PDT 24
Peak memory 289360 kb
Host smart-e1a940a5-9cca-4567-9d32-0fdc36c422ba
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186859382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2186859382
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.576218053
Short name T396
Test name
Test status
Simulation time 190993288163 ps
CPU time 2932.1 seconds
Started Jul 17 06:08:47 PM PDT 24
Finished Jul 17 06:57:46 PM PDT 24
Peak memory 281508 kb
Host smart-25b10d69-3981-4587-982c-78f561cb468e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576218053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.576218053
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.4118737838
Short name T237
Test name
Test status
Simulation time 6488398614 ps
CPU time 145.61 seconds
Started Jul 17 06:08:38 PM PDT 24
Finished Jul 17 06:11:13 PM PDT 24
Peak memory 256548 kb
Host smart-6ca36199-de6b-4321-a50b-c9936243690a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41187
37838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.4118737838
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2999074363
Short name T670
Test name
Test status
Simulation time 1864301338 ps
CPU time 67.11 seconds
Started Jul 17 06:08:39 PM PDT 24
Finished Jul 17 06:09:56 PM PDT 24
Peak memory 248276 kb
Host smart-145d6fd4-a6d6-4e59-849d-e8e3790dd97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29990
74363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2999074363
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.251913648
Short name T283
Test name
Test status
Simulation time 7307607705 ps
CPU time 769.74 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:21:41 PM PDT 24
Peak memory 272672 kb
Host smart-a95bcece-97f4-40d3-a7c6-9a0ae0207e54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251913648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.251913648
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3944734748
Short name T362
Test name
Test status
Simulation time 43627146985 ps
CPU time 1350.84 seconds
Started Jul 17 06:08:39 PM PDT 24
Finished Jul 17 06:31:20 PM PDT 24
Peak memory 272332 kb
Host smart-96f7b7bc-0ac4-47c0-acdb-96f00e9be95c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944734748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3944734748
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1996069672
Short name T519
Test name
Test status
Simulation time 2064411842 ps
CPU time 89.92 seconds
Started Jul 17 06:09:07 PM PDT 24
Finished Jul 17 06:10:39 PM PDT 24
Peak memory 247548 kb
Host smart-2912e515-ac7c-4258-bb0f-5d8a77f534c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996069672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1996069672
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1388174354
Short name T47
Test name
Test status
Simulation time 525771122 ps
CPU time 33.54 seconds
Started Jul 17 06:08:38 PM PDT 24
Finished Jul 17 06:09:21 PM PDT 24
Peak memory 255712 kb
Host smart-31b826f4-6d1a-4aa8-9abe-1e39c092ea0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13881
74354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1388174354
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2339280943
Short name T424
Test name
Test status
Simulation time 1414744037 ps
CPU time 27.68 seconds
Started Jul 17 06:08:43 PM PDT 24
Finished Jul 17 06:09:19 PM PDT 24
Peak memory 256260 kb
Host smart-71733f18-27a4-4652-8da4-2defa4775784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23392
80943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2339280943
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3471324790
Short name T104
Test name
Test status
Simulation time 358168801 ps
CPU time 15.3 seconds
Started Jul 17 06:08:39 PM PDT 24
Finished Jul 17 06:09:04 PM PDT 24
Peak memory 256440 kb
Host smart-12ce8c58-d150-48ce-83eb-d19ce4a04e69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34713
24790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3471324790
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.200496466
Short name T20
Test name
Test status
Simulation time 2136571736 ps
CPU time 58.91 seconds
Started Jul 17 06:09:05 PM PDT 24
Finished Jul 17 06:10:06 PM PDT 24
Peak memory 248720 kb
Host smart-fde70c6c-35cd-4691-a1ac-1a11eedcb9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20049
6466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.200496466
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.16391266
Short name T41
Test name
Test status
Simulation time 53254666 ps
CPU time 2.55 seconds
Started Jul 17 06:07:50 PM PDT 24
Finished Jul 17 06:07:57 PM PDT 24
Peak memory 248952 kb
Host smart-86c4fc81-6e61-4749-a6e2-b19b64df2ed4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=16391266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.16391266
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3189727909
Short name T450
Test name
Test status
Simulation time 209966269602 ps
CPU time 2956.97 seconds
Started Jul 17 06:07:49 PM PDT 24
Finished Jul 17 06:57:11 PM PDT 24
Peak memory 288252 kb
Host smart-d2be60ec-5fbe-4953-9302-d09435eba45d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189727909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3189727909
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1991311303
Short name T368
Test name
Test status
Simulation time 499279248 ps
CPU time 21.57 seconds
Started Jul 17 06:08:18 PM PDT 24
Finished Jul 17 06:08:41 PM PDT 24
Peak memory 248604 kb
Host smart-33bf4691-dcc1-4093-99e0-953323852647
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1991311303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1991311303
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.328826550
Short name T33
Test name
Test status
Simulation time 714726725 ps
CPU time 76.5 seconds
Started Jul 17 06:08:00 PM PDT 24
Finished Jul 17 06:09:18 PM PDT 24
Peak memory 256560 kb
Host smart-ae797324-1264-4f0d-af75-e585cd42f0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32882
6550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.328826550
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2452626023
Short name T445
Test name
Test status
Simulation time 1175097042 ps
CPU time 34.5 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 06:08:35 PM PDT 24
Peak memory 248676 kb
Host smart-163cce84-178b-4e25-ba47-eecb11f3c836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24526
26023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2452626023
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3929190733
Short name T681
Test name
Test status
Simulation time 10977738728 ps
CPU time 1026.49 seconds
Started Jul 17 06:07:49 PM PDT 24
Finished Jul 17 06:25:01 PM PDT 24
Peak memory 273344 kb
Host smart-867dd4b5-fa02-447e-85c6-397a8726b536
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929190733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3929190733
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3596657037
Short name T411
Test name
Test status
Simulation time 10363001787 ps
CPU time 1132.04 seconds
Started Jul 17 06:07:46 PM PDT 24
Finished Jul 17 06:26:44 PM PDT 24
Peak memory 288736 kb
Host smart-65e8cdfd-15a2-4783-8fc9-08585dde0b61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596657037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3596657037
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2056368163
Short name T482
Test name
Test status
Simulation time 9518068413 ps
CPU time 361.52 seconds
Started Jul 17 06:07:59 PM PDT 24
Finished Jul 17 06:14:02 PM PDT 24
Peak memory 254652 kb
Host smart-f33e12a1-2e73-4feb-9aad-e5e3a03229ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056368163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2056368163
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2866678753
Short name T91
Test name
Test status
Simulation time 1046901076 ps
CPU time 16.36 seconds
Started Jul 17 06:07:49 PM PDT 24
Finished Jul 17 06:08:11 PM PDT 24
Peak memory 248640 kb
Host smart-18e488d7-10fb-4222-a71f-251b1c89a856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28666
78753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2866678753
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2275561253
Short name T378
Test name
Test status
Simulation time 395558513 ps
CPU time 14.34 seconds
Started Jul 17 06:07:59 PM PDT 24
Finished Jul 17 06:08:15 PM PDT 24
Peak memory 248456 kb
Host smart-bdc22c4f-ccee-4830-821f-53163a683108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22755
61253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2275561253
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2666707496
Short name T31
Test name
Test status
Simulation time 3435000774 ps
CPU time 10.22 seconds
Started Jul 17 06:08:24 PM PDT 24
Finished Jul 17 06:08:35 PM PDT 24
Peak memory 269676 kb
Host smart-cbef091c-e47f-4f9d-ad5e-9b9fad10c4c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2666707496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2666707496
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2624386644
Short name T453
Test name
Test status
Simulation time 179157650 ps
CPU time 19.51 seconds
Started Jul 17 06:08:00 PM PDT 24
Finished Jul 17 06:08:21 PM PDT 24
Peak memory 248200 kb
Host smart-c7c0791d-d347-4b7d-8718-ca82c52aa85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26243
86644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2624386644
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3415873518
Short name T351
Test name
Test status
Simulation time 655893718 ps
CPU time 33.14 seconds
Started Jul 17 06:07:59 PM PDT 24
Finished Jul 17 06:08:34 PM PDT 24
Peak memory 256348 kb
Host smart-e2038ca4-5733-4d06-820e-5a4b2240a3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34158
73518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3415873518
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.211199967
Short name T608
Test name
Test status
Simulation time 80351834457 ps
CPU time 2738.93 seconds
Started Jul 17 06:09:07 PM PDT 24
Finished Jul 17 06:54:48 PM PDT 24
Peak memory 289696 kb
Host smart-1e1f9c9c-13d5-45bc-a84c-e3b4262953bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211199967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.211199967
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3057778234
Short name T549
Test name
Test status
Simulation time 870408347 ps
CPU time 24.67 seconds
Started Jul 17 06:08:34 PM PDT 24
Finished Jul 17 06:09:07 PM PDT 24
Peak memory 248260 kb
Host smart-38866b3a-d48d-4e7f-ab25-116d298c7bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30577
78234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3057778234
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3853561882
Short name T687
Test name
Test status
Simulation time 52310729 ps
CPU time 2.58 seconds
Started Jul 17 06:08:46 PM PDT 24
Finished Jul 17 06:08:56 PM PDT 24
Peak memory 249180 kb
Host smart-c721a5f7-c724-4f35-846c-08233fa5376b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38535
61882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3853561882
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.575573427
Short name T518
Test name
Test status
Simulation time 56005331825 ps
CPU time 1438.41 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:32:45 PM PDT 24
Peak memory 289840 kb
Host smart-7ffe4d67-8b3e-4dfd-8530-6354a754d908
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575573427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.575573427
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.594726780
Short name T634
Test name
Test status
Simulation time 6604331440 ps
CPU time 266.59 seconds
Started Jul 17 06:08:45 PM PDT 24
Finished Jul 17 06:13:19 PM PDT 24
Peak memory 255516 kb
Host smart-12720b0c-2265-4fb3-ba59-cac122ad31a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594726780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.594726780
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3541701797
Short name T563
Test name
Test status
Simulation time 2291916189 ps
CPU time 40.16 seconds
Started Jul 17 06:08:58 PM PDT 24
Finished Jul 17 06:09:39 PM PDT 24
Peak memory 248820 kb
Host smart-bf080496-bc0e-47bd-bd77-4f235b784afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35417
01797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3541701797
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.578498837
Short name T271
Test name
Test status
Simulation time 1998033254 ps
CPU time 32.07 seconds
Started Jul 17 06:09:02 PM PDT 24
Finished Jul 17 06:09:35 PM PDT 24
Peak memory 248576 kb
Host smart-e86c78f3-7855-452f-9958-4df41bd30c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57849
8837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.578498837
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2561507786
Short name T62
Test name
Test status
Simulation time 1510915826 ps
CPU time 46.57 seconds
Started Jul 17 06:08:40 PM PDT 24
Finished Jul 17 06:09:36 PM PDT 24
Peak memory 248268 kb
Host smart-821e417d-b645-4b36-ae0c-f9a0e11bfe71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25615
07786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2561507786
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2659143674
Short name T621
Test name
Test status
Simulation time 544057133 ps
CPU time 18.04 seconds
Started Jul 17 06:08:40 PM PDT 24
Finished Jul 17 06:09:07 PM PDT 24
Peak memory 252976 kb
Host smart-253ad6b4-bb7c-4d1b-8780-49e67851e10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
43674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2659143674
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3308407413
Short name T569
Test name
Test status
Simulation time 2971047167 ps
CPU time 168.76 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:11:36 PM PDT 24
Peak memory 257052 kb
Host smart-18456b3f-935a-4cc5-af70-170adec4433d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308407413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3308407413
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.402587199
Short name T593
Test name
Test status
Simulation time 84261797051 ps
CPU time 945.02 seconds
Started Jul 17 06:09:03 PM PDT 24
Finished Jul 17 06:24:50 PM PDT 24
Peak memory 289812 kb
Host smart-3266d36f-6dfa-4a24-9637-15c9fc3f2e31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402587199 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.402587199
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2541681413
Short name T400
Test name
Test status
Simulation time 169015956083 ps
CPU time 2747.39 seconds
Started Jul 17 06:08:40 PM PDT 24
Finished Jul 17 06:54:37 PM PDT 24
Peak memory 288632 kb
Host smart-7657d7d7-6c7a-4556-933a-23a18c5041b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541681413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2541681413
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3518211965
Short name T639
Test name
Test status
Simulation time 2856718128 ps
CPU time 92.63 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:10:18 PM PDT 24
Peak memory 257016 kb
Host smart-0b7b75be-31a9-43f1-a05d-e32d6a267631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35182
11965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3518211965
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.146644603
Short name T357
Test name
Test status
Simulation time 688901281 ps
CPU time 18.86 seconds
Started Jul 17 06:08:48 PM PDT 24
Finished Jul 17 06:09:13 PM PDT 24
Peak memory 248616 kb
Host smart-ed3c2878-56fd-4028-8484-15054cbaa8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14664
4603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.146644603
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2234218089
Short name T659
Test name
Test status
Simulation time 227008543377 ps
CPU time 3366.44 seconds
Started Jul 17 06:08:40 PM PDT 24
Finished Jul 17 07:04:56 PM PDT 24
Peak memory 289656 kb
Host smart-52629501-4c29-4be6-a11c-d5060dc90e3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234218089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2234218089
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.838260887
Short name T657
Test name
Test status
Simulation time 101190414120 ps
CPU time 2389.06 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:48:40 PM PDT 24
Peak memory 281620 kb
Host smart-7a5a1fce-4cd7-49d8-9aef-df58d84563c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838260887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.838260887
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.126552945
Short name T291
Test name
Test status
Simulation time 2644507089 ps
CPU time 119.89 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:10:47 PM PDT 24
Peak memory 255268 kb
Host smart-e934f13f-dd9b-4254-8a8d-63d770556347
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126552945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.126552945
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2344894507
Short name T483
Test name
Test status
Simulation time 220443370 ps
CPU time 19.73 seconds
Started Jul 17 06:08:38 PM PDT 24
Finished Jul 17 06:09:07 PM PDT 24
Peak memory 248588 kb
Host smart-707e0b00-91d6-449c-aa65-e235c31d9c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23448
94507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2344894507
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3250181355
Short name T697
Test name
Test status
Simulation time 756796361 ps
CPU time 17.51 seconds
Started Jul 17 06:08:47 PM PDT 24
Finished Jul 17 06:09:11 PM PDT 24
Peak memory 256852 kb
Host smart-486f16c8-8d1a-449c-b392-24087e5859e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32501
81355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3250181355
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1519707349
Short name T503
Test name
Test status
Simulation time 299209045 ps
CPU time 18.23 seconds
Started Jul 17 06:08:47 PM PDT 24
Finished Jul 17 06:09:12 PM PDT 24
Peak memory 248292 kb
Host smart-4ab64def-e7d7-4077-8038-195b42e26790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15197
07349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1519707349
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1922109165
Short name T451
Test name
Test status
Simulation time 725791673 ps
CPU time 11.66 seconds
Started Jul 17 06:08:45 PM PDT 24
Finished Jul 17 06:09:04 PM PDT 24
Peak memory 249088 kb
Host smart-943d7745-71e2-48d5-bf0a-ac24ef805ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19221
09165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1922109165
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1165272427
Short name T365
Test name
Test status
Simulation time 45311965136 ps
CPU time 1384.79 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:32:00 PM PDT 24
Peak memory 287896 kb
Host smart-9ded970b-13c2-42c9-8a12-c0350598ac01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165272427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1165272427
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1762204627
Short name T548
Test name
Test status
Simulation time 1450074122 ps
CPU time 72.4 seconds
Started Jul 17 06:08:47 PM PDT 24
Finished Jul 17 06:10:06 PM PDT 24
Peak memory 256548 kb
Host smart-85c6718b-fca0-436a-b447-7e05f4049bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17622
04627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1762204627
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1546886329
Short name T116
Test name
Test status
Simulation time 506200789 ps
CPU time 32.45 seconds
Started Jul 17 06:08:52 PM PDT 24
Finished Jul 17 06:09:29 PM PDT 24
Peak memory 248604 kb
Host smart-9b0dc037-40ee-4c66-b03c-1e4566b054f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15468
86329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1546886329
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2128256262
Short name T644
Test name
Test status
Simulation time 156875337081 ps
CPU time 2579.94 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:51:51 PM PDT 24
Peak memory 288832 kb
Host smart-2f1dbc55-a951-491b-beab-95e15212a7cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128256262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2128256262
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1572253701
Short name T380
Test name
Test status
Simulation time 303306130314 ps
CPU time 2031.52 seconds
Started Jul 17 06:09:08 PM PDT 24
Finished Jul 17 06:43:01 PM PDT 24
Peak memory 273372 kb
Host smart-d649379a-c93c-4739-ab08-47b569b500ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572253701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1572253701
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1204880853
Short name T299
Test name
Test status
Simulation time 24590918190 ps
CPU time 401.03 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:15:32 PM PDT 24
Peak memory 255968 kb
Host smart-6de235c6-0396-4b7c-9d59-9652fa1e0dba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204880853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1204880853
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2893025765
Short name T43
Test name
Test status
Simulation time 343345165 ps
CPU time 28.95 seconds
Started Jul 17 06:08:46 PM PDT 24
Finished Jul 17 06:09:22 PM PDT 24
Peak memory 256304 kb
Host smart-b532f2ad-b111-4a93-be00-e7a8cfcd2e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28930
25765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2893025765
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3367439955
Short name T439
Test name
Test status
Simulation time 280299734 ps
CPU time 29.19 seconds
Started Jul 17 06:08:47 PM PDT 24
Finished Jul 17 06:09:22 PM PDT 24
Peak memory 247776 kb
Host smart-83223b6e-cc19-49c1-a532-689a3489b67e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33674
39955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3367439955
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.722424992
Short name T70
Test name
Test status
Simulation time 880986704 ps
CPU time 27.45 seconds
Started Jul 17 06:08:47 PM PDT 24
Finished Jul 17 06:09:21 PM PDT 24
Peak memory 248648 kb
Host smart-02149d5c-7785-4c33-8fa4-84fc4c4cc72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72242
4992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.722424992
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.683206508
Short name T398
Test name
Test status
Simulation time 1312688878 ps
CPU time 43.9 seconds
Started Jul 17 06:09:03 PM PDT 24
Finished Jul 17 06:09:48 PM PDT 24
Peak memory 255964 kb
Host smart-ff421db5-d005-4caf-89d6-4204f3306877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68320
6508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.683206508
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2880707622
Short name T425
Test name
Test status
Simulation time 101847367521 ps
CPU time 1485.78 seconds
Started Jul 17 06:08:46 PM PDT 24
Finished Jul 17 06:33:39 PM PDT 24
Peak memory 289812 kb
Host smart-b9d5bc29-1f97-4691-8e71-6de0c3b2e229
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880707622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2880707622
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1146681632
Short name T430
Test name
Test status
Simulation time 158794195093 ps
CPU time 1796.71 seconds
Started Jul 17 06:08:50 PM PDT 24
Finished Jul 17 06:38:52 PM PDT 24
Peak memory 273380 kb
Host smart-7020251b-2352-4d7a-8558-abdec6902ac3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146681632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1146681632
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3961959867
Short name T92
Test name
Test status
Simulation time 1739461141 ps
CPU time 133.06 seconds
Started Jul 17 06:09:01 PM PDT 24
Finished Jul 17 06:11:15 PM PDT 24
Peak memory 251752 kb
Host smart-b103f060-5c5a-4a73-bdc7-caf75c694b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39619
59867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3961959867
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.4267215649
Short name T520
Test name
Test status
Simulation time 1067061978 ps
CPU time 17.27 seconds
Started Jul 17 06:08:47 PM PDT 24
Finished Jul 17 06:09:11 PM PDT 24
Peak memory 248220 kb
Host smart-ce678269-af66-42f5-81c8-2964b2b6c0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42672
15649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.4267215649
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1839183138
Short name T539
Test name
Test status
Simulation time 235228908074 ps
CPU time 1732.61 seconds
Started Jul 17 06:09:06 PM PDT 24
Finished Jul 17 06:38:01 PM PDT 24
Peak memory 272948 kb
Host smart-fc4eca73-6cf9-4f45-b017-f3a18acbe9b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839183138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1839183138
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2891993564
Short name T63
Test name
Test status
Simulation time 7698671324 ps
CPU time 321.16 seconds
Started Jul 17 06:09:08 PM PDT 24
Finished Jul 17 06:14:31 PM PDT 24
Peak memory 255808 kb
Host smart-2e2a3ab4-8ced-4f06-9779-8df1eacc4e49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891993564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2891993564
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3007284674
Short name T468
Test name
Test status
Simulation time 383872597 ps
CPU time 24.98 seconds
Started Jul 17 06:09:06 PM PDT 24
Finished Jul 17 06:09:33 PM PDT 24
Peak memory 256084 kb
Host smart-ff58a334-7efd-4c5d-a472-71be2b04f73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30072
84674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3007284674
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3284471297
Short name T633
Test name
Test status
Simulation time 601356537 ps
CPU time 19.97 seconds
Started Jul 17 06:08:47 PM PDT 24
Finished Jul 17 06:09:14 PM PDT 24
Peak memory 248036 kb
Host smart-eb1512d3-f8ad-41a5-8ebb-42678a787feb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32844
71297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3284471297
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.256057351
Short name T240
Test name
Test status
Simulation time 1803449055 ps
CPU time 21.27 seconds
Started Jul 17 06:08:46 PM PDT 24
Finished Jul 17 06:09:14 PM PDT 24
Peak memory 248576 kb
Host smart-79f91ca6-a667-4ab2-8e2f-8f9dfb8be0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25605
7351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.256057351
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3148230016
Short name T612
Test name
Test status
Simulation time 1042778310 ps
CPU time 42.53 seconds
Started Jul 17 06:10:01 PM PDT 24
Finished Jul 17 06:10:45 PM PDT 24
Peak memory 256876 kb
Host smart-7a1a4d8d-38af-424f-a229-95959a995c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31482
30016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3148230016
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2658479446
Short name T49
Test name
Test status
Simulation time 199319797064 ps
CPU time 5237.25 seconds
Started Jul 17 06:08:39 PM PDT 24
Finished Jul 17 07:36:07 PM PDT 24
Peak memory 363528 kb
Host smart-789b37ac-a3f7-4f16-9a6a-41c6886e16a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658479446 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2658479446
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.4044419171
Short name T404
Test name
Test status
Simulation time 6465215944 ps
CPU time 90.49 seconds
Started Jul 17 06:08:48 PM PDT 24
Finished Jul 17 06:10:25 PM PDT 24
Peak memory 255636 kb
Host smart-e335fbde-dbb3-42c0-93c1-f308f7bebe1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40444
19171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.4044419171
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3474576163
Short name T444
Test name
Test status
Simulation time 1658610783 ps
CPU time 27.14 seconds
Started Jul 17 06:08:40 PM PDT 24
Finished Jul 17 06:09:16 PM PDT 24
Peak memory 248648 kb
Host smart-ac23d1e5-a100-4b1b-adc3-8b3b9ed85ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34745
76163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3474576163
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1508493772
Short name T438
Test name
Test status
Simulation time 44552650476 ps
CPU time 1190.15 seconds
Started Jul 17 06:08:51 PM PDT 24
Finished Jul 17 06:28:46 PM PDT 24
Peak memory 288208 kb
Host smart-d92a4140-86ff-48ba-8dc9-be7b4eef4cd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508493772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1508493772
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3335003465
Short name T516
Test name
Test status
Simulation time 460553931 ps
CPU time 15.84 seconds
Started Jul 17 06:08:41 PM PDT 24
Finished Jul 17 06:09:06 PM PDT 24
Peak memory 248640 kb
Host smart-f050330d-12c7-4577-b799-532c43b63536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33350
03465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3335003465
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2501397122
Short name T433
Test name
Test status
Simulation time 771215396 ps
CPU time 53.64 seconds
Started Jul 17 06:08:37 PM PDT 24
Finished Jul 17 06:09:40 PM PDT 24
Peak memory 248932 kb
Host smart-f650653a-591e-43c4-86e3-c0ab5756ae49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25013
97122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2501397122
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1428403819
Short name T275
Test name
Test status
Simulation time 1468935017 ps
CPU time 16.18 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:09:07 PM PDT 24
Peak memory 248244 kb
Host smart-9e224150-6a6a-431d-b120-eae6a089d786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14284
03819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1428403819
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2697864004
Short name T470
Test name
Test status
Simulation time 624496395 ps
CPU time 40.86 seconds
Started Jul 17 06:09:06 PM PDT 24
Finished Jul 17 06:09:49 PM PDT 24
Peak memory 256824 kb
Host smart-f2642059-831e-46c2-ab49-ae34cdc1a6b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26978
64004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2697864004
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2593851729
Short name T239
Test name
Test status
Simulation time 66820675851 ps
CPU time 2523.21 seconds
Started Jul 17 06:08:50 PM PDT 24
Finished Jul 17 06:50:59 PM PDT 24
Peak memory 288988 kb
Host smart-5f6d63d0-5022-407c-971e-f3f831bb13ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593851729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2593851729
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1858771120
Short name T665
Test name
Test status
Simulation time 65376157821 ps
CPU time 1809.31 seconds
Started Jul 17 06:09:08 PM PDT 24
Finished Jul 17 06:39:19 PM PDT 24
Peak memory 268296 kb
Host smart-2c82c9da-96ea-4e81-9d2f-863ff0c566c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858771120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1858771120
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1426798955
Short name T565
Test name
Test status
Simulation time 281545439 ps
CPU time 17.37 seconds
Started Jul 17 06:09:09 PM PDT 24
Finished Jul 17 06:09:27 PM PDT 24
Peak memory 255148 kb
Host smart-07450e3c-b647-4e75-8f26-90bf917f13b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14267
98955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1426798955
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2341284637
Short name T449
Test name
Test status
Simulation time 625148304 ps
CPU time 14.98 seconds
Started Jul 17 06:08:41 PM PDT 24
Finished Jul 17 06:09:05 PM PDT 24
Peak memory 248640 kb
Host smart-95932c19-7ffe-47f9-81a3-4680b349fced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23412
84637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2341284637
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1757885017
Short name T306
Test name
Test status
Simulation time 34198537365 ps
CPU time 1903.35 seconds
Started Jul 17 06:08:57 PM PDT 24
Finished Jul 17 06:40:42 PM PDT 24
Peak memory 272728 kb
Host smart-9441ee63-1630-43dc-a5db-cbbad819b420
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757885017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1757885017
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1702254148
Short name T370
Test name
Test status
Simulation time 16228586186 ps
CPU time 1450.33 seconds
Started Jul 17 06:09:06 PM PDT 24
Finished Jul 17 06:33:18 PM PDT 24
Peak memory 289836 kb
Host smart-e6c11866-1906-4e2b-aec3-fdc6de8b8c60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702254148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1702254148
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4231021351
Short name T289
Test name
Test status
Simulation time 38358543368 ps
CPU time 393.5 seconds
Started Jul 17 06:09:02 PM PDT 24
Finished Jul 17 06:15:37 PM PDT 24
Peak memory 248592 kb
Host smart-e416702a-001d-4080-903d-589422a629f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231021351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4231021351
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1968287030
Short name T94
Test name
Test status
Simulation time 378799108 ps
CPU time 10.55 seconds
Started Jul 17 06:08:40 PM PDT 24
Finished Jul 17 06:08:59 PM PDT 24
Peak memory 248692 kb
Host smart-03d3742c-6681-44ff-8a33-f96a2129e48b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19682
87030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1968287030
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2807505399
Short name T525
Test name
Test status
Simulation time 357906447 ps
CPU time 5.75 seconds
Started Jul 17 06:09:04 PM PDT 24
Finished Jul 17 06:09:12 PM PDT 24
Peak memory 240712 kb
Host smart-5d2e6f05-7ad6-448a-8170-a2e32d5864e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28075
05399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2807505399
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3419276877
Short name T113
Test name
Test status
Simulation time 193382083 ps
CPU time 13.24 seconds
Started Jul 17 06:09:07 PM PDT 24
Finished Jul 17 06:09:22 PM PDT 24
Peak memory 256232 kb
Host smart-28682d63-1a61-439d-b2b2-35d677bbc8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34192
76877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3419276877
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3379814755
Short name T669
Test name
Test status
Simulation time 1518949540 ps
CPU time 28.3 seconds
Started Jul 17 06:08:51 PM PDT 24
Finished Jul 17 06:09:24 PM PDT 24
Peak memory 255244 kb
Host smart-11680eff-860c-4e6a-9a6d-054c90c103c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33798
14755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3379814755
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2475637478
Short name T419
Test name
Test status
Simulation time 1099605252 ps
CPU time 65.33 seconds
Started Jul 17 06:08:42 PM PDT 24
Finished Jul 17 06:09:56 PM PDT 24
Peak memory 256872 kb
Host smart-1e5e045b-f020-4a7c-83e4-4e07c21b9ee2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475637478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2475637478
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3056510799
Short name T627
Test name
Test status
Simulation time 148513411891 ps
CPU time 2407.91 seconds
Started Jul 17 06:08:46 PM PDT 24
Finished Jul 17 06:49:01 PM PDT 24
Peak memory 289296 kb
Host smart-93c5928a-8d41-4e49-aee0-029f52e8771d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056510799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3056510799
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4126461936
Short name T547
Test name
Test status
Simulation time 795944171 ps
CPU time 42.03 seconds
Started Jul 17 06:08:46 PM PDT 24
Finished Jul 17 06:09:35 PM PDT 24
Peak memory 256220 kb
Host smart-3ca57119-0f95-447d-aaa0-19dc72c1addd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41264
61936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4126461936
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.34607299
Short name T77
Test name
Test status
Simulation time 150593326 ps
CPU time 8.01 seconds
Started Jul 17 06:09:03 PM PDT 24
Finished Jul 17 06:09:12 PM PDT 24
Peak memory 248196 kb
Host smart-240bfe57-65cf-4b12-883e-c2d80f056450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34607
299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.34607299
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2726968905
Short name T329
Test name
Test status
Simulation time 40027400712 ps
CPU time 2256.32 seconds
Started Jul 17 06:08:53 PM PDT 24
Finished Jul 17 06:46:33 PM PDT 24
Peak memory 272644 kb
Host smart-d9c35d36-ddc4-4694-8e6c-68ca789bb2ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726968905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2726968905
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3438247412
Short name T374
Test name
Test status
Simulation time 15708383883 ps
CPU time 1380.27 seconds
Started Jul 17 06:08:48 PM PDT 24
Finished Jul 17 06:31:55 PM PDT 24
Peak memory 289648 kb
Host smart-493c2c13-ec09-476b-a974-4f0a03f1eded
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438247412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3438247412
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.349876973
Short name T305
Test name
Test status
Simulation time 12445774593 ps
CPU time 189.98 seconds
Started Jul 17 06:08:51 PM PDT 24
Finished Jul 17 06:12:06 PM PDT 24
Peak memory 248604 kb
Host smart-205af4cb-9312-4a2c-a40f-71806ffe9df2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349876973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.349876973
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.190859418
Short name T536
Test name
Test status
Simulation time 206371361 ps
CPU time 9.1 seconds
Started Jul 17 06:08:47 PM PDT 24
Finished Jul 17 06:09:02 PM PDT 24
Peak memory 248468 kb
Host smart-b00fc9ab-7062-41ab-8b01-dbbe8c3391e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19085
9418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.190859418
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2525864477
Short name T372
Test name
Test status
Simulation time 621267034 ps
CPU time 17.66 seconds
Started Jul 17 06:09:02 PM PDT 24
Finished Jul 17 06:09:21 PM PDT 24
Peak memory 255376 kb
Host smart-4145b825-1a5a-43eb-9bed-de86125cac9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25258
64477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2525864477
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1775318195
Short name T102
Test name
Test status
Simulation time 121509058 ps
CPU time 16.38 seconds
Started Jul 17 06:09:07 PM PDT 24
Finished Jul 17 06:09:25 PM PDT 24
Peak memory 248592 kb
Host smart-d8941c26-9a59-4c6f-906c-f55701a6ad17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17753
18195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1775318195
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3199483371
Short name T44
Test name
Test status
Simulation time 8145977446 ps
CPU time 40.39 seconds
Started Jul 17 06:08:36 PM PDT 24
Finished Jul 17 06:09:26 PM PDT 24
Peak memory 256944 kb
Host smart-b5e604d4-89bc-403f-8c70-3afab3842e54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31994
83371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3199483371
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2855047412
Short name T248
Test name
Test status
Simulation time 41069373808 ps
CPU time 2130.02 seconds
Started Jul 17 06:08:40 PM PDT 24
Finished Jul 17 06:44:19 PM PDT 24
Peak memory 289584 kb
Host smart-60f3cda5-e0e0-41da-8600-e55688ac76d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855047412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2855047412
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2558366575
Short name T640
Test name
Test status
Simulation time 106221662626 ps
CPU time 2434.54 seconds
Started Jul 17 06:09:00 PM PDT 24
Finished Jul 17 06:49:36 PM PDT 24
Peak memory 298056 kb
Host smart-c12f400e-9e34-43a9-8224-8f982df8216d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558366575 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2558366575
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1840491178
Short name T264
Test name
Test status
Simulation time 55961879978 ps
CPU time 1970.81 seconds
Started Jul 17 06:09:04 PM PDT 24
Finished Jul 17 06:41:57 PM PDT 24
Peak memory 273248 kb
Host smart-8cacf10f-a3ef-41df-ba2d-dc1823bb47f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840491178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1840491178
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1351178218
Short name T399
Test name
Test status
Simulation time 2682018688 ps
CPU time 163.15 seconds
Started Jul 17 06:08:47 PM PDT 24
Finished Jul 17 06:11:37 PM PDT 24
Peak memory 256984 kb
Host smart-a0a54220-6188-46bd-be26-b05709c7e794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13511
78218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1351178218
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3647107408
Short name T695
Test name
Test status
Simulation time 1208399662 ps
CPU time 23.56 seconds
Started Jul 17 06:08:57 PM PDT 24
Finished Jul 17 06:09:22 PM PDT 24
Peak memory 256856 kb
Host smart-5b99ac12-2408-473f-ad6f-632039c18f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36471
07408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3647107408
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3022763553
Short name T318
Test name
Test status
Simulation time 28574899962 ps
CPU time 1553.52 seconds
Started Jul 17 06:09:01 PM PDT 24
Finished Jul 17 06:34:55 PM PDT 24
Peak memory 288268 kb
Host smart-12057116-cdcb-4720-b6c6-f6533de8c9e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022763553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3022763553
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1013636223
Short name T523
Test name
Test status
Simulation time 137798537154 ps
CPU time 1973.23 seconds
Started Jul 17 06:09:07 PM PDT 24
Finished Jul 17 06:42:02 PM PDT 24
Peak memory 284360 kb
Host smart-4162780b-3f12-48d5-a0d8-17243a9c620e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013636223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1013636223
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3870177239
Short name T290
Test name
Test status
Simulation time 17197856643 ps
CPU time 597.31 seconds
Started Jul 17 06:09:05 PM PDT 24
Finished Jul 17 06:19:04 PM PDT 24
Peak memory 248788 kb
Host smart-c81f6b84-9f1d-4dab-9d51-6e3784d779b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870177239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3870177239
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3371685100
Short name T406
Test name
Test status
Simulation time 4503121340 ps
CPU time 65.37 seconds
Started Jul 17 06:09:00 PM PDT 24
Finished Jul 17 06:10:06 PM PDT 24
Peak memory 256852 kb
Host smart-fb99cc05-ff46-4cea-b10e-ed76d2855932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33716
85100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3371685100
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2552139442
Short name T349
Test name
Test status
Simulation time 1833783622 ps
CPU time 68.95 seconds
Started Jul 17 06:08:49 PM PDT 24
Finished Jul 17 06:10:04 PM PDT 24
Peak memory 256008 kb
Host smart-e83b7c9e-ebdc-47b7-9cdc-5d4508f42af2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25521
39442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2552139442
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1258555582
Short name T383
Test name
Test status
Simulation time 1546170643 ps
CPU time 24.78 seconds
Started Jul 17 06:08:57 PM PDT 24
Finished Jul 17 06:09:23 PM PDT 24
Peak memory 256100 kb
Host smart-5e4f9aec-b9c1-4c2e-9af7-849d8dec8c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12585
55582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1258555582
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3259904038
Short name T269
Test name
Test status
Simulation time 716007094 ps
CPU time 39.1 seconds
Started Jul 17 06:08:45 PM PDT 24
Finished Jul 17 06:09:32 PM PDT 24
Peak memory 256896 kb
Host smart-f00fab5a-9e0e-4877-bb20-0be3a9532f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32599
04038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3259904038
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1868977419
Short name T208
Test name
Test status
Simulation time 191378389387 ps
CPU time 1257.69 seconds
Started Jul 17 06:08:59 PM PDT 24
Finished Jul 17 06:29:57 PM PDT 24
Peak memory 289828 kb
Host smart-088dcf8c-25c2-49f3-b17d-1670c0af5c62
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868977419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1868977419
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3735300127
Short name T58
Test name
Test status
Simulation time 32325647856 ps
CPU time 2857.87 seconds
Started Jul 17 06:09:37 PM PDT 24
Finished Jul 17 06:57:15 PM PDT 24
Peak memory 322564 kb
Host smart-63ef5905-fd82-4bd2-ba2a-8cb2f9a986e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735300127 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3735300127
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3556404332
Short name T346
Test name
Test status
Simulation time 52529607598 ps
CPU time 1303.73 seconds
Started Jul 17 06:09:04 PM PDT 24
Finished Jul 17 06:30:49 PM PDT 24
Peak memory 289276 kb
Host smart-6b1e28ac-9fab-4ebd-a445-9bba470721eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556404332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3556404332
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1721000771
Short name T34
Test name
Test status
Simulation time 2166799739 ps
CPU time 86.96 seconds
Started Jul 17 06:09:05 PM PDT 24
Finished Jul 17 06:10:34 PM PDT 24
Peak memory 256516 kb
Host smart-8524d83d-1895-4d2c-8eaa-e3d163087848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17210
00771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1721000771
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2132772761
Short name T23
Test name
Test status
Simulation time 660884996 ps
CPU time 36.6 seconds
Started Jul 17 06:08:52 PM PDT 24
Finished Jul 17 06:09:33 PM PDT 24
Peak memory 248688 kb
Host smart-31402c96-538b-42e8-a551-3ebae16c1620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21327
72761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2132772761
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.648225384
Short name T679
Test name
Test status
Simulation time 32686616338 ps
CPU time 1759.1 seconds
Started Jul 17 06:09:08 PM PDT 24
Finished Jul 17 06:38:29 PM PDT 24
Peak memory 273328 kb
Host smart-d1b1222d-5eb0-4251-8bd6-c2d351128905
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648225384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.648225384
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2104621804
Short name T484
Test name
Test status
Simulation time 261942752881 ps
CPU time 3330.92 seconds
Started Jul 17 06:09:37 PM PDT 24
Finished Jul 17 07:05:09 PM PDT 24
Peak memory 289212 kb
Host smart-71c26947-d32b-4e6b-9749-706fa463849e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104621804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2104621804
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.447169207
Short name T310
Test name
Test status
Simulation time 9227653696 ps
CPU time 377.34 seconds
Started Jul 17 06:08:54 PM PDT 24
Finished Jul 17 06:15:14 PM PDT 24
Peak memory 248796 kb
Host smart-720c1955-251e-42a1-81c7-121ed8dd625a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447169207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.447169207
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2391593020
Short name T517
Test name
Test status
Simulation time 641781762 ps
CPU time 45.2 seconds
Started Jul 17 06:09:03 PM PDT 24
Finished Jul 17 06:09:50 PM PDT 24
Peak memory 248900 kb
Host smart-51716842-befa-4f97-a90d-74a2ccbca027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23915
93020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2391593020
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2868638050
Short name T676
Test name
Test status
Simulation time 264239935 ps
CPU time 5.61 seconds
Started Jul 17 06:09:38 PM PDT 24
Finished Jul 17 06:09:44 PM PDT 24
Peak memory 240452 kb
Host smart-8fe2a436-01e4-4609-afb2-8a2ea154bfd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28686
38050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2868638050
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3873223269
Short name T594
Test name
Test status
Simulation time 129858081 ps
CPU time 5.46 seconds
Started Jul 17 06:08:43 PM PDT 24
Finished Jul 17 06:08:57 PM PDT 24
Peak memory 240040 kb
Host smart-a78c65e0-800c-49e8-8a30-f756f1cec6c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38732
23269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3873223269
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1737759682
Short name T678
Test name
Test status
Simulation time 320344546 ps
CPU time 18.33 seconds
Started Jul 17 06:08:49 PM PDT 24
Finished Jul 17 06:09:13 PM PDT 24
Peak memory 248720 kb
Host smart-3a094087-6010-4033-825a-8bd38dca773d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17377
59682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1737759682
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3042690343
Short name T649
Test name
Test status
Simulation time 3190584666 ps
CPU time 191.76 seconds
Started Jul 17 06:08:45 PM PDT 24
Finished Jul 17 06:12:04 PM PDT 24
Peak memory 256988 kb
Host smart-491b6689-cf29-48af-8bd5-87b346848748
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042690343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3042690343
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2234911678
Short name T59
Test name
Test status
Simulation time 25418993403 ps
CPU time 1416.08 seconds
Started Jul 17 06:09:07 PM PDT 24
Finished Jul 17 06:32:45 PM PDT 24
Peak memory 289252 kb
Host smart-60586acd-2569-4fc7-a0d9-7feb3b3f0c14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234911678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2234911678
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.193056311
Short name T585
Test name
Test status
Simulation time 462937389 ps
CPU time 58.49 seconds
Started Jul 17 06:08:52 PM PDT 24
Finished Jul 17 06:09:54 PM PDT 24
Peak memory 256404 kb
Host smart-cc25010d-7169-480e-87b7-f865f9090d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19305
6311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.193056311
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2980066729
Short name T494
Test name
Test status
Simulation time 63984447 ps
CPU time 5.58 seconds
Started Jul 17 06:09:08 PM PDT 24
Finished Jul 17 06:09:15 PM PDT 24
Peak memory 248664 kb
Host smart-b7e318be-08ca-4d04-babd-3b95fdbe7115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29800
66729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2980066729
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3472802584
Short name T599
Test name
Test status
Simulation time 15353354240 ps
CPU time 872.87 seconds
Started Jul 17 06:09:05 PM PDT 24
Finished Jul 17 06:23:40 PM PDT 24
Peak memory 272704 kb
Host smart-faffff2d-27d7-4fdb-8365-3ea6edac5464
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472802584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3472802584
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3189623678
Short name T543
Test name
Test status
Simulation time 58521217209 ps
CPU time 1931.38 seconds
Started Jul 17 06:09:06 PM PDT 24
Finished Jul 17 06:41:20 PM PDT 24
Peak memory 273344 kb
Host smart-deadac97-004f-446e-b656-c8fd94d2fedd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189623678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3189623678
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1010385040
Short name T506
Test name
Test status
Simulation time 31959724267 ps
CPU time 627.34 seconds
Started Jul 17 06:09:38 PM PDT 24
Finished Jul 17 06:20:06 PM PDT 24
Peak memory 255408 kb
Host smart-e996eadf-c8ae-4c83-ba37-0b5a9c662899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010385040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1010385040
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3137838791
Short name T698
Test name
Test status
Simulation time 750700253 ps
CPU time 28.56 seconds
Started Jul 17 06:09:03 PM PDT 24
Finished Jul 17 06:09:33 PM PDT 24
Peak memory 248668 kb
Host smart-89feaa58-8877-4477-b469-2eb01247ab2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31378
38791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3137838791
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2748950178
Short name T706
Test name
Test status
Simulation time 946400920 ps
CPU time 49.54 seconds
Started Jul 17 06:09:03 PM PDT 24
Finished Jul 17 06:09:54 PM PDT 24
Peak memory 256352 kb
Host smart-e86a5e69-3d5e-483d-a93b-53c28ea55c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27489
50178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2748950178
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.4123690050
Short name T245
Test name
Test status
Simulation time 243520303 ps
CPU time 34.52 seconds
Started Jul 17 06:09:05 PM PDT 24
Finished Jul 17 06:09:41 PM PDT 24
Peak memory 256476 kb
Host smart-679f8285-4dd3-44a3-bbc9-e2b7075fb5de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41236
90050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.4123690050
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3950050339
Short name T417
Test name
Test status
Simulation time 311850910 ps
CPU time 9.78 seconds
Started Jul 17 06:09:07 PM PDT 24
Finished Jul 17 06:09:19 PM PDT 24
Peak memory 254772 kb
Host smart-50f66305-fa2d-48e2-b1d9-f4e492a55b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39500
50339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3950050339
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3400275471
Short name T251
Test name
Test status
Simulation time 236614838646 ps
CPU time 1474.96 seconds
Started Jul 17 06:08:52 PM PDT 24
Finished Jul 17 06:33:31 PM PDT 24
Peak memory 289788 kb
Host smart-7cdd3e6c-6986-4c0d-af72-63ec810d8456
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400275471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3400275471
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1417375353
Short name T46
Test name
Test status
Simulation time 157004580952 ps
CPU time 2401.51 seconds
Started Jul 17 06:09:05 PM PDT 24
Finished Jul 17 06:49:08 PM PDT 24
Peak memory 289836 kb
Host smart-54503a22-40a6-45dc-8361-caca7290f4e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417375353 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1417375353
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.909975454
Short name T203
Test name
Test status
Simulation time 16968329 ps
CPU time 2.36 seconds
Started Jul 17 06:07:56 PM PDT 24
Finished Jul 17 06:08:00 PM PDT 24
Peak memory 248964 kb
Host smart-c6586791-db35-40ff-9712-9ad190419ff3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=909975454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.909975454
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.445067862
Short name T6
Test name
Test status
Simulation time 23965180399 ps
CPU time 1337.93 seconds
Started Jul 17 06:07:59 PM PDT 24
Finished Jul 17 06:30:19 PM PDT 24
Peak memory 280988 kb
Host smart-9f3dd450-83c8-4fa5-af42-da19c1bdeaa9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445067862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.445067862
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3711133499
Short name T638
Test name
Test status
Simulation time 3039390760 ps
CPU time 9.5 seconds
Started Jul 17 06:08:05 PM PDT 24
Finished Jul 17 06:08:16 PM PDT 24
Peak memory 248812 kb
Host smart-31e81201-39c3-4709-8665-4cf5e26244d3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3711133499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3711133499
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2912210747
Short name T431
Test name
Test status
Simulation time 14788349280 ps
CPU time 220.57 seconds
Started Jul 17 06:07:56 PM PDT 24
Finished Jul 17 06:11:38 PM PDT 24
Peak memory 256028 kb
Host smart-60ad722e-652f-46a3-824e-56f2b3e0114f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29122
10747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2912210747
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1850110973
Short name T674
Test name
Test status
Simulation time 402366494 ps
CPU time 38.65 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:09:30 PM PDT 24
Peak memory 256252 kb
Host smart-11a49d10-4bed-4593-ba13-650f5e5525da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18501
10973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1850110973
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2920482162
Short name T575
Test name
Test status
Simulation time 7363503712 ps
CPU time 669.09 seconds
Started Jul 17 06:08:00 PM PDT 24
Finished Jul 17 06:19:11 PM PDT 24
Peak memory 272772 kb
Host smart-059853a3-1ab2-4c7f-829a-6757f35763de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920482162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2920482162
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2448654043
Short name T273
Test name
Test status
Simulation time 22137020457 ps
CPU time 1172.76 seconds
Started Jul 17 06:07:56 PM PDT 24
Finished Jul 17 06:27:31 PM PDT 24
Peak memory 265252 kb
Host smart-2b22fe06-e018-4d22-bd3b-5cf8e8e0cd67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448654043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2448654043
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2540297111
Short name T623
Test name
Test status
Simulation time 9171480031 ps
CPU time 389.92 seconds
Started Jul 17 06:07:56 PM PDT 24
Finished Jul 17 06:14:27 PM PDT 24
Peak memory 248828 kb
Host smart-df5c4527-de85-4ab6-9cd7-838c78219503
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540297111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2540297111
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1210185393
Short name T118
Test name
Test status
Simulation time 2602952278 ps
CPU time 34.78 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 06:08:34 PM PDT 24
Peak memory 255616 kb
Host smart-8f52c343-8439-4921-b9f6-18e0cc289f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12101
85393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1210185393
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2648979044
Short name T263
Test name
Test status
Simulation time 217739132 ps
CPU time 14.02 seconds
Started Jul 17 06:08:06 PM PDT 24
Finished Jul 17 06:08:22 PM PDT 24
Peak memory 248684 kb
Host smart-631922ff-b9b9-4a5c-87db-fe5a35009e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26489
79044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2648979044
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1007239052
Short name T12
Test name
Test status
Simulation time 975341028 ps
CPU time 46.41 seconds
Started Jul 17 06:07:57 PM PDT 24
Finished Jul 17 06:08:45 PM PDT 24
Peak memory 273240 kb
Host smart-526416b0-4ffd-4d34-867e-f6a4ebbc7a73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1007239052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1007239052
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1008159818
Short name T441
Test name
Test status
Simulation time 468309851 ps
CPU time 23.43 seconds
Started Jul 17 06:08:16 PM PDT 24
Finished Jul 17 06:08:41 PM PDT 24
Peak memory 248012 kb
Host smart-9b8871cc-95fa-4f4f-8470-9f2096f6a299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10081
59818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1008159818
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.792039264
Short name T504
Test name
Test status
Simulation time 2008354663 ps
CPU time 53.44 seconds
Started Jul 17 06:07:57 PM PDT 24
Finished Jul 17 06:08:52 PM PDT 24
Peak memory 256340 kb
Host smart-43018de6-5705-4a2e-bb65-1fbbfa88c27d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79203
9264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.792039264
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.867649826
Short name T373
Test name
Test status
Simulation time 39129877302 ps
CPU time 977.08 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 06:24:17 PM PDT 24
Peak memory 289772 kb
Host smart-78bf061e-c672-4ece-af7f-0fd3febca078
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867649826 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.867649826
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2363890987
Short name T109
Test name
Test status
Simulation time 26469965177 ps
CPU time 591.41 seconds
Started Jul 17 06:09:06 PM PDT 24
Finished Jul 17 06:19:00 PM PDT 24
Peak memory 273228 kb
Host smart-1709edbd-b778-4379-9c5a-c57c6f8f17b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363890987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2363890987
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1604103024
Short name T210
Test name
Test status
Simulation time 1238033667 ps
CPU time 99.69 seconds
Started Jul 17 06:09:08 PM PDT 24
Finished Jul 17 06:10:49 PM PDT 24
Peak memory 256864 kb
Host smart-ff57ba96-2051-4242-99ac-0698364a9c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16041
03024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1604103024
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3075150772
Short name T492
Test name
Test status
Simulation time 206313043 ps
CPU time 20.18 seconds
Started Jul 17 06:09:38 PM PDT 24
Finished Jul 17 06:09:59 PM PDT 24
Peak memory 248728 kb
Host smart-cb09f626-ff80-4521-a2d9-a862f1a24862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30751
50772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3075150772
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3189421944
Short name T597
Test name
Test status
Simulation time 46835161443 ps
CPU time 886.09 seconds
Started Jul 17 06:08:51 PM PDT 24
Finished Jul 17 06:23:42 PM PDT 24
Peak memory 273288 kb
Host smart-006bacb5-b88f-43bd-b6ca-c0785eb435e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189421944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3189421944
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2686623860
Short name T684
Test name
Test status
Simulation time 132077443048 ps
CPU time 2294.86 seconds
Started Jul 17 06:09:37 PM PDT 24
Finished Jul 17 06:47:53 PM PDT 24
Peak memory 289784 kb
Host smart-b4d7ebf1-3311-437a-9f06-d6dfb51ec15e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686623860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2686623860
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.4071063353
Short name T605
Test name
Test status
Simulation time 8260903999 ps
CPU time 321.73 seconds
Started Jul 17 06:09:05 PM PDT 24
Finished Jul 17 06:14:29 PM PDT 24
Peak memory 248804 kb
Host smart-7b54c229-0bdd-4e63-8bcf-931f124c515b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071063353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.4071063353
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1303380290
Short name T464
Test name
Test status
Simulation time 1828453350 ps
CPU time 57.96 seconds
Started Jul 17 06:09:56 PM PDT 24
Finished Jul 17 06:10:55 PM PDT 24
Peak memory 256236 kb
Host smart-9f3f81c2-8f6b-435d-af1d-c03a5d14a6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13033
80290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1303380290
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1805403609
Short name T2
Test name
Test status
Simulation time 970411537 ps
CPU time 57.95 seconds
Started Jul 17 06:09:38 PM PDT 24
Finished Jul 17 06:10:37 PM PDT 24
Peak memory 256904 kb
Host smart-11ab6acb-7711-4b33-b1e1-9de10330afaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18054
03609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1805403609
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2312342157
Short name T402
Test name
Test status
Simulation time 1133902971 ps
CPU time 20.61 seconds
Started Jul 17 06:09:03 PM PDT 24
Finished Jul 17 06:09:26 PM PDT 24
Peak memory 248256 kb
Host smart-69d81561-49a2-442b-8f34-8c1f9bcc90e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23123
42157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2312342157
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1227711572
Short name T231
Test name
Test status
Simulation time 265567296 ps
CPU time 22.76 seconds
Started Jul 17 06:09:37 PM PDT 24
Finished Jul 17 06:10:00 PM PDT 24
Peak memory 256788 kb
Host smart-4911bece-11cf-40d6-9baa-24ae187edcf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12277
11572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1227711572
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1211110756
Short name T387
Test name
Test status
Simulation time 48352457606 ps
CPU time 1345 seconds
Started Jul 17 06:08:54 PM PDT 24
Finished Jul 17 06:31:22 PM PDT 24
Peak memory 289480 kb
Host smart-c43e108a-77f5-4275-90db-48a095c70d72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211110756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1211110756
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3810545843
Short name T214
Test name
Test status
Simulation time 19232104779 ps
CPU time 192.43 seconds
Started Jul 17 06:09:02 PM PDT 24
Finished Jul 17 06:12:16 PM PDT 24
Peak memory 256480 kb
Host smart-fd660552-9dce-40ba-a93e-2b198ad15679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38105
45843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3810545843
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.424346374
Short name T529
Test name
Test status
Simulation time 10992429407 ps
CPU time 68.91 seconds
Started Jul 17 06:09:04 PM PDT 24
Finished Jul 17 06:10:15 PM PDT 24
Peak memory 248488 kb
Host smart-e8747dad-8d71-4d2c-a1f6-3d4295275e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42434
6374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.424346374
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3885345319
Short name T666
Test name
Test status
Simulation time 17856355563 ps
CPU time 1055.29 seconds
Started Jul 17 06:09:02 PM PDT 24
Finished Jul 17 06:26:38 PM PDT 24
Peak memory 273356 kb
Host smart-d2286ddf-7b48-4c5a-8adf-865304f14148
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885345319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3885345319
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3534488132
Short name T489
Test name
Test status
Simulation time 29482821649 ps
CPU time 1636.1 seconds
Started Jul 17 06:09:01 PM PDT 24
Finished Jul 17 06:36:18 PM PDT 24
Peak memory 285824 kb
Host smart-ad1b161b-2fa3-4269-9dc0-c5b0f8deeb03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534488132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3534488132
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1350502213
Short name T604
Test name
Test status
Simulation time 51859592983 ps
CPU time 536.65 seconds
Started Jul 17 06:09:05 PM PDT 24
Finished Jul 17 06:18:03 PM PDT 24
Peak memory 247768 kb
Host smart-d7774913-57a6-4d7f-b05f-ca90b7abb931
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350502213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1350502213
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3362452519
Short name T466
Test name
Test status
Simulation time 1340957226 ps
CPU time 24.32 seconds
Started Jul 17 06:09:06 PM PDT 24
Finished Jul 17 06:09:33 PM PDT 24
Peak memory 248716 kb
Host smart-203b58b8-3b0c-4c55-b72c-6c49429a1f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33624
52519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3362452519
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.276688949
Short name T344
Test name
Test status
Simulation time 1084285870 ps
CPU time 16.25 seconds
Started Jul 17 06:09:03 PM PDT 24
Finished Jul 17 06:09:21 PM PDT 24
Peak memory 248236 kb
Host smart-76ef2aa3-cf80-4aa9-a5cb-cbdf87db0431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27668
8949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.276688949
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.4136493243
Short name T616
Test name
Test status
Simulation time 1295098519 ps
CPU time 27.5 seconds
Started Jul 17 06:09:02 PM PDT 24
Finished Jul 17 06:09:31 PM PDT 24
Peak memory 247860 kb
Host smart-ecb78abd-e53a-4d4a-bdd0-4f7745396a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41364
93243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4136493243
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2182672197
Short name T66
Test name
Test status
Simulation time 1469656332 ps
CPU time 21.52 seconds
Started Jul 17 06:09:06 PM PDT 24
Finished Jul 17 06:09:30 PM PDT 24
Peak memory 256116 kb
Host smart-718bcd41-46f3-498b-bb91-25a283e29535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21826
72197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2182672197
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1573756722
Short name T105
Test name
Test status
Simulation time 107293171974 ps
CPU time 1692.32 seconds
Started Jul 17 06:08:53 PM PDT 24
Finished Jul 17 06:37:09 PM PDT 24
Peak memory 282308 kb
Host smart-845e2f54-9fcd-4ff8-b1c8-cc3efe2d4771
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573756722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1573756722
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3749691452
Short name T115
Test name
Test status
Simulation time 84760020686 ps
CPU time 1894.95 seconds
Started Jul 17 06:09:08 PM PDT 24
Finished Jul 17 06:40:45 PM PDT 24
Peak memory 273404 kb
Host smart-67239205-021e-4cde-9069-d9bd77ad3628
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749691452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3749691452
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3124558533
Short name T74
Test name
Test status
Simulation time 25704235504 ps
CPU time 255.83 seconds
Started Jul 17 06:09:00 PM PDT 24
Finished Jul 17 06:13:16 PM PDT 24
Peak memory 256476 kb
Host smart-62b649cd-b56b-4dd7-959f-e95ed593639d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31245
58533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3124558533
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1738998587
Short name T561
Test name
Test status
Simulation time 2381465574 ps
CPU time 58.57 seconds
Started Jul 17 06:09:06 PM PDT 24
Finished Jul 17 06:10:06 PM PDT 24
Peak memory 249196 kb
Host smart-596021a8-3825-4809-803e-5ba4c5445383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17389
98587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1738998587
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3925380514
Short name T319
Test name
Test status
Simulation time 24272073349 ps
CPU time 1461.87 seconds
Started Jul 17 06:09:00 PM PDT 24
Finished Jul 17 06:33:23 PM PDT 24
Peak memory 286260 kb
Host smart-27432035-641d-4b9a-8c7e-3c806f6849ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925380514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3925380514
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2286024849
Short name T312
Test name
Test status
Simulation time 20515049834 ps
CPU time 351.7 seconds
Started Jul 17 06:09:20 PM PDT 24
Finished Jul 17 06:15:13 PM PDT 24
Peak memory 255552 kb
Host smart-39040213-613e-426f-9120-a84715770f4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286024849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2286024849
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2342180362
Short name T209
Test name
Test status
Simulation time 1429897740 ps
CPU time 32.24 seconds
Started Jul 17 06:09:17 PM PDT 24
Finished Jul 17 06:09:50 PM PDT 24
Peak memory 248652 kb
Host smart-17875bac-b5a7-4aa1-a67d-e4febbd50888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23421
80362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2342180362
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2612172543
Short name T511
Test name
Test status
Simulation time 105655105 ps
CPU time 8.38 seconds
Started Jul 17 06:09:12 PM PDT 24
Finished Jul 17 06:09:21 PM PDT 24
Peak memory 252208 kb
Host smart-b6053944-a656-41cc-afb0-35e2242e16fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26121
72543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2612172543
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3622421823
Short name T534
Test name
Test status
Simulation time 2782266240 ps
CPU time 47.71 seconds
Started Jul 17 06:09:19 PM PDT 24
Finished Jul 17 06:10:07 PM PDT 24
Peak memory 256964 kb
Host smart-be463a25-8e57-4e17-bf5c-486fa98609ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36224
21823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3622421823
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.169720546
Short name T527
Test name
Test status
Simulation time 403332633 ps
CPU time 27.12 seconds
Started Jul 17 06:08:54 PM PDT 24
Finished Jul 17 06:09:24 PM PDT 24
Peak memory 256848 kb
Host smart-886bee19-d477-4e31-9c92-de769c65e627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16972
0546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.169720546
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3616665987
Short name T61
Test name
Test status
Simulation time 75545841892 ps
CPU time 1790.69 seconds
Started Jul 17 06:08:59 PM PDT 24
Finished Jul 17 06:38:51 PM PDT 24
Peak memory 289504 kb
Host smart-c3caf676-0585-439d-bd70-a34ef61832eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616665987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3616665987
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1142954737
Short name T225
Test name
Test status
Simulation time 27235918378 ps
CPU time 1839.88 seconds
Started Jul 17 06:09:03 PM PDT 24
Finished Jul 17 06:39:44 PM PDT 24
Peak memory 289768 kb
Host smart-461d868c-30bf-41a7-b3dc-2ccba9c08e29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142954737 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1142954737
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.115571890
Short name T414
Test name
Test status
Simulation time 17045562399 ps
CPU time 1401.71 seconds
Started Jul 17 06:09:19 PM PDT 24
Finished Jul 17 06:32:42 PM PDT 24
Peak memory 287888 kb
Host smart-783ef98a-c634-4c93-b1fa-41bf329b587b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115571890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.115571890
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.641538132
Short name T416
Test name
Test status
Simulation time 644798263 ps
CPU time 36.55 seconds
Started Jul 17 06:09:00 PM PDT 24
Finished Jul 17 06:09:38 PM PDT 24
Peak memory 256164 kb
Host smart-a74e5a59-c174-4abe-8291-018357e30267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64153
8132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.641538132
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.4063917600
Short name T663
Test name
Test status
Simulation time 361806748 ps
CPU time 20.9 seconds
Started Jul 17 06:09:09 PM PDT 24
Finished Jul 17 06:09:31 PM PDT 24
Peak memory 248208 kb
Host smart-1635abe3-783d-4611-bb8f-85e78530e833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40639
17600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.4063917600
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1622767779
Short name T212
Test name
Test status
Simulation time 42617909096 ps
CPU time 2377.61 seconds
Started Jul 17 06:10:32 PM PDT 24
Finished Jul 17 06:50:10 PM PDT 24
Peak memory 288908 kb
Host smart-feb15b66-0b1c-4e6a-94de-95ad550ab407
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622767779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1622767779
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2812300780
Short name T512
Test name
Test status
Simulation time 14263922369 ps
CPU time 1694.64 seconds
Started Jul 17 06:09:22 PM PDT 24
Finished Jul 17 06:37:37 PM PDT 24
Peak memory 289016 kb
Host smart-51a4c899-5b37-433f-a222-bd78b3dad18e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812300780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2812300780
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.4116417472
Short name T301
Test name
Test status
Simulation time 2823639694 ps
CPU time 126.51 seconds
Started Jul 17 06:09:19 PM PDT 24
Finished Jul 17 06:11:26 PM PDT 24
Peak memory 248624 kb
Host smart-9e79c699-f60d-4472-8776-962272b90907
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116417472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.4116417472
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.405048735
Short name T495
Test name
Test status
Simulation time 828652071 ps
CPU time 18.48 seconds
Started Jul 17 06:09:11 PM PDT 24
Finished Jul 17 06:09:31 PM PDT 24
Peak memory 256372 kb
Host smart-736bf6c1-4d38-487c-b209-0c45a370f550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40504
8735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.405048735
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.816171754
Short name T103
Test name
Test status
Simulation time 7138054795 ps
CPU time 68.3 seconds
Started Jul 17 06:09:03 PM PDT 24
Finished Jul 17 06:10:13 PM PDT 24
Peak memory 248716 kb
Host smart-c3530150-fbd7-437f-9fd3-6c767f92aa9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81617
1754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.816171754
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.942574343
Short name T447
Test name
Test status
Simulation time 410824033 ps
CPU time 17.02 seconds
Started Jul 17 06:09:39 PM PDT 24
Finished Jul 17 06:09:56 PM PDT 24
Peak memory 255932 kb
Host smart-7fd4510e-3f92-4483-ad3d-9508a9fa1390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94257
4343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.942574343
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.252492132
Short name T22
Test name
Test status
Simulation time 11861484537 ps
CPU time 910.42 seconds
Started Jul 17 06:09:19 PM PDT 24
Finished Jul 17 06:24:30 PM PDT 24
Peak memory 289536 kb
Host smart-4b7ac306-aa0a-463b-9fc8-01686f847260
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252492132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.252492132
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2026397718
Short name T394
Test name
Test status
Simulation time 46651474584 ps
CPU time 1195.81 seconds
Started Jul 17 06:09:20 PM PDT 24
Finished Jul 17 06:29:17 PM PDT 24
Peak memory 289276 kb
Host smart-6a4fa7f0-d07b-4674-bf81-0095acfe8734
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026397718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2026397718
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1790371992
Short name T683
Test name
Test status
Simulation time 2125225277 ps
CPU time 56.73 seconds
Started Jul 17 06:09:20 PM PDT 24
Finished Jul 17 06:10:18 PM PDT 24
Peak memory 256388 kb
Host smart-da6495a5-364c-440f-96aa-27afb35d550a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17903
71992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1790371992
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1516461494
Short name T354
Test name
Test status
Simulation time 896280881 ps
CPU time 54.77 seconds
Started Jul 17 06:09:18 PM PDT 24
Finished Jul 17 06:10:14 PM PDT 24
Peak memory 248212 kb
Host smart-b6e01d2d-bc8e-4d03-8d5b-00fb3276bec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15164
61494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1516461494
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2997491029
Short name T282
Test name
Test status
Simulation time 38718956676 ps
CPU time 1711.62 seconds
Started Jul 17 06:09:20 PM PDT 24
Finished Jul 17 06:37:54 PM PDT 24
Peak memory 289216 kb
Host smart-083a2cdb-6368-4861-996d-7a4a00d3fedf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997491029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2997491029
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1916072855
Short name T96
Test name
Test status
Simulation time 90160980346 ps
CPU time 1250.37 seconds
Started Jul 17 06:09:19 PM PDT 24
Finished Jul 17 06:30:11 PM PDT 24
Peak memory 285468 kb
Host smart-ef80ba75-cc9f-436d-95f4-8e52ca02ced1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916072855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1916072855
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3404038477
Short name T618
Test name
Test status
Simulation time 1411260405 ps
CPU time 60.83 seconds
Started Jul 17 06:09:22 PM PDT 24
Finished Jul 17 06:10:23 PM PDT 24
Peak memory 248680 kb
Host smart-e775b134-efe4-4f8b-9f59-dafddd6cd9dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404038477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3404038477
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1153654994
Short name T537
Test name
Test status
Simulation time 3363590365 ps
CPU time 37.99 seconds
Started Jul 17 06:09:17 PM PDT 24
Finished Jul 17 06:09:56 PM PDT 24
Peak memory 256260 kb
Host smart-ed37efb3-d694-4c3d-a42f-7d31661d94cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11536
54994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1153654994
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.74074309
Short name T342
Test name
Test status
Simulation time 245925199 ps
CPU time 18.17 seconds
Started Jul 17 06:09:18 PM PDT 24
Finished Jul 17 06:09:37 PM PDT 24
Peak memory 248212 kb
Host smart-3496af7d-7676-4697-b39b-f07610af781a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74074
309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.74074309
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3795220067
Short name T694
Test name
Test status
Simulation time 276628032 ps
CPU time 29.41 seconds
Started Jul 17 06:10:23 PM PDT 24
Finished Jul 17 06:10:53 PM PDT 24
Peak memory 248240 kb
Host smart-d8357c65-6f28-45c5-bc89-96dd1a903972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37952
20067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3795220067
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1857594048
Short name T454
Test name
Test status
Simulation time 1088252425 ps
CPU time 59.98 seconds
Started Jul 17 06:09:20 PM PDT 24
Finished Jul 17 06:10:21 PM PDT 24
Peak memory 256772 kb
Host smart-b5a20e88-68d7-4d25-a9bd-06879fc06286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18575
94048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1857594048
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.4148133954
Short name T224
Test name
Test status
Simulation time 77334329160 ps
CPU time 2116.45 seconds
Started Jul 17 06:09:23 PM PDT 24
Finished Jul 17 06:44:40 PM PDT 24
Peak memory 289852 kb
Host smart-e3882353-5b41-4dfc-9fd8-2628d19d439e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148133954 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.4148133954
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3863162564
Short name T428
Test name
Test status
Simulation time 53267157544 ps
CPU time 943.08 seconds
Started Jul 17 06:09:20 PM PDT 24
Finished Jul 17 06:25:05 PM PDT 24
Peak memory 281480 kb
Host smart-20a93950-047c-4154-bef2-c686274d7dbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863162564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3863162564
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.930784760
Short name T412
Test name
Test status
Simulation time 25655552561 ps
CPU time 347.65 seconds
Started Jul 17 06:10:31 PM PDT 24
Finished Jul 17 06:16:20 PM PDT 24
Peak memory 256252 kb
Host smart-417fcf01-8a8e-4f0e-9bdd-2b4a7d55551a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93078
4760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.930784760
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2221683022
Short name T533
Test name
Test status
Simulation time 522995528 ps
CPU time 20.48 seconds
Started Jul 17 06:09:19 PM PDT 24
Finished Jul 17 06:09:41 PM PDT 24
Peak memory 256160 kb
Host smart-b9327423-bd71-4649-acde-2938ff7b1367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22216
83022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2221683022
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.147391385
Short name T285
Test name
Test status
Simulation time 13014643505 ps
CPU time 1182.24 seconds
Started Jul 17 06:09:20 PM PDT 24
Finished Jul 17 06:29:04 PM PDT 24
Peak memory 283796 kb
Host smart-3f1f4a0a-6d73-4318-9e6b-62e33ec7104f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147391385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.147391385
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1203630321
Short name T100
Test name
Test status
Simulation time 56261953236 ps
CPU time 1611.66 seconds
Started Jul 17 06:09:18 PM PDT 24
Finished Jul 17 06:36:11 PM PDT 24
Peak memory 273296 kb
Host smart-7462f0c1-83a9-47f5-99d5-ed1a239850a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203630321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1203630321
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.916357770
Short name T528
Test name
Test status
Simulation time 140390156 ps
CPU time 16.99 seconds
Started Jul 17 06:09:19 PM PDT 24
Finished Jul 17 06:09:38 PM PDT 24
Peak memory 248736 kb
Host smart-d7d9e286-78ed-49d5-9a3c-ecd4a2bbadd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91635
7770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.916357770
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.551023474
Short name T586
Test name
Test status
Simulation time 278119193 ps
CPU time 19.55 seconds
Started Jul 17 06:09:23 PM PDT 24
Finished Jul 17 06:09:43 PM PDT 24
Peak memory 248264 kb
Host smart-1a5a75c8-59d6-4692-bbc0-3cb3f49e94e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55102
3474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.551023474
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.32050108
Short name T233
Test name
Test status
Simulation time 2107834539 ps
CPU time 26.35 seconds
Started Jul 17 06:09:19 PM PDT 24
Finished Jul 17 06:09:47 PM PDT 24
Peak memory 256052 kb
Host smart-d512bc76-357a-4449-a561-b45a67994b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32050
108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.32050108
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3068469660
Short name T620
Test name
Test status
Simulation time 790723564 ps
CPU time 26.12 seconds
Started Jul 17 06:09:19 PM PDT 24
Finished Jul 17 06:09:47 PM PDT 24
Peak memory 248696 kb
Host smart-805ddcfb-a226-436c-8a61-09d6da21ebb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30684
69660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3068469660
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3717368260
Short name T532
Test name
Test status
Simulation time 22255644656 ps
CPU time 2163.48 seconds
Started Jul 17 06:10:07 PM PDT 24
Finished Jul 17 06:46:11 PM PDT 24
Peak memory 289820 kb
Host smart-d3dd59e6-b510-463f-8c50-ae7c4e99ab94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717368260 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3717368260
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3102739218
Short name T16
Test name
Test status
Simulation time 14616777984 ps
CPU time 1075.16 seconds
Started Jul 17 06:09:30 PM PDT 24
Finished Jul 17 06:27:27 PM PDT 24
Peak memory 282840 kb
Host smart-e32f7673-c3aa-4166-a99b-d3265f35d1d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102739218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3102739218
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.173565139
Short name T603
Test name
Test status
Simulation time 18404645839 ps
CPU time 270.94 seconds
Started Jul 17 06:09:32 PM PDT 24
Finished Jul 17 06:14:04 PM PDT 24
Peak memory 256540 kb
Host smart-a76aa883-bbf7-44c4-af8e-e15c6806e80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17356
5139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.173565139
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.4277086559
Short name T376
Test name
Test status
Simulation time 352536814 ps
CPU time 6.19 seconds
Started Jul 17 06:09:33 PM PDT 24
Finished Jul 17 06:09:41 PM PDT 24
Peak memory 239948 kb
Host smart-362aaa9a-c1a9-4a01-be3f-e272eaa9db7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42770
86559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.4277086559
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3967694030
Short name T588
Test name
Test status
Simulation time 40246594142 ps
CPU time 2564.9 seconds
Started Jul 17 06:10:11 PM PDT 24
Finished Jul 17 06:52:57 PM PDT 24
Peak memory 288952 kb
Host smart-5761b6e6-8a30-4a03-8029-92429fb23dd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967694030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3967694030
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2870458737
Short name T508
Test name
Test status
Simulation time 62036346071 ps
CPU time 1199.25 seconds
Started Jul 17 06:09:30 PM PDT 24
Finished Jul 17 06:29:31 PM PDT 24
Peak memory 284732 kb
Host smart-17c55c7a-8c52-4c49-a142-bb81d534b8cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870458737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2870458737
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2399553682
Short name T213
Test name
Test status
Simulation time 3152799905 ps
CPU time 128.73 seconds
Started Jul 17 06:09:57 PM PDT 24
Finished Jul 17 06:12:07 PM PDT 24
Peak memory 254368 kb
Host smart-d14087da-5942-420e-adff-e0316ada4403
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399553682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2399553682
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2377521844
Short name T367
Test name
Test status
Simulation time 866712722 ps
CPU time 48.09 seconds
Started Jul 17 06:10:32 PM PDT 24
Finished Jul 17 06:11:20 PM PDT 24
Peak memory 256268 kb
Host smart-f6e8e173-416c-4c01-a15a-b4f1402c4aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23775
21844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2377521844
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3567784479
Short name T578
Test name
Test status
Simulation time 2466779836 ps
CPU time 45.2 seconds
Started Jul 17 06:09:54 PM PDT 24
Finished Jul 17 06:10:40 PM PDT 24
Peak memory 248372 kb
Host smart-3620b183-e99f-49da-a199-0455f4a1eeca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35677
84479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3567784479
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3010556374
Short name T510
Test name
Test status
Simulation time 178569994 ps
CPU time 22.39 seconds
Started Jul 17 06:09:32 PM PDT 24
Finished Jul 17 06:09:57 PM PDT 24
Peak memory 256656 kb
Host smart-7dd920ff-2cad-46da-ac29-7b3d852d89f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30105
56374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3010556374
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.928966057
Short name T465
Test name
Test status
Simulation time 3077566920 ps
CPU time 48.2 seconds
Started Jul 17 06:09:31 PM PDT 24
Finished Jul 17 06:10:20 PM PDT 24
Peak memory 256432 kb
Host smart-7d1259f7-6624-4f67-8dc7-60715492b95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92896
6057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.928966057
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2007082248
Short name T51
Test name
Test status
Simulation time 210069228271 ps
CPU time 3052.13 seconds
Started Jul 17 06:09:32 PM PDT 24
Finished Jul 17 07:00:26 PM PDT 24
Peak memory 289780 kb
Host smart-697ec213-92fd-41a6-96c0-5e304e490852
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007082248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2007082248
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2606270399
Short name T53
Test name
Test status
Simulation time 303933016828 ps
CPU time 2355 seconds
Started Jul 17 06:09:34 PM PDT 24
Finished Jul 17 06:48:51 PM PDT 24
Peak memory 286496 kb
Host smart-c1a10594-4b9a-4436-b2af-d4029b95a98e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606270399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2606270399
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1510252646
Short name T423
Test name
Test status
Simulation time 914039626 ps
CPU time 34.65 seconds
Started Jul 17 06:09:32 PM PDT 24
Finished Jul 17 06:10:09 PM PDT 24
Peak memory 256412 kb
Host smart-3b3a8317-340a-4b22-bae6-b3a56cbbfc49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15102
52646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1510252646
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4256579637
Short name T352
Test name
Test status
Simulation time 184467337 ps
CPU time 16.1 seconds
Started Jul 17 06:09:32 PM PDT 24
Finished Jul 17 06:09:50 PM PDT 24
Peak memory 255188 kb
Host smart-61540930-a5aa-4541-8d5f-1027faa7a586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42565
79637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4256579637
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2828852816
Short name T409
Test name
Test status
Simulation time 169281610116 ps
CPU time 1731.4 seconds
Started Jul 17 06:09:34 PM PDT 24
Finished Jul 17 06:38:27 PM PDT 24
Peak memory 272328 kb
Host smart-979be0d2-f956-430e-a75a-aada891b544d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828852816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2828852816
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1245376820
Short name T295
Test name
Test status
Simulation time 16947632662 ps
CPU time 173.18 seconds
Started Jul 17 06:09:33 PM PDT 24
Finished Jul 17 06:12:28 PM PDT 24
Peak memory 248732 kb
Host smart-53f0c7f5-d082-4e07-8cb5-6f03f3751b2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245376820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1245376820
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3176547529
Short name T356
Test name
Test status
Simulation time 147464784 ps
CPU time 15.45 seconds
Started Jul 17 06:09:34 PM PDT 24
Finished Jul 17 06:09:51 PM PDT 24
Peak memory 248672 kb
Host smart-b8511a22-7c04-4ca2-8fe7-66dd822b1e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31765
47529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3176547529
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1937747808
Short name T664
Test name
Test status
Simulation time 2625321157 ps
CPU time 48.39 seconds
Started Jul 17 06:09:28 PM PDT 24
Finished Jul 17 06:10:17 PM PDT 24
Peak memory 257236 kb
Host smart-fa748108-459d-4651-ad94-ecb2fdce4539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19377
47808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1937747808
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3204790220
Short name T87
Test name
Test status
Simulation time 761929755 ps
CPU time 46.13 seconds
Started Jul 17 06:09:33 PM PDT 24
Finished Jul 17 06:10:21 PM PDT 24
Peak memory 249056 kb
Host smart-02d73eac-c1a9-4663-8fa8-6bbbcd7423da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047
90220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3204790220
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1726689084
Short name T440
Test name
Test status
Simulation time 548087910 ps
CPU time 36.55 seconds
Started Jul 17 06:09:33 PM PDT 24
Finished Jul 17 06:10:11 PM PDT 24
Peak memory 256848 kb
Host smart-828c3742-181b-49ae-a634-d164496828d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17266
89084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1726689084
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.905153546
Short name T614
Test name
Test status
Simulation time 54240551303 ps
CPU time 1657.05 seconds
Started Jul 17 06:09:34 PM PDT 24
Finished Jul 17 06:37:12 PM PDT 24
Peak memory 289816 kb
Host smart-36b60172-00fd-4db5-8162-2bcdb31295da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905153546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.905153546
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.4224921159
Short name T190
Test name
Test status
Simulation time 73508814124 ps
CPU time 6887.71 seconds
Started Jul 17 06:10:55 PM PDT 24
Finished Jul 17 08:05:44 PM PDT 24
Peak memory 354732 kb
Host smart-d73d6773-59fe-4e27-9bea-a39d8279b47b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224921159 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.4224921159
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3480646492
Short name T427
Test name
Test status
Simulation time 448358497 ps
CPU time 29.37 seconds
Started Jul 17 06:10:12 PM PDT 24
Finished Jul 17 06:10:43 PM PDT 24
Peak memory 256352 kb
Host smart-ea1140c7-9a6e-450b-bbff-63c11d64afb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34806
46492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3480646492
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2177561439
Short name T79
Test name
Test status
Simulation time 290096543 ps
CPU time 26.5 seconds
Started Jul 17 06:09:35 PM PDT 24
Finished Jul 17 06:10:03 PM PDT 24
Peak memory 249268 kb
Host smart-fb3f59e7-4828-41c2-846d-b6651a7494e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21775
61439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2177561439
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.393007313
Short name T317
Test name
Test status
Simulation time 157209551327 ps
CPU time 1462.94 seconds
Started Jul 17 06:09:29 PM PDT 24
Finished Jul 17 06:33:53 PM PDT 24
Peak memory 273428 kb
Host smart-eebd4e51-5f55-43fc-a071-ed0d0ee8f6b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393007313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.393007313
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3186362941
Short name T587
Test name
Test status
Simulation time 54217951908 ps
CPU time 1339.97 seconds
Started Jul 17 06:09:33 PM PDT 24
Finished Jul 17 06:31:55 PM PDT 24
Peak memory 289572 kb
Host smart-9e9900de-7c94-49c3-9775-8d6e568caf98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186362941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3186362941
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2637487506
Short name T311
Test name
Test status
Simulation time 41144490447 ps
CPU time 418.58 seconds
Started Jul 17 06:09:32 PM PDT 24
Finished Jul 17 06:16:32 PM PDT 24
Peak memory 248676 kb
Host smart-e9eb5922-bb51-4cd0-acb7-b18fa12fa217
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637487506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2637487506
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1586965281
Short name T353
Test name
Test status
Simulation time 1505632746 ps
CPU time 48.99 seconds
Started Jul 17 06:10:35 PM PDT 24
Finished Jul 17 06:11:25 PM PDT 24
Peak memory 256148 kb
Host smart-f212f6ec-4c51-4b1c-a3e6-3f109025d542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15869
65281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1586965281
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3793456116
Short name T71
Test name
Test status
Simulation time 4098593323 ps
CPU time 59.38 seconds
Started Jul 17 06:09:30 PM PDT 24
Finished Jul 17 06:10:31 PM PDT 24
Peak memory 256516 kb
Host smart-eadb587c-6bde-4a53-a468-2d43f9bb85c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37934
56116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3793456116
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.4018074503
Short name T541
Test name
Test status
Simulation time 89739325 ps
CPU time 9.6 seconds
Started Jul 17 06:09:38 PM PDT 24
Finished Jul 17 06:09:49 PM PDT 24
Peak memory 248656 kb
Host smart-c8a5885e-ff90-42c8-93c4-9d1ecf3b13fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40180
74503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.4018074503
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.601886678
Short name T558
Test name
Test status
Simulation time 558097145 ps
CPU time 20.29 seconds
Started Jul 17 06:09:32 PM PDT 24
Finished Jul 17 06:09:54 PM PDT 24
Peak memory 255956 kb
Host smart-f7e37429-011a-46aa-a846-1fbd80bc6ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60188
6678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.601886678
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3952126124
Short name T60
Test name
Test status
Simulation time 183436045849 ps
CPU time 2781.68 seconds
Started Jul 17 06:10:42 PM PDT 24
Finished Jul 17 06:57:06 PM PDT 24
Peak memory 289072 kb
Host smart-c914863e-eb7f-4ebf-b4fd-23fdbbd0056a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952126124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3952126124
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3155319010
Short name T15
Test name
Test status
Simulation time 25323545507 ps
CPU time 1333.48 seconds
Started Jul 17 06:09:32 PM PDT 24
Finished Jul 17 06:31:47 PM PDT 24
Peak memory 288680 kb
Host smart-d2740dd0-f71e-41ef-8789-ae4cd681b94d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155319010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3155319010
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1714972932
Short name T407
Test name
Test status
Simulation time 152563105 ps
CPU time 9.93 seconds
Started Jul 17 06:09:34 PM PDT 24
Finished Jul 17 06:09:45 PM PDT 24
Peak memory 247964 kb
Host smart-58185b0e-b563-458b-8032-7bc50269b8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17149
72932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1714972932
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2507776810
Short name T488
Test name
Test status
Simulation time 594996816 ps
CPU time 33.44 seconds
Started Jul 17 06:09:32 PM PDT 24
Finished Jul 17 06:10:06 PM PDT 24
Peak memory 256272 kb
Host smart-029a0e1e-ecf4-44c5-a46e-87a95a856018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25077
76810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2507776810
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.280296409
Short name T326
Test name
Test status
Simulation time 69011962048 ps
CPU time 1508.54 seconds
Started Jul 17 06:09:34 PM PDT 24
Finished Jul 17 06:34:44 PM PDT 24
Peak memory 289484 kb
Host smart-388e70c8-5e7d-42f8-aafd-90172f66ec09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280296409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.280296409
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2718949677
Short name T29
Test name
Test status
Simulation time 12562131073 ps
CPU time 757.65 seconds
Started Jul 17 06:09:33 PM PDT 24
Finished Jul 17 06:22:12 PM PDT 24
Peak memory 273368 kb
Host smart-aa026f45-4cc0-415c-a65e-8e0fe1368b50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718949677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2718949677
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3162521678
Short name T300
Test name
Test status
Simulation time 8340318551 ps
CPU time 168.78 seconds
Started Jul 17 06:09:34 PM PDT 24
Finished Jul 17 06:12:24 PM PDT 24
Peak memory 248572 kb
Host smart-0202b33f-c6d3-43a2-ac12-79c138a19e88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162521678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3162521678
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.656049761
Short name T542
Test name
Test status
Simulation time 422076704 ps
CPU time 32.46 seconds
Started Jul 17 06:10:13 PM PDT 24
Finished Jul 17 06:10:46 PM PDT 24
Peak memory 248680 kb
Host smart-8c4bd4f7-5284-4b1b-b314-65bd8fa34398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65604
9761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.656049761
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1679208542
Short name T395
Test name
Test status
Simulation time 283469233 ps
CPU time 18.44 seconds
Started Jul 17 06:10:09 PM PDT 24
Finished Jul 17 06:10:28 PM PDT 24
Peak memory 255608 kb
Host smart-ba696f8c-672a-473c-a3d1-c866437f8e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16792
08542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1679208542
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.4265923937
Short name T654
Test name
Test status
Simulation time 341974851 ps
CPU time 19.76 seconds
Started Jul 17 06:10:30 PM PDT 24
Finished Jul 17 06:10:50 PM PDT 24
Peak memory 254980 kb
Host smart-d415c23a-6544-45e5-a179-78d228d94325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42659
23937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4265923937
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3010643282
Short name T432
Test name
Test status
Simulation time 641245304 ps
CPU time 8.51 seconds
Started Jul 17 06:09:30 PM PDT 24
Finished Jul 17 06:09:40 PM PDT 24
Peak memory 248636 kb
Host smart-bf7af41f-7e75-4177-8280-0a799713e120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30106
43282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3010643282
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2163845855
Short name T114
Test name
Test status
Simulation time 61741103992 ps
CPU time 1795.59 seconds
Started Jul 17 06:10:05 PM PDT 24
Finished Jul 17 06:40:01 PM PDT 24
Peak memory 281444 kb
Host smart-bacf2012-40ec-4ba9-8b7b-c647565c9d79
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163845855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2163845855
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3072655560
Short name T265
Test name
Test status
Simulation time 75043557991 ps
CPU time 2180.16 seconds
Started Jul 17 06:09:32 PM PDT 24
Finished Jul 17 06:45:55 PM PDT 24
Peak memory 305524 kb
Host smart-59d9893c-d0ae-401f-919d-aaa4400151c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072655560 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3072655560
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1218925732
Short name T200
Test name
Test status
Simulation time 18432021 ps
CPU time 2.71 seconds
Started Jul 17 06:08:13 PM PDT 24
Finished Jul 17 06:08:16 PM PDT 24
Peak memory 248952 kb
Host smart-733d95b6-5267-4992-a55a-bb2b0562b21a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1218925732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1218925732
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1451173094
Short name T688
Test name
Test status
Simulation time 179788633892 ps
CPU time 3094.21 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 06:59:34 PM PDT 24
Peak memory 281596 kb
Host smart-4d415ebe-66f2-4768-9a93-dac8e3913ef7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451173094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1451173094
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1274519233
Short name T582
Test name
Test status
Simulation time 5554341755 ps
CPU time 59.91 seconds
Started Jul 17 06:08:13 PM PDT 24
Finished Jul 17 06:09:13 PM PDT 24
Peak memory 248728 kb
Host smart-d2ac6479-f8eb-4682-8409-46a426b71c53
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1274519233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1274519233
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1359467181
Short name T377
Test name
Test status
Simulation time 6569471003 ps
CPU time 139.24 seconds
Started Jul 17 06:07:59 PM PDT 24
Finished Jul 17 06:10:20 PM PDT 24
Peak memory 257048 kb
Host smart-deea4478-1ae5-4e37-a461-bde3ab758be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13594
67181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1359467181
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.4053077037
Short name T83
Test name
Test status
Simulation time 2484212819 ps
CPU time 39.89 seconds
Started Jul 17 06:08:06 PM PDT 24
Finished Jul 17 06:08:48 PM PDT 24
Peak memory 248836 kb
Host smart-7a9a9773-ebb4-4400-80a5-2745a58ff583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40530
77037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.4053077037
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1445101688
Short name T325
Test name
Test status
Simulation time 13527748057 ps
CPU time 1234.22 seconds
Started Jul 17 06:07:57 PM PDT 24
Finished Jul 17 06:28:34 PM PDT 24
Peak memory 289168 kb
Host smart-cd7ecffa-8685-408b-838d-a5225f4c99d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445101688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1445101688
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.154733240
Short name T217
Test name
Test status
Simulation time 69956907571 ps
CPU time 1632.51 seconds
Started Jul 17 06:08:22 PM PDT 24
Finished Jul 17 06:35:36 PM PDT 24
Peak memory 288816 kb
Host smart-394b2d39-4fe7-4bb5-8ea7-d0607a6bf406
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154733240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.154733240
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1392881906
Short name T230
Test name
Test status
Simulation time 7914022044 ps
CPU time 312.36 seconds
Started Jul 17 06:08:25 PM PDT 24
Finished Jul 17 06:13:39 PM PDT 24
Peak memory 248800 kb
Host smart-cad755b8-2a1d-47b5-9e74-326668f77f5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392881906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1392881906
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3865974817
Short name T557
Test name
Test status
Simulation time 6893318314 ps
CPU time 35.09 seconds
Started Jul 17 06:08:05 PM PDT 24
Finished Jul 17 06:08:41 PM PDT 24
Peak memory 256568 kb
Host smart-8fb128ef-2ec8-4041-986c-31eac54b9309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38659
74817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3865974817
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1091204431
Short name T675
Test name
Test status
Simulation time 653097263 ps
CPU time 34.67 seconds
Started Jul 17 06:08:18 PM PDT 24
Finished Jul 17 06:08:55 PM PDT 24
Peak memory 248424 kb
Host smart-f8f0327e-3886-43f7-96f9-a500818ce437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10912
04431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1091204431
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2758753548
Short name T207
Test name
Test status
Simulation time 112231089 ps
CPU time 5.8 seconds
Started Jul 17 06:07:56 PM PDT 24
Finished Jul 17 06:08:03 PM PDT 24
Peak memory 248940 kb
Host smart-1851708f-99db-4046-b601-eec4aac81a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27587
53548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2758753548
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.232230848
Short name T359
Test name
Test status
Simulation time 1435821951 ps
CPU time 21.69 seconds
Started Jul 17 06:08:17 PM PDT 24
Finished Jul 17 06:08:40 PM PDT 24
Peak memory 256516 kb
Host smart-82bf652d-48c7-47cd-87ed-279e3d934476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23223
0848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.232230848
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.902694700
Short name T668
Test name
Test status
Simulation time 274116606018 ps
CPU time 4109.03 seconds
Started Jul 17 06:08:05 PM PDT 24
Finished Jul 17 07:16:36 PM PDT 24
Peak memory 297936 kb
Host smart-e9bc3f98-9945-4b54-bccc-5c7be34f99b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902694700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.902694700
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3366106415
Short name T27
Test name
Test status
Simulation time 54747055457 ps
CPU time 4535.03 seconds
Started Jul 17 06:08:10 PM PDT 24
Finished Jul 17 07:23:46 PM PDT 24
Peak memory 338768 kb
Host smart-ce88aef8-dd45-43fa-9d9a-d6f13aa3066c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366106415 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3366106415
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.767441265
Short name T194
Test name
Test status
Simulation time 26629634 ps
CPU time 2.74 seconds
Started Jul 17 06:07:59 PM PDT 24
Finished Jul 17 06:08:04 PM PDT 24
Peak memory 248952 kb
Host smart-ae4c38f6-fbc8-4a72-a105-88f19aa23ffa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=767441265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.767441265
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1184619126
Short name T222
Test name
Test status
Simulation time 39221776401 ps
CPU time 1017.6 seconds
Started Jul 17 06:08:28 PM PDT 24
Finished Jul 17 06:25:29 PM PDT 24
Peak memory 288820 kb
Host smart-e15b9c0d-12ad-4779-91a9-52a4d82b791d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184619126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1184619126
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1361263925
Short name T410
Test name
Test status
Simulation time 1408260378 ps
CPU time 12.88 seconds
Started Jul 17 06:08:22 PM PDT 24
Finished Jul 17 06:08:36 PM PDT 24
Peak memory 248660 kb
Host smart-f164fb3b-9956-4444-8e6d-f21a43816332
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1361263925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1361263925
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.845945633
Short name T689
Test name
Test status
Simulation time 2589438024 ps
CPU time 59.9 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 06:09:00 PM PDT 24
Peak memory 256540 kb
Host smart-fc219f90-76e9-491d-b39c-277903bbb50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84594
5633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.845945633
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1992396122
Short name T78
Test name
Test status
Simulation time 224083829 ps
CPU time 12.8 seconds
Started Jul 17 06:08:29 PM PDT 24
Finished Jul 17 06:08:47 PM PDT 24
Peak memory 252828 kb
Host smart-abe38600-dc29-4abb-aaf4-0b4cc849f644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19923
96122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1992396122
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.635832552
Short name T322
Test name
Test status
Simulation time 372982678960 ps
CPU time 2060.73 seconds
Started Jul 17 06:08:15 PM PDT 24
Finished Jul 17 06:42:36 PM PDT 24
Peak memory 273356 kb
Host smart-15f7f222-05c7-4ece-803b-29814c9fc26b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635832552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.635832552
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3112250751
Short name T555
Test name
Test status
Simulation time 50728370163 ps
CPU time 2528.64 seconds
Started Jul 17 06:08:11 PM PDT 24
Finished Jul 17 06:50:20 PM PDT 24
Peak memory 289784 kb
Host smart-e54358cd-62a6-4047-a23c-0afb975634e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112250751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3112250751
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3764660553
Short name T397
Test name
Test status
Simulation time 93055669 ps
CPU time 9.66 seconds
Started Jul 17 06:07:57 PM PDT 24
Finished Jul 17 06:08:09 PM PDT 24
Peak memory 254424 kb
Host smart-d0692018-7b02-45da-815c-286da5098496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37646
60553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3764660553
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.566105717
Short name T568
Test name
Test status
Simulation time 1776233847 ps
CPU time 34.1 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 06:08:33 PM PDT 24
Peak memory 256428 kb
Host smart-a1aa7713-0547-4321-b59a-5b8b0cb800c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56610
5717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.566105717
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.851703878
Short name T246
Test name
Test status
Simulation time 94096020 ps
CPU time 11.59 seconds
Started Jul 17 06:07:55 PM PDT 24
Finished Jul 17 06:08:08 PM PDT 24
Peak memory 248640 kb
Host smart-d1220b91-a6dd-45f5-a962-a3183e4e795c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85170
3878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.851703878
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3984508242
Short name T700
Test name
Test status
Simulation time 5851264196 ps
CPU time 66.53 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:09:42 PM PDT 24
Peak memory 248968 kb
Host smart-201d06ef-190a-4e94-b20d-3a4514bdc0b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39845
08242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3984508242
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2364700982
Short name T50
Test name
Test status
Simulation time 22629121820 ps
CPU time 346.91 seconds
Started Jul 17 06:07:56 PM PDT 24
Finished Jul 17 06:13:44 PM PDT 24
Peak memory 257016 kb
Host smart-fbf030aa-23ad-4ee0-a738-e20468b95dc9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364700982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2364700982
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3210602016
Short name T199
Test name
Test status
Simulation time 37083492 ps
CPU time 3.05 seconds
Started Jul 17 06:07:56 PM PDT 24
Finished Jul 17 06:08:00 PM PDT 24
Peak memory 248876 kb
Host smart-12c83540-2f25-4d83-a36e-1cecdcf3987a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3210602016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3210602016
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3868382626
Short name T437
Test name
Test status
Simulation time 38479455134 ps
CPU time 1015.92 seconds
Started Jul 17 06:08:00 PM PDT 24
Finished Jul 17 06:24:58 PM PDT 24
Peak memory 282428 kb
Host smart-c71730f2-c9e7-4f42-ad43-2b6a543f947d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868382626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3868382626
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.844635688
Short name T590
Test name
Test status
Simulation time 167713226 ps
CPU time 10.29 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 06:08:10 PM PDT 24
Peak memory 248652 kb
Host smart-a7e168c3-4c38-481a-95eb-5603efbbb8ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=844635688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.844635688
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.106656734
Short name T452
Test name
Test status
Simulation time 8020662981 ps
CPU time 217.51 seconds
Started Jul 17 06:08:05 PM PDT 24
Finished Jul 17 06:11:43 PM PDT 24
Peak memory 256884 kb
Host smart-6104b130-fb92-4104-aadb-d00fe72baaf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10665
6734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.106656734
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1673078794
Short name T469
Test name
Test status
Simulation time 471116994 ps
CPU time 28.5 seconds
Started Jul 17 06:08:01 PM PDT 24
Finished Jul 17 06:08:31 PM PDT 24
Peak memory 249236 kb
Host smart-5470ddc6-0952-4762-90cb-67a1b6280d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16730
78794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1673078794
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2825780610
Short name T576
Test name
Test status
Simulation time 143415238194 ps
CPU time 886.95 seconds
Started Jul 17 06:08:24 PM PDT 24
Finished Jul 17 06:23:12 PM PDT 24
Peak memory 289436 kb
Host smart-496143ee-1c56-4aa8-bb93-90461ab996ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825780610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2825780610
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1134207894
Short name T309
Test name
Test status
Simulation time 18935566473 ps
CPU time 399.68 seconds
Started Jul 17 06:08:12 PM PDT 24
Finished Jul 17 06:14:52 PM PDT 24
Peak memory 248820 kb
Host smart-30a11e5f-4cc3-45d8-840e-91df52d31c84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134207894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1134207894
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3210728209
Short name T471
Test name
Test status
Simulation time 483898988 ps
CPU time 9.87 seconds
Started Jul 17 06:07:55 PM PDT 24
Finished Jul 17 06:08:12 PM PDT 24
Peak memory 248708 kb
Host smart-342c1efb-89a5-4033-bf8d-49209e731bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32107
28209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3210728209
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.927960791
Short name T366
Test name
Test status
Simulation time 713373573 ps
CPU time 17.32 seconds
Started Jul 17 06:08:20 PM PDT 24
Finished Jul 17 06:08:38 PM PDT 24
Peak memory 248412 kb
Host smart-07126ed2-54d2-4300-a228-8b3cf70e855b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92796
0791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.927960791
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.975100972
Short name T629
Test name
Test status
Simulation time 3536970613 ps
CPU time 50.98 seconds
Started Jul 17 06:07:56 PM PDT 24
Finished Jul 17 06:08:48 PM PDT 24
Peak memory 256232 kb
Host smart-b47c3061-e62c-4482-9915-1424473bdc1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97510
0972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.975100972
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.865498495
Short name T279
Test name
Test status
Simulation time 798051325 ps
CPU time 36.79 seconds
Started Jul 17 06:07:56 PM PDT 24
Finished Jul 17 06:08:34 PM PDT 24
Peak memory 256840 kb
Host smart-6f913bd6-65d0-4597-aa84-4cbad9efaabc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86549
8495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.865498495
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1847369154
Short name T253
Test name
Test status
Simulation time 31077879850 ps
CPU time 2135.24 seconds
Started Jul 17 06:08:18 PM PDT 24
Finished Jul 17 06:43:55 PM PDT 24
Peak memory 287076 kb
Host smart-cfe4dfe5-acb8-4b9b-9714-15221cf8e370
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847369154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1847369154
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2022596745
Short name T57
Test name
Test status
Simulation time 16104233491 ps
CPU time 930.08 seconds
Started Jul 17 06:07:57 PM PDT 24
Finished Jul 17 06:23:29 PM PDT 24
Peak memory 273464 kb
Host smart-cad3c305-372e-4107-9aa7-2663bb637f6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022596745 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2022596745
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1866879626
Short name T42
Test name
Test status
Simulation time 145753227 ps
CPU time 3.11 seconds
Started Jul 17 06:08:22 PM PDT 24
Finished Jul 17 06:08:26 PM PDT 24
Peak memory 248952 kb
Host smart-00580f9d-7e57-47a5-88d8-de9befd84fdb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1866879626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1866879626
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1077481364
Short name T14
Test name
Test status
Simulation time 21621822292 ps
CPU time 1331.07 seconds
Started Jul 17 06:08:01 PM PDT 24
Finished Jul 17 06:30:14 PM PDT 24
Peak memory 288392 kb
Host smart-78623660-0086-4213-8c0e-dc491cdaec79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077481364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1077481364
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1267229165
Short name T661
Test name
Test status
Simulation time 1031713738 ps
CPU time 23.72 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 06:08:23 PM PDT 24
Peak memory 248664 kb
Host smart-c2d94374-83a4-4e69-b239-09139624abca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1267229165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1267229165
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3245522947
Short name T408
Test name
Test status
Simulation time 4060222307 ps
CPU time 207.42 seconds
Started Jul 17 06:08:24 PM PDT 24
Finished Jul 17 06:11:52 PM PDT 24
Peak memory 256552 kb
Host smart-2ed38875-6964-46b6-b1d2-f88f42b7a51d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32455
22947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3245522947
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3217628276
Short name T32
Test name
Test status
Simulation time 2598368964 ps
CPU time 22.05 seconds
Started Jul 17 06:08:15 PM PDT 24
Finished Jul 17 06:08:38 PM PDT 24
Peak memory 248740 kb
Host smart-8aad6fe1-7d4a-4c3b-b1ee-cc3b204de7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32176
28276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3217628276
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1675931967
Short name T232
Test name
Test status
Simulation time 80678237572 ps
CPU time 1355.24 seconds
Started Jul 17 06:08:16 PM PDT 24
Finished Jul 17 06:30:52 PM PDT 24
Peak memory 273400 kb
Host smart-ff8c7bf8-3769-4e9d-a06e-8ce13b6b1df0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675931967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1675931967
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3124115767
Short name T650
Test name
Test status
Simulation time 15825102006 ps
CPU time 1164.66 seconds
Started Jul 17 06:08:18 PM PDT 24
Finished Jul 17 06:27:45 PM PDT 24
Peak memory 288768 kb
Host smart-853058f1-1fd9-4ef0-a6c9-08584a2163e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124115767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3124115767
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3278967656
Short name T287
Test name
Test status
Simulation time 18426581080 ps
CPU time 394.45 seconds
Started Jul 17 06:08:10 PM PDT 24
Finished Jul 17 06:14:45 PM PDT 24
Peak memory 248784 kb
Host smart-91271ce5-9dd8-427e-8b66-7b2b7bd16ce1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278967656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3278967656
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1860066362
Short name T369
Test name
Test status
Simulation time 197491966 ps
CPU time 12.88 seconds
Started Jul 17 06:07:58 PM PDT 24
Finished Jul 17 06:08:12 PM PDT 24
Peak memory 248668 kb
Host smart-7eff0cee-f71a-46e6-b5a7-190606275c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18600
66362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1860066362
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1950141670
Short name T19
Test name
Test status
Simulation time 770696717 ps
CPU time 32.39 seconds
Started Jul 17 06:08:21 PM PDT 24
Finished Jul 17 06:08:54 PM PDT 24
Peak memory 248692 kb
Host smart-b915ec72-8409-45c0-89e0-9236a70daefa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19501
41670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1950141670
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3861106950
Short name T73
Test name
Test status
Simulation time 788415489 ps
CPU time 51.89 seconds
Started Jul 17 06:08:30 PM PDT 24
Finished Jul 17 06:09:28 PM PDT 24
Peak memory 249728 kb
Host smart-e1a63fd2-a953-467b-ab7e-5d322b12dad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38611
06950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3861106950
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.4287935232
Short name T702
Test name
Test status
Simulation time 3935683266 ps
CPU time 28.48 seconds
Started Jul 17 06:08:15 PM PDT 24
Finished Jul 17 06:08:44 PM PDT 24
Peak memory 248816 kb
Host smart-ab91a7f2-221a-4d5c-8bd5-b6304417b2c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42879
35232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.4287935232
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3893101553
Short name T505
Test name
Test status
Simulation time 5336833785 ps
CPU time 71.69 seconds
Started Jul 17 06:08:00 PM PDT 24
Finished Jul 17 06:09:13 PM PDT 24
Peak memory 256960 kb
Host smart-8517f98e-f530-48a2-acfc-37cb4e4a7ce2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893101553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3893101553
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2049360368
Short name T196
Test name
Test status
Simulation time 335228429 ps
CPU time 3.82 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:08:42 PM PDT 24
Peak memory 248864 kb
Host smart-39459fde-bf0c-4702-94f7-1ae1af605790
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2049360368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2049360368
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.4206685748
Short name T25
Test name
Test status
Simulation time 140897842540 ps
CPU time 2162.06 seconds
Started Jul 17 06:08:32 PM PDT 24
Finished Jul 17 06:44:41 PM PDT 24
Peak memory 289112 kb
Host smart-db56f2cf-f3ec-432d-a123-8e5f3d2e8a51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206685748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.4206685748
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2815275974
Short name T551
Test name
Test status
Simulation time 243242421 ps
CPU time 13.22 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:08:40 PM PDT 24
Peak memory 248736 kb
Host smart-b94e6afd-2b84-4eba-817e-b68fb85c2bf3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2815275974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2815275974
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.203833915
Short name T559
Test name
Test status
Simulation time 2967442081 ps
CPU time 47.05 seconds
Started Jul 17 06:08:22 PM PDT 24
Finished Jul 17 06:09:11 PM PDT 24
Peak memory 248560 kb
Host smart-dc6c3a88-f24d-48d0-92c8-f8972a984c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20383
3915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.203833915
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2056572736
Short name T348
Test name
Test status
Simulation time 313152267 ps
CPU time 31.1 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:08:59 PM PDT 24
Peak memory 248640 kb
Host smart-16f51664-9e3a-42b8-b1a3-0cd6c5054072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20565
72736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2056572736
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2115099084
Short name T266
Test name
Test status
Simulation time 42553069958 ps
CPU time 2316.97 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:47:05 PM PDT 24
Peak memory 284016 kb
Host smart-bdbbeb1e-e4fb-4fa7-8cca-37191d5571e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115099084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2115099084
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1614150118
Short name T567
Test name
Test status
Simulation time 42934258490 ps
CPU time 1255.77 seconds
Started Jul 17 06:08:26 PM PDT 24
Finished Jul 17 06:29:23 PM PDT 24
Peak memory 285768 kb
Host smart-d41ae9af-41d4-4b6d-9fc8-87314452ee99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614150118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1614150118
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.808954027
Short name T48
Test name
Test status
Simulation time 974588515 ps
CPU time 31.02 seconds
Started Jul 17 06:08:21 PM PDT 24
Finished Jul 17 06:08:53 PM PDT 24
Peak memory 256092 kb
Host smart-81085921-d66f-4380-a4fc-46c45bb7271e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80895
4027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.808954027
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1028548921
Short name T671
Test name
Test status
Simulation time 284855058 ps
CPU time 19.01 seconds
Started Jul 17 06:07:56 PM PDT 24
Finished Jul 17 06:08:17 PM PDT 24
Peak memory 247924 kb
Host smart-4e084fa1-4b32-4a61-9617-3af4437e2221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10285
48921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1028548921
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.813706934
Short name T107
Test name
Test status
Simulation time 1367759431 ps
CPU time 42.07 seconds
Started Jul 17 06:08:27 PM PDT 24
Finished Jul 17 06:09:11 PM PDT 24
Peak memory 256196 kb
Host smart-29738a08-d760-4d0f-a139-7f07a65df87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81370
6934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.813706934
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2620293014
Short name T615
Test name
Test status
Simulation time 3554764770 ps
CPU time 54.28 seconds
Started Jul 17 06:07:55 PM PDT 24
Finished Jul 17 06:08:50 PM PDT 24
Peak memory 256964 kb
Host smart-7b6510b6-bb8c-4508-b492-cf004153c918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26202
93014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2620293014
Directory /workspace/9.alert_handler_smoke/latest
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