Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	96960	1			T21	111		T28	2946		T248	22
class_i[0x1]	52551	1			T5	22		T42	738		T62	4
class_i[0x2]	53164	1			T1	10		T41	99		T22	195
class_i[0x3]	61961	1			T2	1942		T62	6		T9	9

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	65183	1			T1	5		T2	591		T5	8
alert[0x1]	64291	1			T1	4		T2	11		T5	2
alert[0x2]	67776	1			T1	1		T2	1323		T5	7
alert[0x3]	67386	1			T2	17		T5	5		T41	44

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

264355

1

T1

10

T2

1942

T5

15

esc_ping_fail

281

1

T5

7

T9

9

T10

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	65107	1			T1	5		T2	591		T5	6
esc_integrity_fail	alert[0x1]	64216	1			T1	4		T2	11		T5	1
esc_integrity_fail	alert[0x2]	67707	1			T1	1		T2	1323		T5	5
esc_integrity_fail	alert[0x3]	67325	1			T2	17		T5	3		T41	44
esc_ping_fail	alert[0x0]	76	1			T5	2		T9	3		T10	2
esc_ping_fail	alert[0x1]	75	1			T5	1		T9	2		T10	1
esc_ping_fail	alert[0x2]	69	1			T5	2		T9	1		T10	1
esc_ping_fail	alert[0x3]	61	1			T5	2		T9	3		T10	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	96914	1			T21	111		T28	2946		T248	15
esc_integrity_fail	class_i[0x1]	52470	1			T5	15		T42	738		T62	4
esc_integrity_fail	class_i[0x2]	53117	1			T1	10		T41	99		T22	195
esc_integrity_fail	class_i[0x3]	61854	1			T2	1942		T62	6		T22	9
esc_ping_fail	class_i[0x0]	46	1			T248	7		T139	2		T109	1
esc_ping_fail	class_i[0x1]	81	1			T5	7		T10	6		T248	1
esc_ping_fail	class_i[0x2]	47	1			T70	1		T109	1		T318	1
esc_ping_fail	class_i[0x3]	107	1			T9	9		T248	1		T139	2