Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	675814448	0	0	622
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	675814448	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	675814448	675642911	0	0
tb.dut.CheckAccuCntDw	0	0	622	622	0	0
tb.dut.CheckEscCntDw	0	0	622	622	0	0
tb.dut.CheckNAlerts	0	0	622	622	0	0
tb.dut.CheckNClasses	0	0	622	622	0	0
tb.dut.CheckNEscSev	0	0	622	622	0	0
tb.dut.CrashdumpKnownO_A	0	0	675814448	675642911	0	0
tb.dut.EdnKnownO_A	0	0	675814448	675642911	0	0
tb.dut.EscPKnownO_A	0	0	675814448	675642911	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	675814448	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	675814448	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	675814448	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	675814448	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	675814448	80	0	0
tb.dut.IrqAKnownO_A	0	0	675814448	675642911	0	0
tb.dut.IrqBKnownO_A	0	0	675814448	675642911	0	0
tb.dut.IrqCKnownO_A	0	0	675814448	675642911	0	0
tb.dut.IrqDKnownO_A	0	0	675814448	675642911	0	0
tb.dut.TlAReadyKnownO_A	0	0	675814448	675642911	0	0
tb.dut.TlDValidKnownO_A	0	0	675814448	675642911	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	698100088	3314379	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	698100088	9945	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	698100088	10957	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	698100088	8520	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	698100088	10808	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	698100088	10681	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	698100088	11971	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	698100088	8319	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	698100088	9614	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	698100088	9483	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	698100088	8694	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	698100088	10716	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	698100088	9536	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	698100088	9842	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	698100088	8336	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	698100088	10738	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	698100088	8304	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	698100088	11763	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	698100088	10702	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	698100088	10075	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	698100088	9496	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	698100088	10627	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	698100088	9601	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	698100088	8517	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	698100088	11062	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	698100088	9381	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	698100088	8758	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	698100088	10861	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	698100088	8721	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	698100088	8450	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	698100088	9437	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	698100088	9541	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	698100088	10815	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	698100088	9619	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	698100088	8317	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	698100088	11017	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	698100088	8554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	698100088	9908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	698100088	8402	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	698100088	9715	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	698100088	9528	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	698100088	8672	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	698100088	9442	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	698100088	9467	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	698100088	10788	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	698100088	8599	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	698100088	9804	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	698100088	8430	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	698100088	9559	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	698100088	8555	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	698100088	9872	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	698100088	9379	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	698100088	8711	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	698100088	9493	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	698100088	8538	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	698100088	9489	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	698100088	10858	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	698100088	9776	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	698100088	10784	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	698100088	8830	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	698100088	9819	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	698100088	9442	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	698100088	9474	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	698100088	9509	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	698100088	8329	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	698100088	9478	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	698100088	8647	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	698100088	8653	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	698100088	9671	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	698100088	9670	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	698100088	15180	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	698100088	10884	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	698100088	9859	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	698100088	9798	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	698100088	11687	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	698100088	8667	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	698100088	9519	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	698100088	8538	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	698100088	9684	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	675814448	2944	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	675814448	218222	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	675814448	367321810	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	675814448	249	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	675814448	766	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	675814448	52	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	675814448	370	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	675666033	260395059	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	675814448	870	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	675814448	853	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	675814448	832	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	675814448	817	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	675814448	730	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	675814448	92690	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	675814448	611	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	675814448	67	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675814448	1439	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	675814448	1199	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	675664616	675595473	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	675814448	675642911	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	675814448	6300	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	675814448	183195	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	675814448	364593910	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	675814448	263	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	675814448	517	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	675814448	25	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	675814448	258	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	675666033	302495486	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	675814448	608	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	675814448	598	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	675814448	587	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	675814448	568	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	675814448	1107	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	675814448	109453	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	675814448	1006	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	675814448	75	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675814448	1372	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	675814448	1132	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	675664616	675595473	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	675814448	675642911	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	675814448	1857	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	675814448	160281	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	675814448	409594589	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	675814448	236	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	675814448	444	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	675814448	37	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	675814448	209	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	675666033	347802267	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	675814448	527	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	675814448	513	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	675814448	502	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	675814448	489	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	675814448	1862	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	675814448	162761	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	675814448	1770	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	675814448	51	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675814448	1480	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	675814448	1240	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	675664616	675595473	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	675814448	675642911	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	675814448	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	675814448	3053	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	675814448	173959	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	675814448	393516780	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	675814448	247	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	675814448	492	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	675814448	15	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	675814448	186	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	675666033	305365489	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	675814448	549	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	675814448	545	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	675814448	532	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	675814448	520	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	675814448	1107	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	675814448	116250	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	675814448	1034	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	675814448	57	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	675814448	1454	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	675814448	1214	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	675664616	675595473	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	675814448	675642911	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	698100088	143142174	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	698100088	697429544	0	0
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