Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	67	1			T19	1		T22	1		T67	1
class_index[0x1]	75	1			T1	1		T21	1		T67	1
class_index[0x2]	51	1			T23	1		T25	1		T88	1
class_index[0x3]	57	1			T1	1		T21	1		T62	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	98	1			T1	1		T21	1		T62	1
intr_timeout_cnt[1]	57	1			T21	1		T80	1		T89	2
intr_timeout_cnt[2]	21	1			T23	1		T91	1		T94	1
intr_timeout_cnt[3]	18	1			T19	1		T89	1		T47	2
intr_timeout_cnt[4]	11	1			T74	2		T269	1		T220	1
intr_timeout_cnt[5]	9	1			T67	1		T145	1		T96	1
intr_timeout_cnt[6]	9	1			T258	1		T58	1		T59	1
intr_timeout_cnt[7]	7	1			T67	1		T118	1		T101	1
intr_timeout_cnt[8]	10	1			T118	1		T220	1		T56	2
intr_timeout_cnt[9]	10	1			T1	1		T110	1		T258	2

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[7] , intr_timeout_cnt[8]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	28	1			T22	1		T24	1		T88	1
class_index[0x0]	intr_timeout_cnt[1]	9	1			T270	1		T106	1		T220	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T94	1		T50	1		T271	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T19	1		T89	1		T54	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T258	1		T227	1		T272	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T145	1		T258	1		T104	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T258	1		T273	1		T274	1
class_index[0x0]	intr_timeout_cnt[7]	4	1			T67	1		T118	1		T101	1
class_index[0x0]	intr_timeout_cnt[8]	3	1			T56	2		T275	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T110	1		T276	1		T115	1
class_index[0x1]	intr_timeout_cnt[0]	22	1			T21	1		T80	1		T88	1
class_index[0x1]	intr_timeout_cnt[1]	30	1			T80	1		T51	1		T107	9
class_index[0x1]	intr_timeout_cnt[2]	6	1			T91	1		T277	2		T278	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T47	2		T59	1		T279	1
class_index[0x1]	intr_timeout_cnt[4]	4	1			T74	1		T220	1		T280	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T67	1		T96	1		T281	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T282	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	4	1			T1	1		T283	1		T275	1
class_index[0x2]	intr_timeout_cnt[0]	19	1			T25	1		T88	1		T90	2
class_index[0x2]	intr_timeout_cnt[1]	11	1			T89	1		T122	1		T212	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T23	1		T49	1		T273	1
class_index[0x2]	intr_timeout_cnt[3]	8	1			T101	1		T258	1		T281	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T74	1		T284	1		T285	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T286	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T221	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T260	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	3	1			T220	1		T58	1		T278	1
class_index[0x3]	intr_timeout_cnt[0]	29	1			T1	1		T62	1		T84	1
class_index[0x3]	intr_timeout_cnt[1]	7	1			T21	1		T89	1		T94	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T287	1		T288	2		T289	2
class_index[0x3]	intr_timeout_cnt[3]	2	1			T51	1		T290	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	1	1			T269	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	1	1			T60	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	3	1			T58	1		T59	1		T276	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T277	1		T276	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	4	1			T118	1		T273	2		T221	1
class_index[0x3]	intr_timeout_cnt[9]	3	1			T258	2		T291	1		-	-