Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	371262	1			T1	6		T2	15		T3	1313
all_values[1]	371262	1			T1	6		T2	15		T3	1313
all_values[2]	371262	1			T1	6		T2	15		T3	1313
all_values[3]	371262	1			T1	6		T2	15		T3	1313

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

737103

1

T1

10

T2

30

T3

2651

auto[1]

747945

1

T1

14

T2

30

T3

2601

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

883838

1

T1

5

T2

11

T3

2640

auto[1]

601210

1

T1

19

T2

49

T3

2612

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	106649	1			T2	2		T3	343		T4	317
all_values[0]	auto[0]	auto[1]	78323	1			T1	3		T2	2		T3	341
all_values[0]	auto[1]	auto[0]	107798	1			T1	1		T2	3		T3	316
all_values[0]	auto[1]	auto[1]	78492	1			T1	2		T2	8		T3	313
all_values[1]	auto[0]	auto[0]	110842	1			T2	3		T3	342		T4	328
all_values[1]	auto[0]	auto[1]	73450	1			T2	6		T3	340		T4	324
all_values[1]	auto[1]	auto[0]	112895	1			T1	2		T2	1		T3	316
all_values[1]	auto[1]	auto[1]	74075	1			T1	4		T2	5		T3	315
all_values[2]	auto[0]	auto[0]	110205	1			T1	1		T3	334		T4	335
all_values[2]	auto[0]	auto[1]	73244	1			T1	4		T2	6		T3	329
all_values[2]	auto[1]	auto[0]	113314	1			T2	1		T3	331		T4	325
all_values[2]	auto[1]	auto[1]	74499	1			T1	1		T2	8		T3	319
all_values[3]	auto[0]	auto[0]	110155	1			T2	1		T3	312		T4	336
all_values[3]	auto[0]	auto[1]	74235	1			T1	2		T2	10		T3	310
all_values[3]	auto[1]	auto[0]	111980	1			T1	1		T3	346		T4	327
all_values[3]	auto[1]	auto[1]	74892	1			T1	3		T2	4		T3	345