Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	371262	1			T1	6		T2	15		T3	1313
all_pins[1]	371262	1			T1	6		T2	15		T3	1313
all_pins[2]	371262	1			T1	6		T2	15		T3	1313
all_pins[3]	371262	1			T1	6		T2	15		T3	1313

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1183090	1			T1	14		T2	35		T3	3960
values[0x1]	301958	1			T1	10		T2	25		T3	1292
transitions[0x0=>0x1]	200822	1			T1	5		T2	15		T3	811
transitions[0x1=>0x0]	201071	1			T1	5		T2	15		T3	812

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	292770	1			T1	4		T2	7		T3	1000
all_pins[0]	values[0x1]	78492	1			T1	2		T2	8		T3	313
all_pins[0]	transitions[0x0=>0x1]	77850	1			T1	1		T2	5		T3	312
all_pins[0]	transitions[0x1=>0x0]	74499	1			T1	2		T2	1		T3	345
all_pins[1]	values[0x0]	297187	1			T1	2		T2	10		T3	998
all_pins[1]	values[0x1]	74075	1			T1	4		T2	5		T3	315
all_pins[1]	transitions[0x0=>0x1]	40515	1			T1	2		T2	2		T3	167
all_pins[1]	transitions[0x1=>0x0]	44932	1			T2	5		T3	165		T4	173
all_pins[2]	values[0x0]	296763	1			T1	5		T2	7		T3	994
all_pins[2]	values[0x1]	74499	1			T1	1		T2	8		T3	319
all_pins[2]	transitions[0x0=>0x1]	41281	1			T2	5		T3	165		T4	163
all_pins[2]	transitions[0x1=>0x0]	40857	1			T1	3		T2	2		T3	161
all_pins[3]	values[0x0]	296370	1			T1	3		T2	11		T3	968
all_pins[3]	values[0x1]	74892	1			T1	3		T2	4		T3	345
all_pins[3]	transitions[0x0=>0x1]	41176	1			T1	2		T2	3		T3	167
all_pins[3]	transitions[0x1=>0x0]	40783	1			T2	7		T3	141		T4	164