Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1			T190	4		T191	7		T192	7
all_values[1]	266	1			T190	4		T191	7		T192	7
all_values[2]	266	1			T190	4		T191	7		T192	7
all_values[3]	266	1			T190	4		T191	7		T192	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

594

1

T190

4

T191

20

T192

11

auto[1]

470

1

T190

12

T191

8

T192

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

400

1

T190

9

T191

11

T192

11

auto[1]

664

1

T190

7

T191

17

T192

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619

1

T190

11

T191

14

T192

16

auto[1]

445

1

T190

5

T191

14

T192

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

51

1

T191

2

T362

3

T363

1

all_values[0]

auto[0]

auto[0]

auto[1]

25

1

T192

1

T256

1

T364

1

all_values[0]

auto[0]

auto[1]

auto[0]

40

1

T190

2

T191

1

T192

3

all_values[0]

auto[0]

auto[1]

auto[1]

23

1

T192

1

T364

1

T363

1

all_values[0]

auto[1]

auto[0]

auto[1]

73

1

T190

1

T191

3

T192

1

all_values[0]

auto[1]

auto[1]

auto[1]

54

1

T190

1

T191

1

T192

1

all_values[1]

auto[0]

auto[0]

auto[0]

49

1

T190

1

T191

2

T192

1

all_values[1]

auto[0]

auto[0]

auto[1]

29

1

T191

2

T364

1

T362

1

all_values[1]

auto[0]

auto[1]

auto[0]

46

1

T190

1

T192

2

T362

3

all_values[1]

auto[0]

auto[1]

auto[1]

32

1

T190

1

T192

1

T256

4

all_values[1]

auto[1]

auto[0]

auto[1]

66

1

T191

1

T256

1

T364

3

all_values[1]

auto[1]

auto[1]

auto[1]

44

1

T190

1

T191

2

T192

3

all_values[2]

auto[0]

auto[0]

auto[0]

56

1

T190

1

T191

2

T364

2

all_values[2]

auto[0]

auto[0]

auto[1]

44

1

T191

1

T192

2

T256

4

all_values[2]

auto[0]

auto[1]

auto[0]

42

1

T190

3

T191

2

T192

1

all_values[2]

auto[0]

auto[1]

auto[1]

20

1

T256

1

T362

2

T365

1

all_values[2]

auto[1]

auto[0]

auto[1]

58

1

T191

1

T192

3

T256

1

all_values[2]

auto[1]

auto[1]

auto[1]

46

1

T191

1

T192

1

T256

1

all_values[3]

auto[0]

auto[0]

auto[0]

69

1

T190

1

T191

1

T192

2

all_values[3]

auto[0]

auto[0]

auto[1]

21

1

T364

2

T362

2

T366

1

all_values[3]

auto[0]

auto[1]

auto[0]

47

1

T191

1

T192

2

T364

1

all_values[3]

auto[0]

auto[1]

auto[1]

25

1

T190

1

T256

2

T364

2

all_values[3]

auto[1]

auto[0]

auto[1]

53

1

T191

5

T192

1

T363

2

all_values[3]

auto[1]

auto[1]

auto[1]

51

1

T190

2

T192

2

T256

4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal