Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	89851	1			T2	22		T3	755		T4	835
accum_cnt_1000	246484	1			T3	1069		T4	1015		T15	1912
accum_cnt_100	27420	1			T2	1		T3	60		T4	58
accum_cnt_50	61205	1			T1	4		T2	5		T3	52
accum_cnt_10	193176	1			T1	24		T2	19		T3	1001
accum_cnt_0	439585	1			T1	4		T2	49		T3	987

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	273089	1			T1	8		T2	24		T3	981
class_index[0x1]	273089	1			T1	8		T2	24		T3	981
class_index[0x2]	273089	1			T1	8		T2	24		T3	981
class_index[0x3]	273089	1			T1	8		T2	24		T3	981

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	19315	1			T3	393		T15	216		T28	242
class_index[0x0]	accum_cnt_1000	58759	1			T3	515		T15	630		T21	39
class_index[0x0]	accum_cnt_100	7907	1			T3	30		T15	35		T21	39
class_index[0x0]	accum_cnt_50	16618	1			T1	2		T2	5		T3	25
class_index[0x0]	accum_cnt_10	59092	1			T1	6		T2	19		T3	14
class_index[0x0]	accum_cnt_0	99185	1			T3	4		T4	987		T5	29
class_index[0x1]	accum_cnt_2000	26326	1			T28	182		T25	150		T24	514
class_index[0x1]	accum_cnt_1000	64300	1			T8	876		T42	29		T21	136
class_index[0x1]	accum_cnt_100	7129	1			T8	75		T21	49		T44	26
class_index[0x1]	accum_cnt_50	16580	1			T4	973		T5	15		T19	13
class_index[0x1]	accum_cnt_10	39699	1			T1	7		T3	980		T4	14
class_index[0x1]	accum_cnt_0	110899	1			T1	1		T2	24		T3	1
class_index[0x2]	accum_cnt_2000	21226	1			T3	362		T4	451		T15	397
class_index[0x2]	accum_cnt_1000	56621	1			T3	554		T4	477		T15	466
class_index[0x2]	accum_cnt_100	5473	1			T3	30		T4	26		T15	23
class_index[0x2]	accum_cnt_50	14064	1			T1	2		T3	27		T4	25
class_index[0x2]	accum_cnt_10	44775	1			T1	3		T3	7		T4	8
class_index[0x2]	accum_cnt_0	123843	1			T1	3		T2	24		T3	1
class_index[0x3]	accum_cnt_2000	22984	1			T2	22		T4	384		T16	373
class_index[0x3]	accum_cnt_1000	66804	1			T4	538		T15	816		T16	746
class_index[0x3]	accum_cnt_100	6911	1			T2	1		T4	32		T15	53
class_index[0x3]	accum_cnt_50	13943	1			T4	25		T19	14		T15	43
class_index[0x3]	accum_cnt_10	49610	1			T1	8		T4	7		T19	55
class_index[0x3]	accum_cnt_0	105658	1			T2	1		T3	981		T4	1