Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	6156	1			T1	2		T19	7		T41	51
alert[0x1]	8785	1			T21	106		T24	562		T48	6
alert[0x2]	8137	1			T1	1		T5	2		T41	2
alert[0x3]	10114	1			T41	1		T23	1011		T25	871
alert[0x4]	1515	1			T10	2		T310	108		T116	146
alert[0x5]	10558	1			T5	1		T24	989		T254	105
alert[0x6]	6253	1			T9	1		T22	74		T23	66
alert[0x7]	11174	1			T76	2		T23	962		T25	124
alert[0x8]	3201	1			T1	1		T9	1		T127	1
alert[0x9]	4362	1			T21	346		T9	1		T75	3
alert[0xa]	9229	1			T21	3698		T62	1		T75	151
alert[0xb]	9582	1			T248	1		T25	736		T24	20
alert[0xc]	5138	1			T10	1		T248	1		T24	315
alert[0xd]	6168	1			T22	941		T23	97		T254	16
alert[0xe]	6944	1			T248	1		T23	20		T24	297
alert[0xf]	8743	1			T1	3		T10	1		T22	100
alert[0x10]	8882	1			T10	1		T24	305		T254	1771
alert[0x11]	6891	1			T21	14		T62	3		T22	127
alert[0x12]	7903	1			T10	1		T28	2		T22	146
alert[0x13]	3291	1			T21	27		T22	261		T23	40
alert[0x14]	4724	1			T248	1		T70	1		T24	18
alert[0x15]	5118	1			T41	1		T76	1		T25	11
alert[0x16]	7024	1			T42	1		T21	1613		T22	21
alert[0x17]	1857	1			T248	1		T25	18		T26	4
alert[0x18]	6194	1			T10	1		T248	1		T91	12
alert[0x19]	6758	1			T5	1		T248	1		T67	12
alert[0x1a]	5244	1			T5	1		T21	1835		T62	2
alert[0x1b]	12445	1			T62	6		T9	1		T248	1
alert[0x1c]	4226	1			T24	790		T254	368		T47	58
alert[0x1d]	11741	1			T5	1		T24	105		T105	6
alert[0x1e]	8970	1			T41	2		T62	1		T9	1
alert[0x1f]	9833	1			T22	1200		T23	69		T25	79
alert[0x20]	11391	1			T1	36		T5	1		T21	24
alert[0x21]	6189	1			T42	59		T9	1		T28	3
alert[0x22]	7321	1			T62	3		T28	3		T248	1
alert[0x23]	8414	1			T5	1		T41	8		T21	11
alert[0x24]	7210	1			T28	1		T22	24		T24	16
alert[0x25]	8713	1			T10	1		T28	4		T22	47
alert[0x26]	3401	1			T9	1		T25	68		T24	24
alert[0x27]	11761	1			T25	1073		T88	26		T109	1
alert[0x28]	6973	1			T8	1		T21	263		T10	1
alert[0x29]	6991	1			T41	3		T23	411		T24	57
alert[0x2a]	3592	1			T8	2		T21	36		T22	48
alert[0x2b]	7674	1			T5	1		T41	17		T42	8
alert[0x2c]	10896	1			T22	223		T24	4225		T254	42
alert[0x2d]	4953	1			T5	1		T10	1		T248	1
alert[0x2e]	5492	1			T42	23		T9	1		T25	40
alert[0x2f]	4600	1			T7	1		T248	2		T25	28
alert[0x30]	4326	1			T25	197		T91	2		T88	4
alert[0x31]	5493	1			T42	31		T24	53		T315	163
alert[0x32]	3578	1			T5	1		T9	2		T24	18
alert[0x33]	3498	1			T22	129		T23	105		T315	11
alert[0x34]	5727	1			T10	1		T248	1		T22	881
alert[0x35]	4910	1			T21	60		T10	1		T248	2
alert[0x36]	8048	1			T41	1		T9	2		T248	2
alert[0x37]	1736	1			T2	1		T21	144		T22	41
alert[0x38]	7194	1			T21	171		T28	3		T23	96
alert[0x39]	4355	1			T21	117		T28	2		T22	4
alert[0x3a]	5488	1			T9	1		T10	1		T248	1
alert[0x3b]	3590	1			T19	4		T9	1		T23	186
alert[0x3c]	4936	1			T19	1		T21	4		T23	3
alert[0x3d]	7643	1			T19	13		T9	1		T25	120
alert[0x3e]	8890	1			T22	19		T23	18		T24	15
alert[0x3f]	2111	1			T10	1		T22	28		T23	4
alert[0x40]	9458	1			T5	1		T28	4		T23	14

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	130387	1			T41	2		T62	10		T9	19
class_i[0x1]	45468	1			T2	1		T5	11		T19	8
class_i[0x2]	126862	1			T1	43		T5	1		T41	1
class_i[0x3]	130995	1			T19	17		T8	3		T41	83

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

433037

1

T1

43

T2

1

T19

25

alert_ping_fail

675

1

T5

12

T7

1

T8

3

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	6146	1			T1	2		T19	7		T41	51
alert_integrity_fail	alert[0x1]	8777	1			T21	106		T24	562		T48	6
alert_integrity_fail	alert[0x2]	8129	1			T1	1		T41	2		T21	52
alert_integrity_fail	alert[0x3]	10111	1			T41	1		T23	1011		T25	871
alert_integrity_fail	alert[0x4]	1505	1			T310	108		T116	146		T49	46
alert_integrity_fail	alert[0x5]	10548	1			T24	989		T254	105		T315	89
alert_integrity_fail	alert[0x6]	6245	1			T22	74		T23	66		T25	1
alert_integrity_fail	alert[0x7]	11162	1			T23	962		T25	124		T24	177
alert_integrity_fail	alert[0x8]	3187	1			T1	1		T23	96		T67	3
alert_integrity_fail	alert[0x9]	4352	1			T21	346		T75	3		T24	535
alert_integrity_fail	alert[0xa]	9219	1			T21	3698		T62	1		T75	151
alert_integrity_fail	alert[0xb]	9575	1			T25	736		T24	20		T254	9
alert_integrity_fail	alert[0xc]	5127	1			T24	315		T310	3		T96	522
alert_integrity_fail	alert[0xd]	6162	1			T22	941		T23	97		T254	16
alert_integrity_fail	alert[0xe]	6932	1			T23	20		T24	297		T88	32
alert_integrity_fail	alert[0xf]	8730	1			T1	3		T22	100		T67	7
alert_integrity_fail	alert[0x10]	8873	1			T24	305		T254	1771		T143	1
alert_integrity_fail	alert[0x11]	6884	1			T21	14		T62	3		T22	127
alert_integrity_fail	alert[0x12]	7895	1			T28	2		T22	146		T254	585
alert_integrity_fail	alert[0x13]	3280	1			T21	27		T22	261		T23	40
alert_integrity_fail	alert[0x14]	4713	1			T24	18		T254	45		T91	1
alert_integrity_fail	alert[0x15]	5105	1			T41	1		T25	11		T254	43
alert_integrity_fail	alert[0x16]	7005	1			T42	1		T21	1613		T22	21
alert_integrity_fail	alert[0x17]	1848	1			T25	18		T26	4		T254	1
alert_integrity_fail	alert[0x18]	6187	1			T91	12		T88	17		T316	759
alert_integrity_fail	alert[0x19]	6750	1			T67	12		T25	13		T88	147
alert_integrity_fail	alert[0x1a]	5231	1			T21	1835		T62	2		T22	886
alert_integrity_fail	alert[0x1b]	12434	1			T62	6		T22	68		T23	375
alert_integrity_fail	alert[0x1c]	4216	1			T24	790		T254	368		T47	58
alert_integrity_fail	alert[0x1d]	11730	1			T24	105		T105	6		T45	1
alert_integrity_fail	alert[0x1e]	8954	1			T41	2		T62	1		T79	3
alert_integrity_fail	alert[0x1f]	9817	1			T22	1200		T23	69		T25	79
alert_integrity_fail	alert[0x20]	11379	1			T1	36		T21	24		T23	29
alert_integrity_fail	alert[0x21]	6183	1			T42	59		T28	3		T24	25
alert_integrity_fail	alert[0x22]	7306	1			T62	3		T28	3		T23	17
alert_integrity_fail	alert[0x23]	8406	1			T41	8		T21	11		T24	10
alert_integrity_fail	alert[0x24]	7198	1			T28	1		T22	24		T24	16
alert_integrity_fail	alert[0x25]	8703	1			T28	4		T22	47		T24	10
alert_integrity_fail	alert[0x26]	3393	1			T25	68		T24	24		T88	550
alert_integrity_fail	alert[0x27]	11752	1			T25	1073		T88	26		T310	718
alert_integrity_fail	alert[0x28]	6955	1			T21	263		T22	4		T24	1456
alert_integrity_fail	alert[0x29]	6981	1			T41	3		T23	411		T24	57
alert_integrity_fail	alert[0x2a]	3579	1			T21	36		T22	48		T25	71
alert_integrity_fail	alert[0x2b]	7662	1			T41	17		T42	8		T254	356
alert_integrity_fail	alert[0x2c]	10881	1			T22	223		T24	4225		T254	42
alert_integrity_fail	alert[0x2d]	4938	1			T24	428		T254	560		T315	550
alert_integrity_fail	alert[0x2e]	5481	1			T42	23		T25	40		T26	6
alert_integrity_fail	alert[0x2f]	4587	1			T25	28		T24	79		T254	18
alert_integrity_fail	alert[0x30]	4312	1			T25	197		T91	2		T88	4
alert_integrity_fail	alert[0x31]	5487	1			T42	31		T24	53		T315	163
alert_integrity_fail	alert[0x32]	3565	1			T24	18		T45	1		T310	26
alert_integrity_fail	alert[0x33]	3488	1			T22	129		T23	105		T315	11
alert_integrity_fail	alert[0x34]	5719	1			T22	881		T23	34		T80	1
alert_integrity_fail	alert[0x35]	4898	1			T21	60		T254	9		T315	67
alert_integrity_fail	alert[0x36]	8032	1			T41	1		T24	17		T254	406
alert_integrity_fail	alert[0x37]	1727	1			T2	1		T21	144		T22	41
alert_integrity_fail	alert[0x38]	7184	1			T21	171		T28	3		T23	96
alert_integrity_fail	alert[0x39]	4346	1			T21	117		T28	2		T22	4
alert_integrity_fail	alert[0x3a]	5478	1			T23	46		T25	22		T24	112
alert_integrity_fail	alert[0x3b]	3587	1			T19	4		T23	186		T25	189
alert_integrity_fail	alert[0x3c]	4927	1			T19	1		T21	4		T23	3
alert_integrity_fail	alert[0x3d]	7636	1			T19	13		T25	120		T91	1
alert_integrity_fail	alert[0x3e]	8884	1			T22	19		T23	18		T24	15
alert_integrity_fail	alert[0x3f]	2103	1			T22	28		T23	4		T25	26
alert_integrity_fail	alert[0x40]	9451	1			T28	4		T23	14		T25	15
alert_ping_fail	alert[0x0]	10	1			T9	1		T317	1		T318	1
alert_ping_fail	alert[0x1]	8	1			T98	1		T319	1		T320	1
alert_ping_fail	alert[0x2]	8	1			T5	2		T10	1		T248	1
alert_ping_fail	alert[0x3]	3	1			T317	1		T321	1		T322	1
alert_ping_fail	alert[0x4]	10	1			T10	2		T323	1		T324	1
alert_ping_fail	alert[0x5]	10	1			T5	1		T139	1		T317	1
alert_ping_fail	alert[0x6]	8	1			T9	1		T325	1		T318	1
alert_ping_fail	alert[0x7]	12	1			T76	2		T317	1		T326	1
alert_ping_fail	alert[0x8]	14	1			T9	1		T127	1		T70	1
alert_ping_fail	alert[0x9]	10	1			T9	1		T307	1		T325	1
alert_ping_fail	alert[0xa]	10	1			T76	2		T317	1		T213	1
alert_ping_fail	alert[0xb]	7	1			T248	1		T307	1		T327	2
alert_ping_fail	alert[0xc]	11	1			T10	1		T248	1		T139	1
alert_ping_fail	alert[0xd]	6	1			T328	1		T319	1		T329	1
alert_ping_fail	alert[0xe]	12	1			T248	1		T109	1		T326	1
alert_ping_fail	alert[0xf]	13	1			T10	1		T139	1		T317	1
alert_ping_fail	alert[0x10]	9	1			T10	1		T317	1		T306	2
alert_ping_fail	alert[0x11]	7	1			T70	1		T328	1		T326	1
alert_ping_fail	alert[0x12]	8	1			T10	1		T109	1		T325	1
alert_ping_fail	alert[0x13]	11	1			T263	1		T137	1		T330	1
alert_ping_fail	alert[0x14]	11	1			T248	1		T70	1		T139	1
alert_ping_fail	alert[0x15]	13	1			T76	1		T250	1		T109	1
alert_ping_fail	alert[0x16]	19	1			T109	2		T331	1		T317	1
alert_ping_fail	alert[0x17]	9	1			T248	1		T109	1		T330	1
alert_ping_fail	alert[0x18]	7	1			T10	1		T248	1		T332	1
alert_ping_fail	alert[0x19]	8	1			T5	1		T248	1		T333	1
alert_ping_fail	alert[0x1a]	13	1			T5	1		T10	1		T139	1
alert_ping_fail	alert[0x1b]	11	1			T9	1		T248	1		T334	1
alert_ping_fail	alert[0x1c]	10	1			T146	2		T318	1		T330	1
alert_ping_fail	alert[0x1d]	11	1			T5	1		T317	1		T325	1
alert_ping_fail	alert[0x1e]	16	1			T9	1		T317	1		T326	2
alert_ping_fail	alert[0x1f]	16	1			T139	1		T109	1		T331	2
alert_ping_fail	alert[0x20]	12	1			T5	1		T10	1		T248	1
alert_ping_fail	alert[0x21]	6	1			T9	1		T98	1		T320	1
alert_ping_fail	alert[0x22]	15	1			T248	1		T70	1		T141	1
alert_ping_fail	alert[0x23]	8	1			T5	1		T9	2		T248	1
alert_ping_fail	alert[0x24]	12	1			T317	1		T98	1		T335	1
alert_ping_fail	alert[0x25]	10	1			T10	1		T317	1		T332	1
alert_ping_fail	alert[0x26]	8	1			T9	1		T317	1		T318	1
alert_ping_fail	alert[0x27]	9	1			T109	1		T326	1		T327	1
alert_ping_fail	alert[0x28]	18	1			T8	1		T10	1		T317	1
alert_ping_fail	alert[0x29]	10	1			T317	1		T306	1		T330	2
alert_ping_fail	alert[0x2a]	13	1			T8	2		T336	1		T109	1
alert_ping_fail	alert[0x2b]	12	1			T5	1		T9	1		T330	2
alert_ping_fail	alert[0x2c]	15	1			T306	1		T318	1		T98	1
alert_ping_fail	alert[0x2d]	15	1			T5	1		T10	1		T248	1
alert_ping_fail	alert[0x2e]	11	1			T9	1		T328	2		T98	2
alert_ping_fail	alert[0x2f]	13	1			T7	1		T248	2		T139	1
alert_ping_fail	alert[0x30]	14	1			T337	2		T98	1		T338	1
alert_ping_fail	alert[0x31]	6	1			T98	2		T324	1		T333	1
alert_ping_fail	alert[0x32]	13	1			T5	1		T9	2		T317	1
alert_ping_fail	alert[0x33]	10	1			T317	1		T339	2		T340	1
alert_ping_fail	alert[0x34]	8	1			T10	1		T248	1		T317	1
alert_ping_fail	alert[0x35]	12	1			T10	1		T248	2		T326	2
alert_ping_fail	alert[0x36]	16	1			T9	2		T248	2		T330	1
alert_ping_fail	alert[0x37]	9	1			T325	1		T318	1		T330	1
alert_ping_fail	alert[0x38]	10	1			T139	1		T328	1		T326	1
alert_ping_fail	alert[0x39]	9	1			T328	1		T317	1		T335	1
alert_ping_fail	alert[0x3a]	10	1			T9	1		T10	1		T248	1
alert_ping_fail	alert[0x3b]	3	1			T9	1		T325	1		T341	1
alert_ping_fail	alert[0x3c]	9	1			T139	3		T317	1		T332	1
alert_ping_fail	alert[0x3d]	7	1			T9	1		T342	1		T329	1
alert_ping_fail	alert[0x3e]	6	1			T317	1		T306	1		T327	1
alert_ping_fail	alert[0x3f]	8	1			T10	1		T306	1		T326	1
alert_ping_fail	alert[0x40]	7	1			T5	1		T306	1		T326	2

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	130230	1			T41	2		T62	10		T22	553
alert_integrity_fail	class_i[0x1]	45287	1			T2	1		T19	8		T62	6
alert_integrity_fail	class_i[0x2]	126724	1			T1	43		T41	1		T42	98
alert_integrity_fail	class_i[0x3]	130796	1			T19	17		T41	83		T42	24
alert_ping_fail	class_i[0x0]	157	1			T9	19		T70	2		T250	1
alert_ping_fail	class_i[0x1]	181	1			T5	11		T7	1		T248	17
alert_ping_fail	class_i[0x2]	138	1			T5	1		T127	1		T248	2
alert_ping_fail	class_i[0x3]	199	1			T8	3		T10	17		T76	5