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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.67 100.00 100.00 100.00 99.38 99.56


Total test records in report: 827
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T772 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2637939323 Jul 18 06:45:07 PM PDT 24 Jul 18 06:45:16 PM PDT 24 69144881 ps
T773 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.946617945 Jul 18 06:44:57 PM PDT 24 Jul 18 06:45:15 PM PDT 24 122435952 ps
T199 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1829400003 Jul 18 06:44:43 PM PDT 24 Jul 18 06:46:10 PM PDT 24 4686796351 ps
T198 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3506592008 Jul 18 06:44:52 PM PDT 24 Jul 18 06:45:35 PM PDT 24 457280449 ps
T774 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.4008119557 Jul 18 06:45:16 PM PDT 24 Jul 18 06:45:21 PM PDT 24 20700184 ps
T775 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3759763424 Jul 18 06:44:52 PM PDT 24 Jul 18 06:45:05 PM PDT 24 345934236 ps
T776 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2114973350 Jul 18 06:44:37 PM PDT 24 Jul 18 06:50:22 PM PDT 24 18796981064 ps
T777 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.358472376 Jul 18 06:45:08 PM PDT 24 Jul 18 06:45:14 PM PDT 24 16119684 ps
T778 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1550855680 Jul 18 06:45:02 PM PDT 24 Jul 18 06:45:32 PM PDT 24 388776309 ps
T196 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.381137437 Jul 18 06:44:54 PM PDT 24 Jul 18 06:45:25 PM PDT 24 603730012 ps
T779 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4151810981 Jul 18 06:44:35 PM PDT 24 Jul 18 06:44:55 PM PDT 24 138518514 ps
T159 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3570104612 Jul 18 06:44:34 PM PDT 24 Jul 18 06:54:51 PM PDT 24 18133352694 ps
T780 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2832780 Jul 18 06:45:19 PM PDT 24 Jul 18 06:45:24 PM PDT 24 13834252 ps
T781 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2276783612 Jul 18 06:44:53 PM PDT 24 Jul 18 06:45:06 PM PDT 24 127653793 ps
T782 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.231147136 Jul 18 06:44:41 PM PDT 24 Jul 18 06:44:53 PM PDT 24 7594301 ps
T783 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3075776200 Jul 18 06:45:06 PM PDT 24 Jul 18 06:45:14 PM PDT 24 35139052 ps
T182 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1896940733 Jul 18 06:44:40 PM PDT 24 Jul 18 06:54:53 PM PDT 24 8737359708 ps
T784 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3146014875 Jul 18 06:44:39 PM PDT 24 Jul 18 06:44:57 PM PDT 24 137854662 ps
T785 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1934312090 Jul 18 06:50:29 PM PDT 24 Jul 18 06:50:38 PM PDT 24 121150191 ps
T167 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.502861477 Jul 18 06:44:58 PM PDT 24 Jul 18 06:48:08 PM PDT 24 18186199344 ps
T164 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1430427361 Jul 18 06:44:43 PM PDT 24 Jul 18 06:47:48 PM PDT 24 2928669418 ps
T786 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1841777855 Jul 18 06:45:09 PM PDT 24 Jul 18 06:45:16 PM PDT 24 25293082 ps
T787 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.176393750 Jul 18 06:44:42 PM PDT 24 Jul 18 06:45:05 PM PDT 24 115790769 ps
T788 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1804034613 Jul 18 06:44:53 PM PDT 24 Jul 18 06:45:39 PM PDT 24 2295337946 ps
T160 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1626345150 Jul 18 06:45:08 PM PDT 24 Jul 18 06:48:16 PM PDT 24 5279927662 ps
T179 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2405249470 Jul 18 06:44:53 PM PDT 24 Jul 18 07:01:30 PM PDT 24 105802451921 ps
T789 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.430787322 Jul 18 06:45:04 PM PDT 24 Jul 18 06:45:11 PM PDT 24 12075916 ps
T185 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.107222700 Jul 18 06:44:43 PM PDT 24 Jul 18 06:50:11 PM PDT 24 9122555508 ps
T790 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2308280525 Jul 18 06:44:38 PM PDT 24 Jul 18 06:44:51 PM PDT 24 8233876 ps
T181 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1134954822 Jul 18 06:44:53 PM PDT 24 Jul 18 06:55:29 PM PDT 24 4438550142 ps
T791 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.288498372 Jul 18 06:44:55 PM PDT 24 Jul 18 06:45:12 PM PDT 24 329952317 ps
T792 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2904924080 Jul 18 06:44:53 PM PDT 24 Jul 18 06:45:20 PM PDT 24 1003499946 ps
T793 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3887245875 Jul 18 06:44:51 PM PDT 24 Jul 18 06:45:08 PM PDT 24 91979183 ps
T794 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2906994429 Jul 18 06:44:51 PM PDT 24 Jul 18 06:45:00 PM PDT 24 19870046 ps
T795 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2153436127 Jul 18 06:44:41 PM PDT 24 Jul 18 06:45:01 PM PDT 24 955650002 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.939302543 Jul 18 06:44:23 PM PDT 24 Jul 18 06:45:32 PM PDT 24 2361315745 ps
T797 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3974277677 Jul 18 06:44:22 PM PDT 24 Jul 18 06:44:41 PM PDT 24 2616374281 ps
T798 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1467103542 Jul 18 06:44:57 PM PDT 24 Jul 18 06:45:16 PM PDT 24 127972774 ps
T183 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3634616156 Jul 18 06:44:42 PM PDT 24 Jul 18 06:47:09 PM PDT 24 3950781270 ps
T799 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.666393845 Jul 18 06:44:52 PM PDT 24 Jul 18 06:45:10 PM PDT 24 495557686 ps
T800 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3885080576 Jul 18 06:44:25 PM PDT 24 Jul 18 06:44:41 PM PDT 24 109860369 ps
T801 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.94363575 Jul 18 06:44:57 PM PDT 24 Jul 18 06:45:18 PM PDT 24 338184712 ps
T802 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4086253357 Jul 18 06:45:01 PM PDT 24 Jul 18 06:45:12 PM PDT 24 495659006 ps
T803 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.126706421 Jul 18 06:44:51 PM PDT 24 Jul 18 06:45:01 PM PDT 24 10297896 ps
T178 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1400953348 Jul 18 06:44:25 PM PDT 24 Jul 18 06:49:50 PM PDT 24 6296492303 ps
T804 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.231713396 Jul 18 06:44:42 PM PDT 24 Jul 18 06:45:03 PM PDT 24 130702603 ps
T805 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.689755539 Jul 18 06:44:39 PM PDT 24 Jul 18 06:44:58 PM PDT 24 201796620 ps
T170 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2123302219 Jul 18 06:44:37 PM PDT 24 Jul 18 06:50:22 PM PDT 24 14997489334 ps
T806 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1213880814 Jul 18 06:44:25 PM PDT 24 Jul 18 06:44:40 PM PDT 24 129772217 ps
T807 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4373997 Jul 18 06:44:51 PM PDT 24 Jul 18 06:45:19 PM PDT 24 291268321 ps
T808 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.106696472 Jul 18 06:45:10 PM PDT 24 Jul 18 06:45:17 PM PDT 24 13214909 ps
T809 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3859310092 Jul 18 06:45:09 PM PDT 24 Jul 18 06:45:16 PM PDT 24 29672392 ps
T171 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1835236039 Jul 18 06:44:37 PM PDT 24 Jul 18 06:49:34 PM PDT 24 7543588094 ps
T810 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1658731153 Jul 18 06:44:34 PM PDT 24 Jul 18 06:44:48 PM PDT 24 38865743 ps
T180 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2969363489 Jul 18 06:44:55 PM PDT 24 Jul 18 06:46:30 PM PDT 24 3010543889 ps
T208 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1331536133 Jul 18 06:44:58 PM PDT 24 Jul 18 06:45:11 PM PDT 24 175097574 ps
T172 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.709004513 Jul 18 06:44:25 PM PDT 24 Jul 18 07:03:21 PM PDT 24 34091553642 ps
T811 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2530146258 Jul 18 06:44:23 PM PDT 24 Jul 18 06:47:58 PM PDT 24 9072186683 ps
T812 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1230509125 Jul 18 06:44:43 PM PDT 24 Jul 18 06:44:55 PM PDT 24 18262407 ps
T186 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.888706519 Jul 18 06:44:54 PM PDT 24 Jul 18 07:01:03 PM PDT 24 235928670569 ps
T813 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4061867962 Jul 18 06:44:53 PM PDT 24 Jul 18 06:50:10 PM PDT 24 2213509866 ps
T814 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.121834242 Jul 18 06:45:01 PM PDT 24 Jul 18 06:45:26 PM PDT 24 305359838 ps
T815 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3414202233 Jul 18 06:45:02 PM PDT 24 Jul 18 06:45:13 PM PDT 24 251736137 ps
T816 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2575512505 Jul 18 06:44:53 PM PDT 24 Jul 18 06:45:05 PM PDT 24 22597778 ps
T817 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1175641094 Jul 18 06:44:38 PM PDT 24 Jul 18 06:47:51 PM PDT 24 1670592965 ps
T818 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1872078895 Jul 18 06:45:07 PM PDT 24 Jul 18 06:45:14 PM PDT 24 13450154 ps
T819 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4170024153 Jul 18 06:44:59 PM PDT 24 Jul 18 06:45:08 PM PDT 24 77514094 ps
T820 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3399270903 Jul 18 06:45:09 PM PDT 24 Jul 18 06:45:16 PM PDT 24 7337694 ps
T821 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1927278104 Jul 18 06:44:43 PM PDT 24 Jul 18 06:45:03 PM PDT 24 127070790 ps
T822 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.501030771 Jul 18 06:44:28 PM PDT 24 Jul 18 06:48:28 PM PDT 24 6532127685 ps
T197 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1698657000 Jul 18 06:44:57 PM PDT 24 Jul 18 06:45:47 PM PDT 24 5996437428 ps
T184 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4105580851 Jul 18 06:44:54 PM PDT 24 Jul 18 06:47:27 PM PDT 24 16753814149 ps
T823 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1984040838 Jul 18 06:44:52 PM PDT 24 Jul 18 06:45:19 PM PDT 24 263278669 ps
T824 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2052515128 Jul 18 06:44:41 PM PDT 24 Jul 18 06:44:57 PM PDT 24 49166351 ps
T825 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2035936170 Jul 18 06:44:56 PM PDT 24 Jul 18 06:45:16 PM PDT 24 140983596 ps
T826 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3326403523 Jul 18 06:44:25 PM PDT 24 Jul 18 06:51:22 PM PDT 24 10960729225 ps
T827 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2236045635 Jul 18 06:44:38 PM PDT 24 Jul 18 06:44:54 PM PDT 24 139613267 ps

Test location /workspace/coverage/default/22.alert_handler_stress_all.1432682520
Short name T19
Test name
Test status
Simulation time 18048184422 ps
CPU time 289.37 seconds
Started Jul 18 04:50:02 PM PDT 24
Finished Jul 18 04:54:53 PM PDT 24
Peak memory 265476 kb
Host smart-532d7e54-b4c1-4364-9ee9-11e2877e5853
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432682520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1432682520
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.510481468
Short name T22
Test name
Test status
Simulation time 755090777722 ps
CPU time 5253.88 seconds
Started Jul 18 04:49:35 PM PDT 24
Finished Jul 18 06:17:10 PM PDT 24
Peak memory 355648 kb
Host smart-e01e235f-5fae-4148-9993-0a1de6511089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510481468 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.510481468
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3523470059
Short name T17
Test name
Test status
Simulation time 248193960 ps
CPU time 10.65 seconds
Started Jul 18 04:49:15 PM PDT 24
Finished Jul 18 04:49:27 PM PDT 24
Peak memory 248852 kb
Host smart-f0472018-d34b-413a-a9f4-b0c18e097836
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3523470059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3523470059
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1205342869
Short name T12
Test name
Test status
Simulation time 1600214626 ps
CPU time 22.13 seconds
Started Jul 18 04:48:54 PM PDT 24
Finished Jul 18 04:49:17 PM PDT 24
Peak memory 274656 kb
Host smart-5e3d9701-97dd-4d32-ac25-0363f86777f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1205342869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1205342869
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2879732308
Short name T188
Test name
Test status
Simulation time 2365359507 ps
CPU time 81.84 seconds
Started Jul 18 06:45:10 PM PDT 24
Finished Jul 18 06:46:38 PM PDT 24
Peak memory 246456 kb
Host smart-4ec5e732-a48a-4da3-8efa-9c349a9d8033
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2879732308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2879732308
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3432955311
Short name T21
Test name
Test status
Simulation time 653957100296 ps
CPU time 2973.46 seconds
Started Jul 18 04:52:02 PM PDT 24
Finished Jul 18 05:41:36 PM PDT 24
Peak memory 305896 kb
Host smart-8a0ca50c-f79a-4075-a434-b209079cf912
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432955311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3432955311
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.29836162
Short name T24
Test name
Test status
Simulation time 31463214310 ps
CPU time 1421.01 seconds
Started Jul 18 04:51:13 PM PDT 24
Finished Jul 18 05:14:57 PM PDT 24
Peak memory 298356 kb
Host smart-9deb70f1-0724-4552-9f12-63bda846399a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29836162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_hand
ler_stress_all.29836162
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1248607833
Short name T64
Test name
Test status
Simulation time 39252642911 ps
CPU time 2170.57 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 05:26:57 PM PDT 24
Peak memory 283980 kb
Host smart-8c15bce5-3c2e-4650-b1c9-962b10291b72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248607833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1248607833
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1660526733
Short name T150
Test name
Test status
Simulation time 5924945247 ps
CPU time 295.66 seconds
Started Jul 18 06:44:51 PM PDT 24
Finished Jul 18 06:49:55 PM PDT 24
Peak memory 273792 kb
Host smart-41216aed-ec17-4303-9551-c4d5fba2fc23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1660526733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1660526733
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1555869526
Short name T221
Test name
Test status
Simulation time 277850115725 ps
CPU time 5451.02 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 06:21:08 PM PDT 24
Peak memory 321988 kb
Host smart-57802144-b3a3-4f1f-ba07-0dd8393cf164
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555869526 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1555869526
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2734954604
Short name T25
Test name
Test status
Simulation time 305332102335 ps
CPU time 2010.41 seconds
Started Jul 18 04:50:48 PM PDT 24
Finished Jul 18 05:24:22 PM PDT 24
Peak memory 273292 kb
Host smart-68588cdf-1885-4854-b887-d1a462a024f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734954604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2734954604
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3131939100
Short name T152
Test name
Test status
Simulation time 18258179577 ps
CPU time 629.14 seconds
Started Jul 18 06:44:36 PM PDT 24
Finished Jul 18 06:55:16 PM PDT 24
Peak memory 273692 kb
Host smart-e8519b86-dda8-4636-8c72-79cbb42c1c86
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131939100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3131939100
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1213746480
Short name T109
Test name
Test status
Simulation time 52171974577 ps
CPU time 257.1 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 04:54:34 PM PDT 24
Peak memory 247904 kb
Host smart-c8dfd9de-9f1b-4746-9983-90e820baefdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213746480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1213746480
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2815256546
Short name T352
Test name
Test status
Simulation time 31869337054 ps
CPU time 1920.68 seconds
Started Jul 18 04:49:12 PM PDT 24
Finished Jul 18 05:21:15 PM PDT 24
Peak memory 284336 kb
Host smart-964f1a8f-dc64-485f-b05f-85f7b2b9f52f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815256546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2815256546
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.274681848
Short name T98
Test name
Test status
Simulation time 188266583645 ps
CPU time 517.05 seconds
Started Jul 18 04:51:13 PM PDT 24
Finished Jul 18 04:59:53 PM PDT 24
Peak memory 256472 kb
Host smart-eacfc503-1061-4021-b059-adebb27fed53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274681848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.274681848
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1691248827
Short name T149
Test name
Test status
Simulation time 16540326895 ps
CPU time 546.74 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:53:59 PM PDT 24
Peak memory 266608 kb
Host smart-6cee2a07-b273-48cc-8ee5-cc2399301336
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691248827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1691248827
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1432422189
Short name T28
Test name
Test status
Simulation time 40345282108 ps
CPU time 831.43 seconds
Started Jul 18 04:50:04 PM PDT 24
Finished Jul 18 05:03:57 PM PDT 24
Peak memory 273596 kb
Host smart-7a80fe94-aef8-42ef-8d69-2c42d6623ab2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432422189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1432422189
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2405249470
Short name T179
Test name
Test status
Simulation time 105802451921 ps
CPU time 987.76 seconds
Started Jul 18 06:44:53 PM PDT 24
Finished Jul 18 07:01:30 PM PDT 24
Peak memory 265632 kb
Host smart-40fedc99-0891-4cac-9acb-433e81f1ccb7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405249470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2405249470
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.635490804
Short name T263
Test name
Test status
Simulation time 45957545642 ps
CPU time 2412.67 seconds
Started Jul 18 04:52:07 PM PDT 24
Finished Jul 18 05:32:21 PM PDT 24
Peak memory 283280 kb
Host smart-f89c9983-4585-4625-8a93-e186ab29e80d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635490804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.635490804
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1859760799
Short name T364
Test name
Test status
Simulation time 10309525 ps
CPU time 1.6 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:44:53 PM PDT 24
Peak memory 237776 kb
Host smart-8b9f11e4-28fe-422b-b513-6947f3b71521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1859760799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1859760799
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1540475195
Short name T162
Test name
Test status
Simulation time 5553600067 ps
CPU time 396.87 seconds
Started Jul 18 06:45:00 PM PDT 24
Finished Jul 18 06:51:44 PM PDT 24
Peak memory 265832 kb
Host smart-d092af1f-c2f4-427b-95e7-4ce96bf61e8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1540475195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1540475195
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3663427565
Short name T10
Test name
Test status
Simulation time 43945469181 ps
CPU time 488.68 seconds
Started Jul 18 04:51:53 PM PDT 24
Finished Jul 18 05:00:03 PM PDT 24
Peak memory 249004 kb
Host smart-10d6779f-7925-4a03-82fb-6d4bf567d48d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663427565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3663427565
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.888706519
Short name T186
Test name
Test status
Simulation time 235928670569 ps
CPU time 960.98 seconds
Started Jul 18 06:44:54 PM PDT 24
Finished Jul 18 07:01:03 PM PDT 24
Peak memory 265564 kb
Host smart-5714addd-be7d-43f6-8a0e-88c11cb68772
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888706519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.888706519
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.632293902
Short name T154
Test name
Test status
Simulation time 11477989119 ps
CPU time 190.36 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:48:04 PM PDT 24
Peak memory 265604 kb
Host smart-2ebd4eaf-3100-4daa-adb5-6bbb95e5eaff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=632293902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.632293902
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3149122175
Short name T97
Test name
Test status
Simulation time 30041721172 ps
CPU time 1293.43 seconds
Started Jul 18 04:49:52 PM PDT 24
Finished Jul 18 05:11:27 PM PDT 24
Peak memory 281820 kb
Host smart-6fd97095-147c-4a03-93cd-4957a9d29b34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149122175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3149122175
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1437438230
Short name T9
Test name
Test status
Simulation time 59004378741 ps
CPU time 536.38 seconds
Started Jul 18 04:51:16 PM PDT 24
Finished Jul 18 05:00:14 PM PDT 24
Peak memory 249012 kb
Host smart-ea2d4b59-b235-4602-a34f-da8fecf78ee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437438230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1437438230
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3510480591
Short name T146
Test name
Test status
Simulation time 147463769564 ps
CPU time 1983.97 seconds
Started Jul 18 04:49:47 PM PDT 24
Finished Jul 18 05:22:52 PM PDT 24
Peak memory 283180 kb
Host smart-9037d25a-4a65-4c0e-a0f2-d058acece818
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510480591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3510480591
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.2641885227
Short name T258
Test name
Test status
Simulation time 67926290089 ps
CPU time 4225.36 seconds
Started Jul 18 04:51:23 PM PDT 24
Finished Jul 18 06:01:49 PM PDT 24
Peak memory 306000 kb
Host smart-dfe565c1-45f8-459a-ae29-ff9626ffd11b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641885227 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.2641885227
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2377684359
Short name T317
Test name
Test status
Simulation time 29743970781 ps
CPU time 551.83 seconds
Started Jul 18 04:49:46 PM PDT 24
Finished Jul 18 04:58:59 PM PDT 24
Peak memory 248920 kb
Host smart-708965ab-4e60-45ea-aa84-c30aa5965979
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377684359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2377684359
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2042344888
Short name T151
Test name
Test status
Simulation time 6284565309 ps
CPU time 197.94 seconds
Started Jul 18 06:44:39 PM PDT 24
Finished Jul 18 06:48:08 PM PDT 24
Peak memory 265600 kb
Host smart-7f92ce50-eae8-47a0-80c1-42201893826e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2042344888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2042344888
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.4268972274
Short name T220
Test name
Test status
Simulation time 126072573403 ps
CPU time 3450.97 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 05:47:50 PM PDT 24
Peak memory 298176 kb
Host smart-cbd97826-a414-4e84-9506-f7809fc502c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268972274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.4268972274
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3580928496
Short name T118
Test name
Test status
Simulation time 529598303637 ps
CPU time 2611.44 seconds
Started Jul 18 04:51:15 PM PDT 24
Finished Jul 18 05:34:49 PM PDT 24
Peak memory 289784 kb
Host smart-33229ecb-74ad-429c-bc7b-130910524179
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580928496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3580928496
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.567942034
Short name T126
Test name
Test status
Simulation time 72671917123 ps
CPU time 2108.36 seconds
Started Jul 18 04:51:12 PM PDT 24
Finished Jul 18 05:26:24 PM PDT 24
Peak memory 273372 kb
Host smart-6504eae6-1c05-4017-9501-72ac41a85a94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567942034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.567942034
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1835236039
Short name T171
Test name
Test status
Simulation time 7543588094 ps
CPU time 285.58 seconds
Started Jul 18 06:44:37 PM PDT 24
Finished Jul 18 06:49:34 PM PDT 24
Peak memory 265604 kb
Host smart-f6ab137b-02b6-42f2-bc36-d888aa7dac61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1835236039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1835236039
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.575213925
Short name T49
Test name
Test status
Simulation time 50237154289 ps
CPU time 3252.76 seconds
Started Jul 18 04:50:02 PM PDT 24
Finished Jul 18 05:44:17 PM PDT 24
Peak memory 306312 kb
Host smart-2621d722-3ef0-4ca4-89ee-d5a990fc720b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575213925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.575213925
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1239402538
Short name T200
Test name
Test status
Simulation time 85566975 ps
CPU time 5.18 seconds
Started Jul 18 06:45:02 PM PDT 24
Finished Jul 18 06:45:13 PM PDT 24
Peak memory 236820 kb
Host smart-926e704c-84e0-411b-ac88-cb0d98081658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1239402538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1239402538
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1984997443
Short name T713
Test name
Test status
Simulation time 15899367 ps
CPU time 1.62 seconds
Started Jul 18 06:45:06 PM PDT 24
Finished Jul 18 06:45:13 PM PDT 24
Peak memory 237788 kb
Host smart-3c721c3a-7459-4ebf-8157-ed84f65085bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1984997443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1984997443
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2227393661
Short name T99
Test name
Test status
Simulation time 43068494152 ps
CPU time 1125.82 seconds
Started Jul 18 04:49:58 PM PDT 24
Finished Jul 18 05:08:45 PM PDT 24
Peak memory 273516 kb
Host smart-ef454f2a-def1-45e2-af31-da06a3e995f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227393661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2227393661
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1313355843
Short name T134
Test name
Test status
Simulation time 30635577182 ps
CPU time 1417.44 seconds
Started Jul 18 04:50:08 PM PDT 24
Finished Jul 18 05:13:47 PM PDT 24
Peak memory 267828 kb
Host smart-10fdec39-f9f5-4c5d-afcc-93719de39132
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313355843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1313355843
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1749702099
Short name T350
Test name
Test status
Simulation time 83837698088 ps
CPU time 1558.17 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 05:16:48 PM PDT 24
Peak memory 273536 kb
Host smart-c1e3f6e8-4214-410b-9b70-6468d3466fda
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749702099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1749702099
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2280421334
Short name T276
Test name
Test status
Simulation time 52595195555 ps
CPU time 3435.71 seconds
Started Jul 18 04:51:37 PM PDT 24
Finished Jul 18 05:48:54 PM PDT 24
Peak memory 305236 kb
Host smart-f25f13bf-abc0-4f16-bf18-b16fbb32959f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280421334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2280421334
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1645416023
Short name T166
Test name
Test status
Simulation time 5086352114 ps
CPU time 358.6 seconds
Started Jul 18 06:44:42 PM PDT 24
Finished Jul 18 06:50:52 PM PDT 24
Peak memory 265780 kb
Host smart-4d41a7c7-2cd1-4186-9ee6-5e7970c36352
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1645416023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1645416023
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1134954822
Short name T181
Test name
Test status
Simulation time 4438550142 ps
CPU time 627.9 seconds
Started Jul 18 06:44:53 PM PDT 24
Finished Jul 18 06:55:29 PM PDT 24
Peak memory 273736 kb
Host smart-2adb98be-8867-40a5-914a-7b02ab48f2b8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134954822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1134954822
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.860236951
Short name T328
Test name
Test status
Simulation time 15158154373 ps
CPU time 306.11 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 04:54:52 PM PDT 24
Peak memory 248672 kb
Host smart-44543333-7700-442d-8d23-91ed3843a621
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860236951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.860236951
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2602340502
Short name T295
Test name
Test status
Simulation time 26377095064 ps
CPU time 1428.72 seconds
Started Jul 18 04:52:02 PM PDT 24
Finished Jul 18 05:15:52 PM PDT 24
Peak memory 289768 kb
Host smart-a298ae26-69e5-4789-9e3a-0673b924ff71
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602340502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2602340502
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1959989767
Short name T232
Test name
Test status
Simulation time 645099372 ps
CPU time 3.74 seconds
Started Jul 18 04:48:51 PM PDT 24
Finished Jul 18 04:48:57 PM PDT 24
Peak memory 249132 kb
Host smart-3af7d42a-4a9d-47f9-95d4-c071dea562b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1959989767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1959989767
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3718183044
Short name T236
Test name
Test status
Simulation time 56623106 ps
CPU time 2.43 seconds
Started Jul 18 04:48:54 PM PDT 24
Finished Jul 18 04:48:57 PM PDT 24
Peak memory 249136 kb
Host smart-8d31c185-0825-4f58-9269-b12630897003
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3718183044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3718183044
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3056290131
Short name T71
Test name
Test status
Simulation time 39488635 ps
CPU time 3.34 seconds
Started Jul 18 04:49:41 PM PDT 24
Finished Jul 18 04:49:46 PM PDT 24
Peak memory 249144 kb
Host smart-bfcaed1f-cfc3-4e7d-a243-6e4578f6061d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3056290131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3056290131
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.250812408
Short name T241
Test name
Test status
Simulation time 124281667 ps
CPU time 3.12 seconds
Started Jul 18 04:49:56 PM PDT 24
Finished Jul 18 04:50:01 PM PDT 24
Peak memory 249156 kb
Host smart-e048af56-282f-4ca1-9fc6-d6558fc6c189
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=250812408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.250812408
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3847717005
Short name T676
Test name
Test status
Simulation time 301320180499 ps
CPU time 2435.1 seconds
Started Jul 18 04:48:44 PM PDT 24
Finished Jul 18 05:29:21 PM PDT 24
Peak memory 289636 kb
Host smart-0fd40bf9-07c7-43fe-bf76-0ebb57b632a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847717005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3847717005
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1677513788
Short name T275
Test name
Test status
Simulation time 1909785134 ps
CPU time 53.89 seconds
Started Jul 18 04:48:46 PM PDT 24
Finished Jul 18 04:49:43 PM PDT 24
Peak memory 248232 kb
Host smart-d4c462f9-0579-43c4-a8c5-26b4357eba6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16775
13788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1677513788
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3024501052
Short name T320
Test name
Test status
Simulation time 65075539098 ps
CPU time 668.39 seconds
Started Jul 18 04:48:47 PM PDT 24
Finished Jul 18 04:59:58 PM PDT 24
Peak memory 249008 kb
Host smart-bddbdbb4-087a-4977-9168-0cf3b4140b7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024501052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3024501052
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3377518341
Short name T290
Test name
Test status
Simulation time 1353957376 ps
CPU time 37.1 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 04:51:25 PM PDT 24
Peak memory 249256 kb
Host smart-1f3144c9-ac71-4dd0-8d32-565df2ffc13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33775
18341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3377518341
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.205857050
Short name T260
Test name
Test status
Simulation time 54670162727 ps
CPU time 3268.87 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 05:45:39 PM PDT 24
Peak memory 298184 kb
Host smart-007c27c9-7706-4729-978b-e165eaf4e137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205857050 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.205857050
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.338537525
Short name T346
Test name
Test status
Simulation time 120863816721 ps
CPU time 1499.83 seconds
Started Jul 18 04:51:12 PM PDT 24
Finished Jul 18 05:16:15 PM PDT 24
Peak memory 273004 kb
Host smart-d56d5419-00b7-4eb9-a1ae-336cb70444c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338537525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.338537525
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.494670512
Short name T305
Test name
Test status
Simulation time 114832809322 ps
CPU time 1769.46 seconds
Started Jul 18 04:51:15 PM PDT 24
Finished Jul 18 05:20:47 PM PDT 24
Peak memory 284952 kb
Host smart-7ff0446b-2c38-43df-bfae-68c7cbfd250d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494670512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.494670512
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2394865465
Short name T302
Test name
Test status
Simulation time 403453026629 ps
CPU time 3609.09 seconds
Started Jul 18 04:51:19 PM PDT 24
Finished Jul 18 05:51:29 PM PDT 24
Peak memory 301548 kb
Host smart-35be81d1-a644-4548-a819-d158b5558bd0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394865465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2394865465
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1569587633
Short name T297
Test name
Test status
Simulation time 356809830634 ps
CPU time 2724.95 seconds
Started Jul 18 04:49:33 PM PDT 24
Finished Jul 18 05:34:59 PM PDT 24
Peak memory 289080 kb
Host smart-fe68b527-dfe5-4de4-a6f7-cabe6a1bdc18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569587633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1569587633
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1626345150
Short name T160
Test name
Test status
Simulation time 5279927662 ps
CPU time 182.57 seconds
Started Jul 18 06:45:08 PM PDT 24
Finished Jul 18 06:48:16 PM PDT 24
Peak memory 265596 kb
Host smart-9a10abb2-0326-4d40-9bfb-b8fb5c9ec6f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1626345150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1626345150
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2595939838
Short name T45
Test name
Test status
Simulation time 1409501888 ps
CPU time 30.33 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 04:50:16 PM PDT 24
Peak memory 248912 kb
Host smart-a86f427d-5497-41be-a921-2c0574bb5385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25959
39838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2595939838
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1809029989
Short name T177
Test name
Test status
Simulation time 25503880274 ps
CPU time 541.1 seconds
Started Jul 18 06:44:21 PM PDT 24
Finished Jul 18 06:53:32 PM PDT 24
Peak memory 273228 kb
Host smart-5f7210c2-9051-4c4e-ad58-8e75c6821158
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809029989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1809029989
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2969363489
Short name T180
Test name
Test status
Simulation time 3010543889 ps
CPU time 86.92 seconds
Started Jul 18 06:44:55 PM PDT 24
Finished Jul 18 06:46:30 PM PDT 24
Peak memory 265736 kb
Host smart-635419cc-cdf5-4c88-82f5-cdd2f387fe1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2969363489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2969363489
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.449253084
Short name T362
Test name
Test status
Simulation time 26058661 ps
CPU time 1.46 seconds
Started Jul 18 06:44:57 PM PDT 24
Finished Jul 18 06:45:06 PM PDT 24
Peak memory 236828 kb
Host smart-2eae1e2e-aab6-43e1-829e-4dff016704c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=449253084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.449253084
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2646825144
Short name T135
Test name
Test status
Simulation time 8070680907 ps
CPU time 121.28 seconds
Started Jul 18 04:48:46 PM PDT 24
Finished Jul 18 04:50:50 PM PDT 24
Peak memory 256892 kb
Host smart-eff96758-98af-439b-bc48-d293ecf99ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26468
25144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2646825144
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3551042884
Short name T626
Test name
Test status
Simulation time 16854988766 ps
CPU time 343.96 seconds
Started Jul 18 04:49:37 PM PDT 24
Finished Jul 18 04:55:22 PM PDT 24
Peak memory 248996 kb
Host smart-10ada770-6cb8-4a14-abd1-5e25460e7e62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551042884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3551042884
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1305766524
Short name T282
Test name
Test status
Simulation time 302159368 ps
CPU time 34.58 seconds
Started Jul 18 04:49:42 PM PDT 24
Finished Jul 18 04:50:18 PM PDT 24
Peak memory 248964 kb
Host smart-ab21975b-f605-4587-84b3-01f75de92d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13057
66524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1305766524
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2405427212
Short name T339
Test name
Test status
Simulation time 29998046944 ps
CPU time 519.2 seconds
Started Jul 18 04:49:56 PM PDT 24
Finished Jul 18 04:58:36 PM PDT 24
Peak memory 248976 kb
Host smart-09616750-2d3e-489e-801c-f43b3f3a30af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405427212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2405427212
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3919465432
Short name T289
Test name
Test status
Simulation time 1665622206 ps
CPU time 48.26 seconds
Started Jul 18 04:49:59 PM PDT 24
Finished Jul 18 04:50:50 PM PDT 24
Peak memory 248928 kb
Host smart-89f64530-eb3c-4b65-8e08-91d5b84e79e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39194
65432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3919465432
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2979504534
Short name T143
Test name
Test status
Simulation time 28688367559 ps
CPU time 1633.99 seconds
Started Jul 18 04:49:58 PM PDT 24
Finished Jul 18 05:17:13 PM PDT 24
Peak memory 282272 kb
Host smart-09cac0ea-5def-490f-bc85-5b7653d02bab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979504534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2979504534
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.4261100667
Short name T67
Test name
Test status
Simulation time 198526658 ps
CPU time 20.61 seconds
Started Jul 18 04:50:00 PM PDT 24
Finished Jul 18 04:50:22 PM PDT 24
Peak memory 256176 kb
Host smart-d7e73b63-b6bf-42da-a82a-fe45c12ca22a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42611
00667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.4261100667
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.944632250
Short name T285
Test name
Test status
Simulation time 1020912248763 ps
CPU time 4985.89 seconds
Started Jul 18 04:50:47 PM PDT 24
Finished Jul 18 06:13:57 PM PDT 24
Peak memory 338676 kb
Host smart-cd714967-a6a2-4416-8f41-990134f5a4f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944632250 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.944632250
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1625540104
Short name T309
Test name
Test status
Simulation time 3745204668 ps
CPU time 164.31 seconds
Started Jul 18 04:49:17 PM PDT 24
Finished Jul 18 04:52:03 PM PDT 24
Peak memory 257076 kb
Host smart-ac429602-bc5f-4b2e-a0ec-070ba0707ff2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625540104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1625540104
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1110153055
Short name T286
Test name
Test status
Simulation time 228722435 ps
CPU time 30.19 seconds
Started Jul 18 04:51:32 PM PDT 24
Finished Jul 18 04:52:04 PM PDT 24
Peak memory 248920 kb
Host smart-5656d61c-f9c2-441d-89fa-e7d002c3c14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11101
53055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1110153055
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.505212765
Short name T269
Test name
Test status
Simulation time 13824222792 ps
CPU time 1456.4 seconds
Started Jul 18 04:52:05 PM PDT 24
Finished Jul 18 05:16:23 PM PDT 24
Peak memory 298976 kb
Host smart-77a72ed3-7aa6-4776-b645-dbff3e72c3b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505212765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.505212765
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.759742716
Short name T60
Test name
Test status
Simulation time 71863265348 ps
CPU time 6810.42 seconds
Started Jul 18 04:52:05 PM PDT 24
Finished Jul 18 06:45:37 PM PDT 24
Peak memory 366544 kb
Host smart-f1bfb65b-ae39-48fa-9515-1938fb5f1133
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759742716 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.759742716
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1829400003
Short name T199
Test name
Test status
Simulation time 4686796351 ps
CPU time 76.55 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:46:10 PM PDT 24
Peak memory 248088 kb
Host smart-07fe9a8f-7865-4050-894f-66b5de54c75b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1829400003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1829400003
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3976998501
Short name T153
Test name
Test status
Simulation time 2136133312 ps
CPU time 161.79 seconds
Started Jul 18 06:44:25 PM PDT 24
Finished Jul 18 06:47:18 PM PDT 24
Peak memory 265476 kb
Host smart-73d782b0-9f62-4702-8372-2834d1d29794
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3976998501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3976998501
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2768992344
Short name T165
Test name
Test status
Simulation time 5174781175 ps
CPU time 711 seconds
Started Jul 18 06:44:52 PM PDT 24
Finished Jul 18 06:56:52 PM PDT 24
Peak memory 273744 kb
Host smart-351299e3-da76-407b-9f03-be8a03d5a23b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768992344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2768992344
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3151597772
Short name T194
Test name
Test status
Simulation time 105345891 ps
CPU time 2.19 seconds
Started Jul 18 06:44:55 PM PDT 24
Finished Jul 18 06:45:05 PM PDT 24
Peak memory 237768 kb
Host smart-652f3446-7e26-4fd5-a5b5-ebaa3cc7d5f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3151597772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3151597772
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.381137437
Short name T196
Test name
Test status
Simulation time 603730012 ps
CPU time 23.1 seconds
Started Jul 18 06:44:54 PM PDT 24
Finished Jul 18 06:45:25 PM PDT 24
Peak memory 240756 kb
Host smart-0ae218b8-c38e-410e-aab3-ea882502569b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=381137437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.381137437
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1698657000
Short name T197
Test name
Test status
Simulation time 5996437428 ps
CPU time 42.31 seconds
Started Jul 18 06:44:57 PM PDT 24
Finished Jul 18 06:45:47 PM PDT 24
Peak memory 248916 kb
Host smart-f0823490-374b-440a-ae15-d4f096ad75b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1698657000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1698657000
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1331536133
Short name T208
Test name
Test status
Simulation time 175097574 ps
CPU time 5.08 seconds
Started Jul 18 06:44:58 PM PDT 24
Finished Jul 18 06:45:11 PM PDT 24
Peak memory 237772 kb
Host smart-2a21adbf-fea8-4d62-894e-398850c2f385
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1331536133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1331536133
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.786867690
Short name T163
Test name
Test status
Simulation time 66975719638 ps
CPU time 311.56 seconds
Started Jul 18 06:44:36 PM PDT 24
Finished Jul 18 06:49:58 PM PDT 24
Peak memory 265612 kb
Host smart-58fc79d8-5ab4-4998-b5a1-04291d6967a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=786867690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.786867690
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3189812063
Short name T189
Test name
Test status
Simulation time 150470184 ps
CPU time 21.16 seconds
Started Jul 18 06:44:40 PM PDT 24
Finished Jul 18 06:45:13 PM PDT 24
Peak memory 240792 kb
Host smart-f6598496-4a71-4dc0-94e3-176dd075251d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3189812063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3189812063
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.327714723
Short name T206
Test name
Test status
Simulation time 651031766 ps
CPU time 44.66 seconds
Started Jul 18 06:44:23 PM PDT 24
Finished Jul 18 06:45:17 PM PDT 24
Peak memory 238008 kb
Host smart-07b8419b-ecc1-4fbe-9ec5-b298fe5e18af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=327714723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.327714723
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.639067888
Short name T203
Test name
Test status
Simulation time 62978542 ps
CPU time 4.03 seconds
Started Jul 18 06:44:25 PM PDT 24
Finished Jul 18 06:44:41 PM PDT 24
Peak memory 237756 kb
Host smart-77f73e41-ad5c-421d-9dc1-15bd5371cce5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=639067888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.639067888
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3506592008
Short name T198
Test name
Test status
Simulation time 457280449 ps
CPU time 34.93 seconds
Started Jul 18 06:44:52 PM PDT 24
Finished Jul 18 06:45:35 PM PDT 24
Peak memory 240724 kb
Host smart-ddef10ad-a189-4b9c-8d28-a5bc33f50a59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3506592008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3506592008
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.4110011807
Short name T201
Test name
Test status
Simulation time 320835112 ps
CPU time 23.08 seconds
Started Jul 18 06:44:50 PM PDT 24
Finished Jul 18 06:45:22 PM PDT 24
Peak memory 238140 kb
Host smart-0ed356ed-8ba7-46b0-9566-ba2977457590
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4110011807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.4110011807
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1743649213
Short name T193
Test name
Test status
Simulation time 31134717 ps
CPU time 2.96 seconds
Started Jul 18 06:44:58 PM PDT 24
Finished Jul 18 06:45:09 PM PDT 24
Peak memory 238792 kb
Host smart-a2d9695c-8465-4972-9a55-44891db2affe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1743649213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1743649213
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2795595757
Short name T202
Test name
Test status
Simulation time 50054177 ps
CPU time 3.54 seconds
Started Jul 18 06:44:38 PM PDT 24
Finished Jul 18 06:44:52 PM PDT 24
Peak memory 237984 kb
Host smart-1922b89d-99bf-4b0a-b890-941587667f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2795595757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2795595757
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.4129348814
Short name T187
Test name
Test status
Simulation time 56169029 ps
CPU time 2.8 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:44:55 PM PDT 24
Peak memory 237796 kb
Host smart-0c8b39a6-d2da-4c35-9c6e-2e7fbc06b717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4129348814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.4129348814
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3434004579
Short name T20
Test name
Test status
Simulation time 36013820788 ps
CPU time 859.36 seconds
Started Jul 18 04:50:17 PM PDT 24
Finished Jul 18 05:04:39 PM PDT 24
Peak memory 273648 kb
Host smart-10887672-7f36-41da-a668-2138023a93e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434004579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3434004579
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2423908601
Short name T754
Test name
Test status
Simulation time 1074176617 ps
CPU time 151.52 seconds
Started Jul 18 06:44:25 PM PDT 24
Finished Jul 18 06:47:08 PM PDT 24
Peak memory 241480 kb
Host smart-60d92f73-dc20-473b-bbb7-0d5a42b084b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2423908601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2423908601
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2530146258
Short name T811
Test name
Test status
Simulation time 9072186683 ps
CPU time 204.57 seconds
Started Jul 18 06:44:23 PM PDT 24
Finished Jul 18 06:47:58 PM PDT 24
Peak memory 237812 kb
Host smart-e5e5608b-b247-4fba-b928-bf2faba45ab7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2530146258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2530146258
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.4252350409
Short name T757
Test name
Test status
Simulation time 102471813 ps
CPU time 8.79 seconds
Started Jul 18 06:44:24 PM PDT 24
Finished Jul 18 06:44:43 PM PDT 24
Peak memory 249340 kb
Host smart-e56d5618-40aa-41dc-8015-7de1db662dab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4252350409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.4252350409
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1739816463
Short name T715
Test name
Test status
Simulation time 287317984 ps
CPU time 6.56 seconds
Started Jul 18 06:44:23 PM PDT 24
Finished Jul 18 06:44:40 PM PDT 24
Peak memory 241220 kb
Host smart-9855faae-1520-46fd-a48f-83eebc457daf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739816463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1739816463
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2273071188
Short name T766
Test name
Test status
Simulation time 283833360 ps
CPU time 8.32 seconds
Started Jul 18 06:44:25 PM PDT 24
Finished Jul 18 06:44:44 PM PDT 24
Peak memory 237884 kb
Host smart-0ecbf3b8-8397-494f-a302-ac218094c826
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2273071188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2273071188
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.594711033
Short name T743
Test name
Test status
Simulation time 19032219 ps
CPU time 1.48 seconds
Started Jul 18 06:44:25 PM PDT 24
Finished Jul 18 06:44:38 PM PDT 24
Peak memory 237664 kb
Host smart-7dff2f09-090c-4526-bec4-ee679cb144cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=594711033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.594711033
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.4147800897
Short name T706
Test name
Test status
Simulation time 89434407 ps
CPU time 13.31 seconds
Started Jul 18 06:44:24 PM PDT 24
Finished Jul 18 06:44:48 PM PDT 24
Peak memory 245968 kb
Host smart-dd745eb4-d32b-4c0e-8622-db8f52c92a2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4147800897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.4147800897
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3974277677
Short name T797
Test name
Test status
Simulation time 2616374281 ps
CPU time 9.77 seconds
Started Jul 18 06:44:22 PM PDT 24
Finished Jul 18 06:44:41 PM PDT 24
Peak memory 248264 kb
Host smart-630277d2-1603-46ad-83f7-9a00fbcaeb3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3974277677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3974277677
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.939302543
Short name T796
Test name
Test status
Simulation time 2361315745 ps
CPU time 59.59 seconds
Started Jul 18 06:44:23 PM PDT 24
Finished Jul 18 06:45:32 PM PDT 24
Peak memory 240748 kb
Host smart-e18bea62-d89e-42aa-9a91-0b8b16fcbfad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=939302543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.939302543
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3326403523
Short name T826
Test name
Test status
Simulation time 10960729225 ps
CPU time 406.47 seconds
Started Jul 18 06:44:25 PM PDT 24
Finished Jul 18 06:51:22 PM PDT 24
Peak memory 237816 kb
Host smart-590481ec-9edf-4cc5-9c62-1c5891ee1429
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3326403523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3326403523
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4290248637
Short name T765
Test name
Test status
Simulation time 411558617 ps
CPU time 4.73 seconds
Started Jul 18 06:44:23 PM PDT 24
Finished Jul 18 06:44:37 PM PDT 24
Peak memory 240700 kb
Host smart-9fb37bc8-806b-4a4e-929f-6e722f82a5bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4290248637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.4290248637
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.689755539
Short name T805
Test name
Test status
Simulation time 201796620 ps
CPU time 8.17 seconds
Started Jul 18 06:44:39 PM PDT 24
Finished Jul 18 06:44:58 PM PDT 24
Peak memory 257120 kb
Host smart-f6adcbe0-3890-431a-8390-6be81fc808a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689755539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.689755539
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1213880814
Short name T806
Test name
Test status
Simulation time 129772217 ps
CPU time 5.52 seconds
Started Jul 18 06:44:25 PM PDT 24
Finished Jul 18 06:44:40 PM PDT 24
Peak memory 237736 kb
Host smart-5be74140-d897-47b0-a6c0-af4f3217be2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1213880814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1213880814
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.652568384
Short name T363
Test name
Test status
Simulation time 9635941 ps
CPU time 1.25 seconds
Started Jul 18 06:44:23 PM PDT 24
Finished Jul 18 06:44:33 PM PDT 24
Peak memory 235876 kb
Host smart-9a27ae09-8781-4477-b67d-f8d6d1053bbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=652568384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.652568384
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1533637064
Short name T223
Test name
Test status
Simulation time 687698981 ps
CPU time 42.7 seconds
Started Jul 18 06:44:39 PM PDT 24
Finished Jul 18 06:45:33 PM PDT 24
Peak memory 248792 kb
Host smart-a168c8a5-29c9-46d5-b438-aa8138c80a53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1533637064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1533637064
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1400953348
Short name T178
Test name
Test status
Simulation time 6296492303 ps
CPU time 314.42 seconds
Started Jul 18 06:44:25 PM PDT 24
Finished Jul 18 06:49:50 PM PDT 24
Peak memory 273756 kb
Host smart-2f8afddc-e093-4807-8306-dac2dde16fa5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1400953348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1400953348
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.709004513
Short name T172
Test name
Test status
Simulation time 34091553642 ps
CPU time 1125.46 seconds
Started Jul 18 06:44:25 PM PDT 24
Finished Jul 18 07:03:21 PM PDT 24
Peak memory 265792 kb
Host smart-bccd0e1e-492d-4cef-b809-88b8fccfa6ed
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709004513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.709004513
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3885080576
Short name T800
Test name
Test status
Simulation time 109860369 ps
CPU time 4.59 seconds
Started Jul 18 06:44:25 PM PDT 24
Finished Jul 18 06:44:41 PM PDT 24
Peak memory 251628 kb
Host smart-74281700-261d-44f8-bc84-4938e8f65aae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3885080576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3885080576
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.666393845
Short name T799
Test name
Test status
Simulation time 495557686 ps
CPU time 9.7 seconds
Started Jul 18 06:44:52 PM PDT 24
Finished Jul 18 06:45:10 PM PDT 24
Peak memory 240744 kb
Host smart-2dde7338-91dd-46f1-b71c-d9b4a7848d11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666393845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.666393845
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3759763424
Short name T775
Test name
Test status
Simulation time 345934236 ps
CPU time 5.32 seconds
Started Jul 18 06:44:52 PM PDT 24
Finished Jul 18 06:45:05 PM PDT 24
Peak memory 237760 kb
Host smart-c3980f35-aa3a-47da-873b-1e221d574c5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3759763424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3759763424
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1286593886
Short name T755
Test name
Test status
Simulation time 24952827 ps
CPU time 1.5 seconds
Started Jul 18 06:44:54 PM PDT 24
Finished Jul 18 06:45:03 PM PDT 24
Peak memory 237856 kb
Host smart-c7281c80-621f-4e20-ab07-d8ea52b07f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1286593886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1286593886
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2904924080
Short name T792
Test name
Test status
Simulation time 1003499946 ps
CPU time 18.78 seconds
Started Jul 18 06:44:53 PM PDT 24
Finished Jul 18 06:45:20 PM PDT 24
Peak memory 240680 kb
Host smart-76199610-c205-4c59-9311-aa94bece03db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2904924080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2904924080
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3441162150
Short name T176
Test name
Test status
Simulation time 2386078989 ps
CPU time 86.83 seconds
Started Jul 18 06:44:54 PM PDT 24
Finished Jul 18 06:46:29 PM PDT 24
Peak memory 257700 kb
Host smart-87c5eeb7-d5bc-4103-a113-ea05cbf71ead
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3441162150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3441162150
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.4373997
Short name T807
Test name
Test status
Simulation time 291268321 ps
CPU time 19.21 seconds
Started Jul 18 06:44:51 PM PDT 24
Finished Jul 18 06:45:19 PM PDT 24
Peak memory 256048 kb
Host smart-48b4826b-9b99-4054-a622-851b76b059f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4373997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.4373997
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2276783612
Short name T781
Test name
Test status
Simulation time 127653793 ps
CPU time 5.1 seconds
Started Jul 18 06:44:53 PM PDT 24
Finished Jul 18 06:45:06 PM PDT 24
Peak memory 240836 kb
Host smart-737a5167-47fb-4358-bdb0-41c917998bc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276783612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2276783612
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.200076463
Short name T760
Test name
Test status
Simulation time 35829220 ps
CPU time 6.01 seconds
Started Jul 18 06:44:52 PM PDT 24
Finished Jul 18 06:45:06 PM PDT 24
Peak memory 237748 kb
Host smart-ada8af10-594d-48bd-acaf-e4185d6c6255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=200076463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.200076463
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2906994429
Short name T794
Test name
Test status
Simulation time 19870046 ps
CPU time 1.41 seconds
Started Jul 18 06:44:51 PM PDT 24
Finished Jul 18 06:45:00 PM PDT 24
Peak memory 236804 kb
Host smart-ee2c89c8-33fe-4f4c-9ee0-a0517b61f6a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2906994429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2906994429
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1984040838
Short name T823
Test name
Test status
Simulation time 263278669 ps
CPU time 18.36 seconds
Started Jul 18 06:44:52 PM PDT 24
Finished Jul 18 06:45:19 PM PDT 24
Peak memory 245020 kb
Host smart-af9a8c43-9633-4d82-b223-f67a87cb613c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1984040838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1984040838
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2508234407
Short name T720
Test name
Test status
Simulation time 1420915464 ps
CPU time 10.26 seconds
Started Jul 18 06:44:52 PM PDT 24
Finished Jul 18 06:45:11 PM PDT 24
Peak memory 253364 kb
Host smart-676abfef-ebc9-4e5b-b450-2ab4ed55c5df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2508234407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2508234407
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3567803810
Short name T268
Test name
Test status
Simulation time 456274884 ps
CPU time 34.19 seconds
Started Jul 18 06:44:49 PM PDT 24
Finished Jul 18 06:45:32 PM PDT 24
Peak memory 240684 kb
Host smart-ce049b70-74d7-40a8-ab0d-abf41bdaab81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3567803810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3567803810
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1934312090
Short name T785
Test name
Test status
Simulation time 121150191 ps
CPU time 5.48 seconds
Started Jul 18 06:50:29 PM PDT 24
Finished Jul 18 06:50:38 PM PDT 24
Peak memory 257032 kb
Host smart-59148f06-41c4-478f-bb36-42750feccead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934312090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1934312090
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3887245875
Short name T793
Test name
Test status
Simulation time 91979183 ps
CPU time 8.21 seconds
Started Jul 18 06:44:51 PM PDT 24
Finished Jul 18 06:45:08 PM PDT 24
Peak memory 236820 kb
Host smart-10ea144c-7479-4ec7-9256-d45a6abce3db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3887245875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3887245875
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3875936494
Short name T191
Test name
Test status
Simulation time 11617573 ps
CPU time 1.69 seconds
Started Jul 18 06:44:51 PM PDT 24
Finished Jul 18 06:45:02 PM PDT 24
Peak memory 236836 kb
Host smart-ccc37416-f62e-4780-be54-2a123c7f8a4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3875936494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3875936494
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.899324826
Short name T735
Test name
Test status
Simulation time 8314021949 ps
CPU time 35.16 seconds
Started Jul 18 06:44:51 PM PDT 24
Finished Jul 18 06:45:35 PM PDT 24
Peak memory 248992 kb
Host smart-b33868a2-4d07-4e00-8258-e626bc78259d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=899324826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.899324826
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.4105580851
Short name T184
Test name
Test status
Simulation time 16753814149 ps
CPU time 145.04 seconds
Started Jul 18 06:44:54 PM PDT 24
Finished Jul 18 06:47:27 PM PDT 24
Peak memory 269212 kb
Host smart-b064f5b1-13c1-4294-a391-70b454f7f7e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4105580851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.4105580851
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4061867962
Short name T813
Test name
Test status
Simulation time 2213509866 ps
CPU time 308.5 seconds
Started Jul 18 06:44:53 PM PDT 24
Finished Jul 18 06:50:10 PM PDT 24
Peak memory 265636 kb
Host smart-db244253-a348-40cb-aacb-ce3dfa9ba7e4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061867962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.4061867962
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1302066853
Short name T744
Test name
Test status
Simulation time 83864607 ps
CPU time 7.1 seconds
Started Jul 18 06:44:55 PM PDT 24
Finished Jul 18 06:45:09 PM PDT 24
Peak memory 248552 kb
Host smart-371b8052-da14-47e0-a91d-02a3fafe8e75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1302066853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1302066853
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.946617945
Short name T773
Test name
Test status
Simulation time 122435952 ps
CPU time 10.03 seconds
Started Jul 18 06:44:57 PM PDT 24
Finished Jul 18 06:45:15 PM PDT 24
Peak memory 250048 kb
Host smart-591cbbe7-565d-4996-9657-6769794d295c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946617945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.946617945
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2741935993
Short name T716
Test name
Test status
Simulation time 196671864 ps
CPU time 4.96 seconds
Started Jul 18 06:44:51 PM PDT 24
Finished Jul 18 06:45:04 PM PDT 24
Peak memory 237776 kb
Host smart-f596325a-1c69-4493-ac99-674c6c568dd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2741935993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2741935993
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.126706421
Short name T803
Test name
Test status
Simulation time 10297896 ps
CPU time 1.75 seconds
Started Jul 18 06:44:51 PM PDT 24
Finished Jul 18 06:45:01 PM PDT 24
Peak memory 237780 kb
Host smart-30d3713c-5c3a-4b52-91a2-6c7b5f90a376
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=126706421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.126706421
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2849517627
Short name T724
Test name
Test status
Simulation time 2797330533 ps
CPU time 53.04 seconds
Started Jul 18 06:44:56 PM PDT 24
Finished Jul 18 06:45:57 PM PDT 24
Peak memory 248944 kb
Host smart-0ddeedcf-0827-4c73-8e00-b5622d906738
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2849517627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2849517627
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.288498372
Short name T791
Test name
Test status
Simulation time 329952317 ps
CPU time 9.06 seconds
Started Jul 18 06:44:55 PM PDT 24
Finished Jul 18 06:45:12 PM PDT 24
Peak memory 248684 kb
Host smart-91d5844e-472e-46df-b598-ee854f3986c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=288498372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.288498372
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2837961715
Short name T705
Test name
Test status
Simulation time 149401735 ps
CPU time 6.52 seconds
Started Jul 18 06:44:56 PM PDT 24
Finished Jul 18 06:45:10 PM PDT 24
Peak memory 256936 kb
Host smart-a871cf39-4042-46bf-8abf-f85d19668b4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837961715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2837961715
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1423201160
Short name T719
Test name
Test status
Simulation time 64831609 ps
CPU time 5.3 seconds
Started Jul 18 06:45:02 PM PDT 24
Finished Jul 18 06:45:13 PM PDT 24
Peak memory 237764 kb
Host smart-bb243935-f4e0-4664-bc2a-4b6ed8b815dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1423201160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1423201160
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.94363575
Short name T801
Test name
Test status
Simulation time 338184712 ps
CPU time 13.02 seconds
Started Jul 18 06:44:57 PM PDT 24
Finished Jul 18 06:45:18 PM PDT 24
Peak memory 248900 kb
Host smart-37eedb27-c632-43fa-82eb-ca579d99b1e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=94363575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outs
tanding.94363575
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.792576245
Short name T156
Test name
Test status
Simulation time 6474538903 ps
CPU time 106.5 seconds
Started Jul 18 06:44:56 PM PDT 24
Finished Jul 18 06:46:50 PM PDT 24
Peak memory 265580 kb
Host smart-bc53e378-f4e4-49ce-8040-52c483f05e2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=792576245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.792576245
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2035936170
Short name T825
Test name
Test status
Simulation time 140983596 ps
CPU time 12.05 seconds
Started Jul 18 06:44:56 PM PDT 24
Finished Jul 18 06:45:16 PM PDT 24
Peak memory 248972 kb
Host smart-f916764b-d94c-4f35-b16a-5a27b0d3c9a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2035936170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2035936170
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1467103542
Short name T798
Test name
Test status
Simulation time 127972774 ps
CPU time 10.59 seconds
Started Jul 18 06:44:57 PM PDT 24
Finished Jul 18 06:45:16 PM PDT 24
Peak memory 252044 kb
Host smart-cff5380a-f93e-4910-968c-b891cfe632d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467103542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1467103542
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1345542169
Short name T204
Test name
Test status
Simulation time 28105058 ps
CPU time 3.58 seconds
Started Jul 18 06:44:52 PM PDT 24
Finished Jul 18 06:45:03 PM PDT 24
Peak memory 237772 kb
Host smart-5bfc318d-1c8d-4773-9da7-25b17257ffd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1345542169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1345542169
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.650718329
Short name T366
Test name
Test status
Simulation time 7812551 ps
CPU time 1.33 seconds
Started Jul 18 06:44:57 PM PDT 24
Finished Jul 18 06:45:06 PM PDT 24
Peak memory 235876 kb
Host smart-c89a4360-cc6b-4292-8d37-59b4f0201802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=650718329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.650718329
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1550855680
Short name T778
Test name
Test status
Simulation time 388776309 ps
CPU time 24.81 seconds
Started Jul 18 06:45:02 PM PDT 24
Finished Jul 18 06:45:32 PM PDT 24
Peak memory 248908 kb
Host smart-fff0de78-bc41-49a8-a690-89630edf8473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1550855680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1550855680
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.502861477
Short name T167
Test name
Test status
Simulation time 18186199344 ps
CPU time 182.42 seconds
Started Jul 18 06:44:58 PM PDT 24
Finished Jul 18 06:48:08 PM PDT 24
Peak memory 272876 kb
Host smart-ca90ea89-f8f6-4d4e-a8c1-68b2c16441a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=502861477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.502861477
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1470187176
Short name T155
Test name
Test status
Simulation time 13603226494 ps
CPU time 291.74 seconds
Started Jul 18 06:44:55 PM PDT 24
Finished Jul 18 06:49:54 PM PDT 24
Peak memory 265812 kb
Host smart-7c7e29eb-00ec-410d-9188-6ee16ee0588a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470187176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1470187176
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.121834242
Short name T814
Test name
Test status
Simulation time 305359838 ps
CPU time 18.41 seconds
Started Jul 18 06:45:01 PM PDT 24
Finished Jul 18 06:45:26 PM PDT 24
Peak memory 248976 kb
Host smart-3e1554aa-3d7c-4246-8388-63ac95802133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=121834242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.121834242
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2744452884
Short name T368
Test name
Test status
Simulation time 55825468 ps
CPU time 5.29 seconds
Started Jul 18 06:44:58 PM PDT 24
Finished Jul 18 06:45:11 PM PDT 24
Peak memory 240720 kb
Host smart-2af8aff2-a0c0-4bd8-a4eb-60645e5acff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744452884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2744452884
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3414202233
Short name T815
Test name
Test status
Simulation time 251736137 ps
CPU time 5.02 seconds
Started Jul 18 06:45:02 PM PDT 24
Finished Jul 18 06:45:13 PM PDT 24
Peak memory 237764 kb
Host smart-a2592884-1c14-47ff-9755-a76af94ed847
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3414202233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3414202233
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4170024153
Short name T819
Test name
Test status
Simulation time 77514094 ps
CPU time 1.51 seconds
Started Jul 18 06:44:59 PM PDT 24
Finished Jul 18 06:45:08 PM PDT 24
Peak memory 237644 kb
Host smart-29423b5c-e9df-4b85-ad97-05fc7f0c43be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4170024153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.4170024153
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1169091946
Short name T729
Test name
Test status
Simulation time 699076835 ps
CPU time 22.15 seconds
Started Jul 18 06:45:00 PM PDT 24
Finished Jul 18 06:45:29 PM PDT 24
Peak memory 245972 kb
Host smart-a288c6f6-ca95-44ff-aa47-109d639ccb9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1169091946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1169091946
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1400278753
Short name T174
Test name
Test status
Simulation time 3965961351 ps
CPU time 145.25 seconds
Started Jul 18 06:44:59 PM PDT 24
Finished Jul 18 06:47:31 PM PDT 24
Peak memory 265612 kb
Host smart-88a72da3-981d-485b-8d00-a65329030d1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1400278753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1400278753
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.978956757
Short name T148
Test name
Test status
Simulation time 5083480374 ps
CPU time 281.83 seconds
Started Jul 18 06:44:57 PM PDT 24
Finished Jul 18 06:49:47 PM PDT 24
Peak memory 265560 kb
Host smart-db157123-36a3-4c61-ac99-6f601c3719c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978956757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.978956757
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3870365548
Short name T261
Test name
Test status
Simulation time 3600583718 ps
CPU time 14.53 seconds
Started Jul 18 06:44:54 PM PDT 24
Finished Jul 18 06:45:16 PM PDT 24
Peak memory 253816 kb
Host smart-637b5e37-806e-4e77-8eb3-63c353cf9ea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3870365548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3870365548
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4086253357
Short name T802
Test name
Test status
Simulation time 495659006 ps
CPU time 5.26 seconds
Started Jul 18 06:45:01 PM PDT 24
Finished Jul 18 06:45:12 PM PDT 24
Peak memory 240760 kb
Host smart-1cd538a3-09c5-4b25-976f-b2ecc55f9268
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086253357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.4086253357
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2575512505
Short name T816
Test name
Test status
Simulation time 22597778 ps
CPU time 3.4 seconds
Started Jul 18 06:44:53 PM PDT 24
Finished Jul 18 06:45:05 PM PDT 24
Peak memory 236820 kb
Host smart-17f1aa2b-6ee8-4168-b2f9-58a7fef07eb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2575512505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2575512505
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2273609866
Short name T739
Test name
Test status
Simulation time 15410955 ps
CPU time 1.81 seconds
Started Jul 18 06:44:54 PM PDT 24
Finished Jul 18 06:45:04 PM PDT 24
Peak memory 235784 kb
Host smart-1b213cd6-8bda-475a-b044-75c960c62995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2273609866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2273609866
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1804034613
Short name T788
Test name
Test status
Simulation time 2295337946 ps
CPU time 37.54 seconds
Started Jul 18 06:44:53 PM PDT 24
Finished Jul 18 06:45:39 PM PDT 24
Peak memory 248952 kb
Host smart-05a23d5e-744b-4e25-905f-813fc832c1ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1804034613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1804034613
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2902131488
Short name T158
Test name
Test status
Simulation time 12787617641 ps
CPU time 956.54 seconds
Started Jul 18 06:44:59 PM PDT 24
Finished Jul 18 07:01:03 PM PDT 24
Peak memory 265592 kb
Host smart-8b72d14c-c1c5-47a5-b947-d4d83f273bea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902131488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2902131488
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1240681193
Short name T748
Test name
Test status
Simulation time 158844215 ps
CPU time 12.23 seconds
Started Jul 18 06:45:00 PM PDT 24
Finished Jul 18 06:45:19 PM PDT 24
Peak memory 252044 kb
Host smart-e63e31f4-e703-4f30-9af0-89ed93bb87fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1240681193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1240681193
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2148471429
Short name T369
Test name
Test status
Simulation time 77009579 ps
CPU time 6.08 seconds
Started Jul 18 06:45:09 PM PDT 24
Finished Jul 18 06:45:20 PM PDT 24
Peak memory 239828 kb
Host smart-2c5b3b91-f873-4b09-873d-0843f8a985fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148471429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2148471429
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1745326830
Short name T721
Test name
Test status
Simulation time 672563577 ps
CPU time 7.4 seconds
Started Jul 18 06:45:08 PM PDT 24
Finished Jul 18 06:45:21 PM PDT 24
Peak memory 236816 kb
Host smart-691d8ca1-8f3b-43aa-b49a-a505bd321ef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1745326830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1745326830
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2637939323
Short name T772
Test name
Test status
Simulation time 69144881 ps
CPU time 3.61 seconds
Started Jul 18 06:45:07 PM PDT 24
Finished Jul 18 06:45:16 PM PDT 24
Peak memory 237680 kb
Host smart-fd909526-a889-4171-aa41-1dac4611504e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2637939323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2637939323
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3689395261
Short name T718
Test name
Test status
Simulation time 102549945 ps
CPU time 11.84 seconds
Started Jul 18 06:45:07 PM PDT 24
Finished Jul 18 06:45:24 PM PDT 24
Peak memory 240652 kb
Host smart-d6e1a1d1-ef3b-4655-bff8-8282eaadabc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3689395261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3689395261
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3832871962
Short name T157
Test name
Test status
Simulation time 3680134504 ps
CPU time 140.29 seconds
Started Jul 18 06:44:58 PM PDT 24
Finished Jul 18 06:47:26 PM PDT 24
Peak memory 265620 kb
Host smart-6194de83-b40a-4ad7-92cf-be84e909af56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3832871962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3832871962
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.756476362
Short name T173
Test name
Test status
Simulation time 2359836506 ps
CPU time 336.97 seconds
Started Jul 18 06:45:01 PM PDT 24
Finished Jul 18 06:50:44 PM PDT 24
Peak memory 265548 kb
Host smart-991d66dc-571f-4193-b06c-e202811c9938
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756476362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.756476362
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1881505388
Short name T723
Test name
Test status
Simulation time 57400093 ps
CPU time 5.11 seconds
Started Jul 18 06:45:01 PM PDT 24
Finished Jul 18 06:45:12 PM PDT 24
Peak memory 247780 kb
Host smart-2485da77-a56d-4755-a2a1-b7ff735975c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1881505388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1881505388
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.290511624
Short name T367
Test name
Test status
Simulation time 60117153 ps
CPU time 8.98 seconds
Started Jul 18 06:45:11 PM PDT 24
Finished Jul 18 06:45:26 PM PDT 24
Peak memory 252032 kb
Host smart-bfe4b366-3175-408b-b2f8-7c31aba56366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290511624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.290511624
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3653879431
Short name T733
Test name
Test status
Simulation time 730844735 ps
CPU time 7.59 seconds
Started Jul 18 06:45:07 PM PDT 24
Finished Jul 18 06:45:20 PM PDT 24
Peak memory 237772 kb
Host smart-7779968a-9ecd-4b89-9291-984b0b2b1fe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3653879431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3653879431
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2732834576
Short name T752
Test name
Test status
Simulation time 625062161 ps
CPU time 40.56 seconds
Started Jul 18 06:45:17 PM PDT 24
Finished Jul 18 06:46:02 PM PDT 24
Peak memory 248912 kb
Host smart-871397b3-74fd-478f-a19e-b38105bf1e3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2732834576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2732834576
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1598705288
Short name T161
Test name
Test status
Simulation time 48677652195 ps
CPU time 1028.95 seconds
Started Jul 18 06:45:10 PM PDT 24
Finished Jul 18 07:02:25 PM PDT 24
Peak memory 265712 kb
Host smart-c7e040f7-e125-44c9-a668-f3a090300300
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598705288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1598705288
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4290020316
Short name T763
Test name
Test status
Simulation time 357298803 ps
CPU time 14.31 seconds
Started Jul 18 06:45:12 PM PDT 24
Finished Jul 18 06:45:31 PM PDT 24
Peak memory 253828 kb
Host smart-f961ceed-d69e-4870-b1a3-fb9843a9c342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4290020316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4290020316
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1147655009
Short name T738
Test name
Test status
Simulation time 1990107677 ps
CPU time 76.92 seconds
Started Jul 18 06:44:38 PM PDT 24
Finished Jul 18 06:46:06 PM PDT 24
Peak memory 237756 kb
Host smart-b07794a4-8647-4692-8b14-179b3bfa6599
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1147655009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1147655009
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3174599925
Short name T224
Test name
Test status
Simulation time 1671467003 ps
CPU time 113.83 seconds
Started Jul 18 06:44:36 PM PDT 24
Finished Jul 18 06:46:41 PM PDT 24
Peak memory 237780 kb
Host smart-54fd43f5-fa50-4955-90bd-63dae5de452a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3174599925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3174599925
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2236045635
Short name T827
Test name
Test status
Simulation time 139613267 ps
CPU time 5.02 seconds
Started Jul 18 06:44:38 PM PDT 24
Finished Jul 18 06:44:54 PM PDT 24
Peak memory 249064 kb
Host smart-989ea258-9839-43ae-a159-38db9c7c4666
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2236045635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2236045635
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3146014875
Short name T784
Test name
Test status
Simulation time 137854662 ps
CPU time 6.78 seconds
Started Jul 18 06:44:39 PM PDT 24
Finished Jul 18 06:44:57 PM PDT 24
Peak memory 240784 kb
Host smart-b97ae4a6-b6ca-4c5a-b84e-9278424a5e56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146014875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3146014875
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1024694731
Short name T370
Test name
Test status
Simulation time 282282743 ps
CPU time 4.37 seconds
Started Jul 18 06:44:36 PM PDT 24
Finished Jul 18 06:44:51 PM PDT 24
Peak memory 237748 kb
Host smart-10a1fc7e-75e6-4c2c-9b08-e0be07c1544d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1024694731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1024694731
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2308280525
Short name T790
Test name
Test status
Simulation time 8233876 ps
CPU time 1.54 seconds
Started Jul 18 06:44:38 PM PDT 24
Finished Jul 18 06:44:51 PM PDT 24
Peak memory 237780 kb
Host smart-9c70b996-d388-495b-9966-ddfba92eeb39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2308280525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2308280525
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3284368958
Short name T725
Test name
Test status
Simulation time 948860229 ps
CPU time 21.17 seconds
Started Jul 18 06:44:39 PM PDT 24
Finished Jul 18 06:45:11 PM PDT 24
Peak memory 245000 kb
Host smart-1241eea4-5ba4-4cb8-8945-45535a95dcc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3284368958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3284368958
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2581055369
Short name T169
Test name
Test status
Simulation time 2048099757 ps
CPU time 148.99 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:47:21 PM PDT 24
Peak memory 265540 kb
Host smart-c7ed3e03-23cd-4828-9845-4120ee062c81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2581055369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2581055369
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1896940733
Short name T182
Test name
Test status
Simulation time 8737359708 ps
CPU time 602.54 seconds
Started Jul 18 06:44:40 PM PDT 24
Finished Jul 18 06:54:53 PM PDT 24
Peak memory 273828 kb
Host smart-23569e38-fb93-4774-8a8e-ed408cc292bc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896940733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1896940733
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3624030535
Short name T703
Test name
Test status
Simulation time 1017269231 ps
CPU time 8.08 seconds
Started Jul 18 06:44:40 PM PDT 24
Finished Jul 18 06:44:59 PM PDT 24
Peak memory 253560 kb
Host smart-be283a75-e666-4997-adfc-7f615c42ee28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3624030535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3624030535
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3515949681
Short name T228
Test name
Test status
Simulation time 180301412 ps
CPU time 2.41 seconds
Started Jul 18 06:44:36 PM PDT 24
Finished Jul 18 06:44:49 PM PDT 24
Peak memory 237664 kb
Host smart-2860e7f5-c9fe-4cb2-ad0d-e15703bc4924
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3515949681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3515949681
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2150509031
Short name T190
Test name
Test status
Simulation time 10549185 ps
CPU time 1.4 seconds
Started Jul 18 06:45:07 PM PDT 24
Finished Jul 18 06:45:13 PM PDT 24
Peak memory 236840 kb
Host smart-023f5b43-f128-4802-bd6b-5e46856169fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2150509031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2150509031
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1871552202
Short name T768
Test name
Test status
Simulation time 11900268 ps
CPU time 1.43 seconds
Started Jul 18 06:45:07 PM PDT 24
Finished Jul 18 06:45:14 PM PDT 24
Peak memory 237756 kb
Host smart-49206714-42d8-40c8-8929-543b1fd87097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1871552202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1871552202
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.430787322
Short name T789
Test name
Test status
Simulation time 12075916 ps
CPU time 1.32 seconds
Started Jul 18 06:45:04 PM PDT 24
Finished Jul 18 06:45:11 PM PDT 24
Peak memory 235776 kb
Host smart-8fc94bbe-e2e5-4fb7-ae08-7d7d9ee180fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=430787322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.430787322
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.3939724846
Short name T365
Test name
Test status
Simulation time 10965950 ps
CPU time 1.3 seconds
Started Jul 18 06:45:07 PM PDT 24
Finished Jul 18 06:45:13 PM PDT 24
Peak memory 237764 kb
Host smart-81a5f047-4e1c-48af-b529-dbefa042683e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3939724846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.3939724846
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.4088062480
Short name T707
Test name
Test status
Simulation time 8721460 ps
CPU time 1.46 seconds
Started Jul 18 06:45:15 PM PDT 24
Finished Jul 18 06:45:21 PM PDT 24
Peak memory 237788 kb
Host smart-ae8bed47-5f25-4f39-b1b5-1d8f8eb8f06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4088062480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.4088062480
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.984700499
Short name T770
Test name
Test status
Simulation time 16399835 ps
CPU time 1.33 seconds
Started Jul 18 06:45:05 PM PDT 24
Finished Jul 18 06:45:11 PM PDT 24
Peak memory 236836 kb
Host smart-85ea0ada-b33c-476b-b938-e11ec0840ff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=984700499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.984700499
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2832780
Short name T780
Test name
Test status
Simulation time 13834252 ps
CPU time 1.41 seconds
Started Jul 18 06:45:19 PM PDT 24
Finished Jul 18 06:45:24 PM PDT 24
Peak memory 237788 kb
Host smart-b188d4d2-1c8a-42a6-b4cc-540fe05e2cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2832780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2832780
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.4125010231
Short name T192
Test name
Test status
Simulation time 64323720 ps
CPU time 1.47 seconds
Started Jul 18 06:45:10 PM PDT 24
Finished Jul 18 06:45:17 PM PDT 24
Peak memory 236792 kb
Host smart-18576284-2360-4e3d-a95e-9a74016b7add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4125010231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.4125010231
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.4234220659
Short name T762
Test name
Test status
Simulation time 13316161 ps
CPU time 1.45 seconds
Started Jul 18 06:45:11 PM PDT 24
Finished Jul 18 06:45:18 PM PDT 24
Peak memory 235800 kb
Host smart-c4541d31-b651-4106-a49c-65093e4d2369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4234220659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.4234220659
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.445038333
Short name T710
Test name
Test status
Simulation time 21372115 ps
CPU time 1.29 seconds
Started Jul 18 06:45:07 PM PDT 24
Finished Jul 18 06:45:13 PM PDT 24
Peak memory 237768 kb
Host smart-6785d6d3-1476-47ca-90a8-7d7a490a51e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=445038333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.445038333
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2104644455
Short name T750
Test name
Test status
Simulation time 4814769138 ps
CPU time 137.69 seconds
Started Jul 18 06:44:37 PM PDT 24
Finished Jul 18 06:47:06 PM PDT 24
Peak memory 237816 kb
Host smart-6a6b843a-e513-416a-ba6d-cd05b7afb3df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2104644455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2104644455
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1175641094
Short name T817
Test name
Test status
Simulation time 1670592965 ps
CPU time 181.97 seconds
Started Jul 18 06:44:38 PM PDT 24
Finished Jul 18 06:47:51 PM PDT 24
Peak memory 236820 kb
Host smart-975baa58-b1c9-49db-b79a-e360146bf9ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1175641094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1175641094
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1658731153
Short name T810
Test name
Test status
Simulation time 38865743 ps
CPU time 3.44 seconds
Started Jul 18 06:44:34 PM PDT 24
Finished Jul 18 06:44:48 PM PDT 24
Peak memory 240688 kb
Host smart-3ed6e35a-33b0-4c84-b39e-3ba9204c2c6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1658731153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1658731153
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2517438681
Short name T727
Test name
Test status
Simulation time 130980494 ps
CPU time 8.84 seconds
Started Jul 18 06:44:40 PM PDT 24
Finished Jul 18 06:45:00 PM PDT 24
Peak memory 249036 kb
Host smart-1901419e-c086-461d-acd8-2115168ad5a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517438681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2517438681
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3704895010
Short name T222
Test name
Test status
Simulation time 112333877 ps
CPU time 5.09 seconds
Started Jul 18 06:44:40 PM PDT 24
Finished Jul 18 06:44:57 PM PDT 24
Peak memory 237772 kb
Host smart-f02dfa7c-f203-40ba-bae8-8a782db53e0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3704895010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3704895010
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3182317129
Short name T717
Test name
Test status
Simulation time 142231298 ps
CPU time 12.11 seconds
Started Jul 18 06:44:38 PM PDT 24
Finished Jul 18 06:45:01 PM PDT 24
Peak memory 245020 kb
Host smart-0acd810c-de06-457c-962b-4118f7e67a52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3182317129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3182317129
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2123302219
Short name T170
Test name
Test status
Simulation time 14997489334 ps
CPU time 334.02 seconds
Started Jul 18 06:44:37 PM PDT 24
Finished Jul 18 06:50:22 PM PDT 24
Peak memory 270968 kb
Host smart-29ea609a-efbb-4a11-9a8f-c575deb07fa4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123302219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2123302219
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4151810981
Short name T779
Test name
Test status
Simulation time 138518514 ps
CPU time 9.26 seconds
Started Jul 18 06:44:35 PM PDT 24
Finished Jul 18 06:44:55 PM PDT 24
Peak memory 248884 kb
Host smart-cb57e8a2-d829-44ad-9af3-1208c71b5a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4151810981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.4151810981
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2647494453
Short name T736
Test name
Test status
Simulation time 104992984 ps
CPU time 2.75 seconds
Started Jul 18 06:44:39 PM PDT 24
Finished Jul 18 06:44:53 PM PDT 24
Peak memory 237644 kb
Host smart-35fbb927-baf5-4021-a785-d71bcca58599
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2647494453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2647494453
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.106696472
Short name T808
Test name
Test status
Simulation time 13214909 ps
CPU time 1.39 seconds
Started Jul 18 06:45:10 PM PDT 24
Finished Jul 18 06:45:17 PM PDT 24
Peak memory 237780 kb
Host smart-3ea8f8d8-705d-4e55-bddc-18936e93259c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=106696472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.106696472
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1062633257
Short name T758
Test name
Test status
Simulation time 14509159 ps
CPU time 1.39 seconds
Started Jul 18 06:45:04 PM PDT 24
Finished Jul 18 06:45:11 PM PDT 24
Peak memory 235784 kb
Host smart-3062b1a3-88f3-420b-80b9-59199a344b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1062633257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1062633257
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1841777855
Short name T786
Test name
Test status
Simulation time 25293082 ps
CPU time 1.45 seconds
Started Jul 18 06:45:09 PM PDT 24
Finished Jul 18 06:45:16 PM PDT 24
Peak memory 236852 kb
Host smart-48e1f8ee-87fa-4769-9cb2-1cbd9bf62aae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1841777855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1841777855
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1245239892
Short name T742
Test name
Test status
Simulation time 32981961 ps
CPU time 1.3 seconds
Started Jul 18 06:45:10 PM PDT 24
Finished Jul 18 06:45:17 PM PDT 24
Peak memory 236688 kb
Host smart-f8da3a3b-7698-4a6e-9a5b-59e834253f2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1245239892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1245239892
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3859310092
Short name T809
Test name
Test status
Simulation time 29672392 ps
CPU time 1.44 seconds
Started Jul 18 06:45:09 PM PDT 24
Finished Jul 18 06:45:16 PM PDT 24
Peak memory 236824 kb
Host smart-188a9240-bb4e-4e09-b73a-d7e1bc08f012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3859310092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3859310092
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2979206988
Short name T732
Test name
Test status
Simulation time 12432814 ps
CPU time 1.61 seconds
Started Jul 18 06:45:17 PM PDT 24
Finished Jul 18 06:45:23 PM PDT 24
Peak memory 236836 kb
Host smart-735495ca-99cc-475c-9c8a-d37fb535fa3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2979206988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2979206988
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3399270903
Short name T820
Test name
Test status
Simulation time 7337694 ps
CPU time 1.34 seconds
Started Jul 18 06:45:09 PM PDT 24
Finished Jul 18 06:45:16 PM PDT 24
Peak memory 237764 kb
Host smart-8695d986-cfc6-4316-bb25-473aff6cb418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3399270903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3399270903
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2185324301
Short name T256
Test name
Test status
Simulation time 11414390 ps
CPU time 1.32 seconds
Started Jul 18 06:45:10 PM PDT 24
Finished Jul 18 06:45:17 PM PDT 24
Peak memory 236836 kb
Host smart-38831ab0-123d-43c7-b62e-70601736ae32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2185324301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2185324301
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1774299967
Short name T714
Test name
Test status
Simulation time 16822232 ps
CPU time 1.33 seconds
Started Jul 18 06:45:07 PM PDT 24
Finished Jul 18 06:45:13 PM PDT 24
Peak memory 235796 kb
Host smart-a82485e9-6871-4e2d-a5c5-ec194a94d207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1774299967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1774299967
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.182112435
Short name T751
Test name
Test status
Simulation time 25953805 ps
CPU time 1.47 seconds
Started Jul 18 06:45:08 PM PDT 24
Finished Jul 18 06:45:14 PM PDT 24
Peak memory 237776 kb
Host smart-2ab96190-145b-4ceb-999a-a3a0af9a06a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=182112435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.182112435
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2114973350
Short name T776
Test name
Test status
Simulation time 18796981064 ps
CPU time 333.75 seconds
Started Jul 18 06:44:37 PM PDT 24
Finished Jul 18 06:50:22 PM PDT 24
Peak memory 241040 kb
Host smart-ba124033-a71c-4ab0-886d-bc377c3ad45f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2114973350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2114973350
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.501030771
Short name T822
Test name
Test status
Simulation time 6532127685 ps
CPU time 230.04 seconds
Started Jul 18 06:44:28 PM PDT 24
Finished Jul 18 06:48:28 PM PDT 24
Peak memory 240780 kb
Host smart-1698ae4a-b5af-4839-8b3f-8af33885d32b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=501030771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.501030771
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1318024652
Short name T225
Test name
Test status
Simulation time 39209989 ps
CPU time 5.91 seconds
Started Jul 18 06:44:40 PM PDT 24
Finished Jul 18 06:44:56 PM PDT 24
Peak memory 240776 kb
Host smart-620310f5-5cbe-4562-af65-37d49dda6765
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1318024652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1318024652
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2239840976
Short name T728
Test name
Test status
Simulation time 149254266 ps
CPU time 11.55 seconds
Started Jul 18 06:44:37 PM PDT 24
Finished Jul 18 06:45:00 PM PDT 24
Peak memory 251936 kb
Host smart-edbe574b-7edf-43d3-9895-7b3496c0ea4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239840976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2239840976
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1404727775
Short name T709
Test name
Test status
Simulation time 228917460 ps
CPU time 8.61 seconds
Started Jul 18 06:44:40 PM PDT 24
Finished Jul 18 06:44:59 PM PDT 24
Peak memory 236764 kb
Host smart-dac5e6c2-d574-457a-b506-392483150175
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1404727775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1404727775
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3987476560
Short name T746
Test name
Test status
Simulation time 39573581 ps
CPU time 1.28 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:44:53 PM PDT 24
Peak memory 236832 kb
Host smart-e6046101-00d2-4ed9-aba8-e6a453d171cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3987476560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3987476560
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3074853939
Short name T712
Test name
Test status
Simulation time 269302802 ps
CPU time 18.46 seconds
Started Jul 18 06:44:39 PM PDT 24
Finished Jul 18 06:45:09 PM PDT 24
Peak memory 245016 kb
Host smart-7b30c9f6-6c46-4fa7-9d3d-a69e1872717a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3074853939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3074853939
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3564815455
Short name T264
Test name
Test status
Simulation time 1202406377 ps
CPU time 20.16 seconds
Started Jul 18 06:44:37 PM PDT 24
Finished Jul 18 06:45:08 PM PDT 24
Peak memory 248904 kb
Host smart-a09ebddd-9159-4462-93ba-4f9e86a596aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3564815455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3564815455
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.892488088
Short name T737
Test name
Test status
Simulation time 10925620 ps
CPU time 1.34 seconds
Started Jul 18 06:45:06 PM PDT 24
Finished Jul 18 06:45:12 PM PDT 24
Peak memory 236828 kb
Host smart-210ad11d-3bd0-451a-83ef-20125bff9b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=892488088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.892488088
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.888518332
Short name T756
Test name
Test status
Simulation time 28927243 ps
CPU time 1.46 seconds
Started Jul 18 06:45:08 PM PDT 24
Finished Jul 18 06:45:15 PM PDT 24
Peak memory 236844 kb
Host smart-16f42802-5d5f-451a-8ece-0623652dba83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=888518332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.888518332
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.308753170
Short name T704
Test name
Test status
Simulation time 25716168 ps
CPU time 1.53 seconds
Started Jul 18 06:45:09 PM PDT 24
Finished Jul 18 06:45:16 PM PDT 24
Peak memory 237772 kb
Host smart-1887aea2-f297-4607-9f74-68eb0370ec93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=308753170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.308753170
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.4008119557
Short name T774
Test name
Test status
Simulation time 20700184 ps
CPU time 1.35 seconds
Started Jul 18 06:45:16 PM PDT 24
Finished Jul 18 06:45:21 PM PDT 24
Peak memory 236924 kb
Host smart-7e215cbd-37cc-41a8-9691-8fa1976f73fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4008119557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.4008119557
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2651393780
Short name T741
Test name
Test status
Simulation time 11914328 ps
CPU time 1.7 seconds
Started Jul 18 06:45:12 PM PDT 24
Finished Jul 18 06:45:19 PM PDT 24
Peak memory 236836 kb
Host smart-e6a0ae93-d424-4054-9296-ea87d4bb0f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2651393780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2651393780
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.194141115
Short name T708
Test name
Test status
Simulation time 12978302 ps
CPU time 1.67 seconds
Started Jul 18 06:45:17 PM PDT 24
Finished Jul 18 06:45:23 PM PDT 24
Peak memory 237780 kb
Host smart-3c7bb49d-9dfb-46b9-8d51-4e351858d791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=194141115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.194141115
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3075776200
Short name T783
Test name
Test status
Simulation time 35139052 ps
CPU time 2.61 seconds
Started Jul 18 06:45:06 PM PDT 24
Finished Jul 18 06:45:14 PM PDT 24
Peak memory 237768 kb
Host smart-499cd92b-fbe0-44d0-98ec-fa6a8f9b9f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3075776200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3075776200
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.358472376
Short name T777
Test name
Test status
Simulation time 16119684 ps
CPU time 1.26 seconds
Started Jul 18 06:45:08 PM PDT 24
Finished Jul 18 06:45:14 PM PDT 24
Peak memory 236836 kb
Host smart-e1ffa3fd-1b65-489f-ade0-04563802c212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=358472376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.358472376
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2480572134
Short name T771
Test name
Test status
Simulation time 10624732 ps
CPU time 1.44 seconds
Started Jul 18 06:45:06 PM PDT 24
Finished Jul 18 06:45:12 PM PDT 24
Peak memory 235996 kb
Host smart-e32e2e60-9d51-47cb-80b3-2b58ad7674b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2480572134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2480572134
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1872078895
Short name T818
Test name
Test status
Simulation time 13450154 ps
CPU time 1.32 seconds
Started Jul 18 06:45:07 PM PDT 24
Finished Jul 18 06:45:14 PM PDT 24
Peak memory 236716 kb
Host smart-25d22695-88d2-44e8-b6ef-eb10bd1d4d29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1872078895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1872078895
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1357081392
Short name T731
Test name
Test status
Simulation time 31382642 ps
CPU time 5.25 seconds
Started Jul 18 06:44:40 PM PDT 24
Finished Jul 18 06:44:57 PM PDT 24
Peak memory 240788 kb
Host smart-f194c020-301d-48d9-bb0b-2673d14e74a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357081392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1357081392
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2041486027
Short name T262
Test name
Test status
Simulation time 975930412 ps
CPU time 8.63 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:45:02 PM PDT 24
Peak memory 237736 kb
Host smart-c32e1ba1-2c0b-48c4-9a3f-4e9a89cc3d6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2041486027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2041486027
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1230509125
Short name T812
Test name
Test status
Simulation time 18262407 ps
CPU time 1.38 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:44:55 PM PDT 24
Peak memory 236836 kb
Host smart-b6caaf9a-b852-4df7-be5f-1921481e391e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1230509125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1230509125
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.176393750
Short name T787
Test name
Test status
Simulation time 115790769 ps
CPU time 11.79 seconds
Started Jul 18 06:44:42 PM PDT 24
Finished Jul 18 06:45:05 PM PDT 24
Peak memory 245200 kb
Host smart-5d5ca310-7a66-463d-ad76-4c3ee3e95839
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=176393750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.176393750
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3570104612
Short name T159
Test name
Test status
Simulation time 18133352694 ps
CPU time 606.29 seconds
Started Jul 18 06:44:34 PM PDT 24
Finished Jul 18 06:54:51 PM PDT 24
Peak memory 265540 kb
Host smart-94c9cbc2-0a54-4f6f-8121-2c12b75c2c0e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570104612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3570104612
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2777512799
Short name T726
Test name
Test status
Simulation time 385490668 ps
CPU time 12.51 seconds
Started Jul 18 06:44:39 PM PDT 24
Finished Jul 18 06:45:03 PM PDT 24
Peak memory 248400 kb
Host smart-eda4704f-0fc8-4eaf-b9a5-bb48c13b7706
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2777512799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2777512799
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1547117554
Short name T730
Test name
Test status
Simulation time 103771344 ps
CPU time 9.59 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:45:03 PM PDT 24
Peak memory 240268 kb
Host smart-dce7d895-e1b4-49f3-b5e6-68fda3d7b959
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547117554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1547117554
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.231713396
Short name T804
Test name
Test status
Simulation time 130702603 ps
CPU time 10.15 seconds
Started Jul 18 06:44:42 PM PDT 24
Finished Jul 18 06:45:03 PM PDT 24
Peak memory 237936 kb
Host smart-c808ceda-4a2c-49f8-a67c-29cf209d7398
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=231713396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.231713396
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.231147136
Short name T782
Test name
Test status
Simulation time 7594301 ps
CPU time 1.41 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:44:53 PM PDT 24
Peak memory 237744 kb
Host smart-afd42241-197d-49d4-9701-20a039fe0fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=231147136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.231147136
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2197879721
Short name T722
Test name
Test status
Simulation time 96359879 ps
CPU time 12.49 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:45:04 PM PDT 24
Peak memory 245944 kb
Host smart-1a5311aa-f93a-42fc-a842-4c47b1260ed4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2197879721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2197879721
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3554620891
Short name T753
Test name
Test status
Simulation time 2455734062 ps
CPU time 10.85 seconds
Started Jul 18 06:44:40 PM PDT 24
Finished Jul 18 06:45:02 PM PDT 24
Peak memory 248664 kb
Host smart-bd99697b-bae6-49ad-ac66-e97b0ca874cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3554620891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3554620891
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3178949577
Short name T207
Test name
Test status
Simulation time 41353438 ps
CPU time 3.64 seconds
Started Jul 18 06:44:42 PM PDT 24
Finished Jul 18 06:44:56 PM PDT 24
Peak memory 237944 kb
Host smart-4c7adf07-991a-4ce6-97e3-47cdf88b6e56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3178949577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3178949577
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.924920477
Short name T740
Test name
Test status
Simulation time 54964678 ps
CPU time 4.81 seconds
Started Jul 18 06:44:42 PM PDT 24
Finished Jul 18 06:44:57 PM PDT 24
Peak memory 240728 kb
Host smart-3820298b-4741-431e-ac06-6efcec47da6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924920477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.924920477
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2052515128
Short name T824
Test name
Test status
Simulation time 49166351 ps
CPU time 4.67 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:44:57 PM PDT 24
Peak memory 237724 kb
Host smart-4d78d8b3-63dd-4d3e-921f-74e18c6764b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2052515128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2052515128
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.531297784
Short name T745
Test name
Test status
Simulation time 17582608 ps
CPU time 1.31 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:44:54 PM PDT 24
Peak memory 235800 kb
Host smart-1951e56c-ac5c-41a2-a406-215b218282fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=531297784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.531297784
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2421712035
Short name T205
Test name
Test status
Simulation time 3251481590 ps
CPU time 33.49 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:45:27 PM PDT 24
Peak memory 245064 kb
Host smart-7e6311f5-db54-46bb-bfd2-6a28086ed85b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2421712035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2421712035
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1430427361
Short name T164
Test name
Test status
Simulation time 2928669418 ps
CPU time 174.36 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:47:48 PM PDT 24
Peak memory 268092 kb
Host smart-084805e4-66e8-47c1-9d16-3b17e167cb0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1430427361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1430427361
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.107222700
Short name T185
Test name
Test status
Simulation time 9122555508 ps
CPU time 317.5 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:50:11 PM PDT 24
Peak memory 265544 kb
Host smart-6badb1ef-e75a-4bfb-85a9-b6623e079131
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107222700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.107222700
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2768388756
Short name T759
Test name
Test status
Simulation time 310659968 ps
CPU time 19.24 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:45:11 PM PDT 24
Peak memory 248956 kb
Host smart-d6f9e71a-43bb-4e8d-bbe1-363d3155649b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2768388756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2768388756
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1927278104
Short name T821
Test name
Test status
Simulation time 127070790 ps
CPU time 9.36 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:45:03 PM PDT 24
Peak memory 253936 kb
Host smart-891fa27d-84f9-4a41-8885-884bf6c4dfb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927278104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1927278104
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.4112091145
Short name T764
Test name
Test status
Simulation time 106632722 ps
CPU time 4.47 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:44:58 PM PDT 24
Peak memory 237624 kb
Host smart-43a1b6e0-4f4f-47ca-9602-f76c29ada6b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4112091145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.4112091145
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2074402548
Short name T749
Test name
Test status
Simulation time 18865463 ps
CPU time 1.46 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:44:54 PM PDT 24
Peak memory 236844 kb
Host smart-d3fa5be4-add9-4eb8-8eeb-624c7631645d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2074402548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2074402548
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2868003314
Short name T761
Test name
Test status
Simulation time 320719664 ps
CPU time 18.45 seconds
Started Jul 18 06:44:37 PM PDT 24
Finished Jul 18 06:45:06 PM PDT 24
Peak memory 245012 kb
Host smart-fb5b6364-8dc3-4d7a-b6f5-340dd29deb1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2868003314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2868003314
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.4028211213
Short name T175
Test name
Test status
Simulation time 46370077981 ps
CPU time 855.21 seconds
Started Jul 18 06:44:42 PM PDT 24
Finished Jul 18 06:59:07 PM PDT 24
Peak memory 265572 kb
Host smart-ae80ce8f-924b-4d4e-9eb2-0bfcadde7377
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028211213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.4028211213
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2153436127
Short name T795
Test name
Test status
Simulation time 955650002 ps
CPU time 9.25 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:45:01 PM PDT 24
Peak memory 248960 kb
Host smart-e16fa88e-ec4c-4a18-a161-197a42521f83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2153436127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2153436127
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.636944932
Short name T767
Test name
Test status
Simulation time 409868456 ps
CPU time 10.92 seconds
Started Jul 18 06:44:51 PM PDT 24
Finished Jul 18 06:45:10 PM PDT 24
Peak memory 255276 kb
Host smart-a81571e2-87fa-4646-adee-00d48d628d5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636944932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.636944932
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3006839796
Short name T734
Test name
Test status
Simulation time 34718516 ps
CPU time 5.36 seconds
Started Jul 18 06:44:42 PM PDT 24
Finished Jul 18 06:44:58 PM PDT 24
Peak memory 237748 kb
Host smart-296146c5-e875-47bf-a66d-828ec2111427
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3006839796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3006839796
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.127625193
Short name T711
Test name
Test status
Simulation time 7432686 ps
CPU time 1.46 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:44:53 PM PDT 24
Peak memory 237768 kb
Host smart-e7ccc06d-0a4f-4626-9e99-dfa607dc39a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=127625193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.127625193
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1147558793
Short name T769
Test name
Test status
Simulation time 3605665721 ps
CPU time 40.07 seconds
Started Jul 18 06:44:53 PM PDT 24
Finished Jul 18 06:45:41 PM PDT 24
Peak memory 246028 kb
Host smart-8e48dfde-615d-48e5-9711-510c335ce8fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1147558793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1147558793
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3634616156
Short name T183
Test name
Test status
Simulation time 3950781270 ps
CPU time 136.04 seconds
Started Jul 18 06:44:42 PM PDT 24
Finished Jul 18 06:47:09 PM PDT 24
Peak memory 265596 kb
Host smart-a8604b55-8be3-42a4-b2f6-6b9c0a14c80c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3634616156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3634616156
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2389423361
Short name T168
Test name
Test status
Simulation time 8793704294 ps
CPU time 535.19 seconds
Started Jul 18 06:44:41 PM PDT 24
Finished Jul 18 06:53:47 PM PDT 24
Peak memory 265552 kb
Host smart-d9548a3c-ee49-49cf-b7be-244ac34ffea5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389423361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2389423361
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2521238432
Short name T747
Test name
Test status
Simulation time 176797958 ps
CPU time 14.82 seconds
Started Jul 18 06:44:42 PM PDT 24
Finished Jul 18 06:45:07 PM PDT 24
Peak memory 248632 kb
Host smart-fc349c2e-f9da-459f-881e-48a29484cf6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2521238432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2521238432
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4175655332
Short name T195
Test name
Test status
Simulation time 293635392 ps
CPU time 2.98 seconds
Started Jul 18 06:44:43 PM PDT 24
Finished Jul 18 06:44:57 PM PDT 24
Peak memory 237752 kb
Host smart-1818934f-9f29-4be0-8e4c-3c70cda2115d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4175655332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4175655332
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2991592200
Short name T570
Test name
Test status
Simulation time 90476477772 ps
CPU time 2472.41 seconds
Started Jul 18 04:48:47 PM PDT 24
Finished Jul 18 05:30:02 PM PDT 24
Peak memory 288640 kb
Host smart-fbeaa013-518f-4592-87eb-6969245c1a91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991592200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2991592200
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1566658311
Short name T490
Test name
Test status
Simulation time 1601424254 ps
CPU time 34.56 seconds
Started Jul 18 04:48:50 PM PDT 24
Finished Jul 18 04:49:26 PM PDT 24
Peak memory 248948 kb
Host smart-a109c0ba-74e4-44e2-ad09-944286dadf22
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1566658311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1566658311
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.316745533
Short name T507
Test name
Test status
Simulation time 572286263 ps
CPU time 23.32 seconds
Started Jul 18 04:48:45 PM PDT 24
Finished Jul 18 04:49:10 PM PDT 24
Peak memory 249480 kb
Host smart-700ad918-b70b-459c-b7e1-b2cdf2b7ed6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31674
5533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.316745533
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3089003540
Short name T486
Test name
Test status
Simulation time 105821050551 ps
CPU time 1917.28 seconds
Started Jul 18 04:48:48 PM PDT 24
Finished Jul 18 05:20:48 PM PDT 24
Peak memory 285312 kb
Host smart-15ccca96-eb61-4d76-84e5-cd4908ec1c18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089003540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3089003540
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2966373762
Short name T557
Test name
Test status
Simulation time 16748689708 ps
CPU time 372.51 seconds
Started Jul 18 04:48:44 PM PDT 24
Finished Jul 18 04:54:58 PM PDT 24
Peak memory 249088 kb
Host smart-cab32155-13bd-4b4d-8228-e20b6f90aee2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966373762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2966373762
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3185017014
Short name T68
Test name
Test status
Simulation time 292766296 ps
CPU time 27.89 seconds
Started Jul 18 04:48:45 PM PDT 24
Finished Jul 18 04:49:14 PM PDT 24
Peak memory 256304 kb
Host smart-446661c0-aa37-484c-99d4-b2dcbdc620fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31850
17014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3185017014
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3857784343
Short name T140
Test name
Test status
Simulation time 948978924 ps
CPU time 49.63 seconds
Started Jul 18 04:48:45 PM PDT 24
Finished Jul 18 04:49:36 PM PDT 24
Peak memory 256576 kb
Host smart-f40a892f-1804-4f85-931a-d682e7d9347c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38577
84343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3857784343
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.395981947
Short name T11
Test name
Test status
Simulation time 1209443582 ps
CPU time 12.05 seconds
Started Jul 18 04:48:48 PM PDT 24
Finished Jul 18 04:49:02 PM PDT 24
Peak memory 270456 kb
Host smart-b9405b1f-1732-4f92-b932-601bcb2c687d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=395981947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.395981947
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3017232396
Short name T588
Test name
Test status
Simulation time 1500199394 ps
CPU time 25.06 seconds
Started Jul 18 04:48:44 PM PDT 24
Finished Jul 18 04:49:11 PM PDT 24
Peak memory 257016 kb
Host smart-ea5e4c4b-b9ee-4b0b-aec0-39b3fbe7d886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30172
32396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3017232396
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3509294097
Short name T627
Test name
Test status
Simulation time 30307458685 ps
CPU time 1977.24 seconds
Started Jul 18 04:48:49 PM PDT 24
Finished Jul 18 05:21:48 PM PDT 24
Peak memory 302276 kb
Host smart-6bdf7853-1171-4b29-96c1-40b44bc6ff7e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509294097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3509294097
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2837811766
Short name T694
Test name
Test status
Simulation time 36415116244 ps
CPU time 2018.25 seconds
Started Jul 18 04:48:47 PM PDT 24
Finished Jul 18 05:22:28 PM PDT 24
Peak memory 290000 kb
Host smart-be0ef3d6-be27-457c-ad7f-689dbdbf6f53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837811766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2837811766
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1032122378
Short name T623
Test name
Test status
Simulation time 388827779 ps
CPU time 18.32 seconds
Started Jul 18 04:48:44 PM PDT 24
Finished Jul 18 04:49:04 PM PDT 24
Peak memory 248868 kb
Host smart-21e8f321-a845-49a2-8a4a-333dd5334c6a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1032122378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1032122378
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.751344
Short name T496
Test name
Test status
Simulation time 2030232041 ps
CPU time 82.37 seconds
Started Jul 18 04:48:46 PM PDT 24
Finished Jul 18 04:50:11 PM PDT 24
Peak memory 256632 kb
Host smart-35bcc1b8-fed2-42ea-a7e2-436d2476ca99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75134
4 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.751344
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2402540560
Short name T633
Test name
Test status
Simulation time 201389216 ps
CPU time 18.19 seconds
Started Jul 18 04:48:47 PM PDT 24
Finished Jul 18 04:49:08 PM PDT 24
Peak memory 248908 kb
Host smart-7cdb5e5c-5887-472b-8017-bcfa9e85f4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24025
40560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2402540560
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1470005716
Short name T645
Test name
Test status
Simulation time 19619207371 ps
CPU time 1501.5 seconds
Started Jul 18 04:48:51 PM PDT 24
Finished Jul 18 05:13:55 PM PDT 24
Peak memory 288984 kb
Host smart-2d52cabc-79f7-4f58-b5d7-3b3e809ca6f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470005716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1470005716
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3797588420
Short name T537
Test name
Test status
Simulation time 148053491647 ps
CPU time 2092.28 seconds
Started Jul 18 04:48:48 PM PDT 24
Finished Jul 18 05:23:43 PM PDT 24
Peak memory 282896 kb
Host smart-8d98e5d7-f262-4a65-9720-55c29df89a98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797588420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3797588420
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.33931036
Short name T251
Test name
Test status
Simulation time 1521422784 ps
CPU time 25.97 seconds
Started Jul 18 04:48:47 PM PDT 24
Finished Jul 18 04:49:15 PM PDT 24
Peak memory 256164 kb
Host smart-f1c6d407-738c-4f40-9e00-1557a122264f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33931
036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.33931036
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1186784451
Short name T392
Test name
Test status
Simulation time 178608599 ps
CPU time 20.07 seconds
Started Jul 18 04:48:51 PM PDT 24
Finished Jul 18 04:49:13 PM PDT 24
Peak memory 248260 kb
Host smart-d129737a-17a0-4cba-b279-2d00d994c8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11867
84451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1186784451
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2754237260
Short name T405
Test name
Test status
Simulation time 2258354218 ps
CPU time 22.39 seconds
Started Jul 18 04:48:48 PM PDT 24
Finished Jul 18 04:49:13 PM PDT 24
Peak memory 248748 kb
Host smart-b800a26d-5ce6-4b51-9c48-1a16309f99ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27542
37260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2754237260
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3923907135
Short name T553
Test name
Test status
Simulation time 298942141 ps
CPU time 23.32 seconds
Started Jul 18 04:48:47 PM PDT 24
Finished Jul 18 04:49:13 PM PDT 24
Peak memory 257180 kb
Host smart-8ffd6074-93f8-41cd-bae6-c5fe5e2616b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39239
07135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3923907135
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1273097452
Short name T304
Test name
Test status
Simulation time 27562529161 ps
CPU time 1447.08 seconds
Started Jul 18 04:48:46 PM PDT 24
Finished Jul 18 05:12:56 PM PDT 24
Peak memory 273540 kb
Host smart-d669c6b7-736e-4682-a4a8-f977d3d6a691
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273097452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1273097452
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2491794062
Short name T239
Test name
Test status
Simulation time 44079165 ps
CPU time 2.54 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 04:49:48 PM PDT 24
Peak memory 249104 kb
Host smart-b3952813-1a1d-42f4-a353-bef2b11e2b8a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2491794062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2491794062
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1712985521
Short name T544
Test name
Test status
Simulation time 139402687683 ps
CPU time 2169.99 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 05:25:55 PM PDT 24
Peak memory 289836 kb
Host smart-a1b02905-2563-43cd-a4a2-03cf15a853ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712985521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1712985521
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2348451377
Short name T6
Test name
Test status
Simulation time 1024418870 ps
CPU time 23.08 seconds
Started Jul 18 04:49:38 PM PDT 24
Finished Jul 18 04:50:03 PM PDT 24
Peak memory 248884 kb
Host smart-37908f62-f965-48ec-bc20-9ccb83a3f1e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2348451377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2348451377
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3353577866
Short name T308
Test name
Test status
Simulation time 4907502141 ps
CPU time 123.48 seconds
Started Jul 18 04:49:42 PM PDT 24
Finished Jul 18 04:51:47 PM PDT 24
Peak memory 251116 kb
Host smart-18463549-192f-4b4e-a850-48f51316cd34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33535
77866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3353577866
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2144154002
Short name T69
Test name
Test status
Simulation time 374142773 ps
CPU time 28.76 seconds
Started Jul 18 04:49:36 PM PDT 24
Finished Jul 18 04:50:06 PM PDT 24
Peak memory 249440 kb
Host smart-49665e2c-408b-4e86-8665-7d7298059ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21441
54002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2144154002
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1839919611
Short name T349
Test name
Test status
Simulation time 41572173066 ps
CPU time 2390.39 seconds
Started Jul 18 04:49:39 PM PDT 24
Finished Jul 18 05:29:31 PM PDT 24
Peak memory 289760 kb
Host smart-b8bc2bd4-6ede-44da-aac7-57861bee6cc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839919611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1839919611
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.448542922
Short name T464
Test name
Test status
Simulation time 14054186039 ps
CPU time 801.52 seconds
Started Jul 18 04:49:47 PM PDT 24
Finished Jul 18 05:03:10 PM PDT 24
Peak memory 273664 kb
Host smart-b338ddd0-a9d6-47c2-9a3b-93d8ef07aaea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448542922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.448542922
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1113726018
Short name T665
Test name
Test status
Simulation time 299274432 ps
CPU time 29.25 seconds
Started Jul 18 04:49:47 PM PDT 24
Finished Jul 18 04:50:18 PM PDT 24
Peak memory 248924 kb
Host smart-2a1376f7-0f32-4f36-b453-0e4a9e71b571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11137
26018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1113726018
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3860384433
Short name T484
Test name
Test status
Simulation time 7430849511 ps
CPU time 39.61 seconds
Started Jul 18 04:49:37 PM PDT 24
Finished Jul 18 04:50:18 PM PDT 24
Peak memory 248284 kb
Host smart-e60bc504-8a8a-44bf-bda0-b161837476e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38603
84433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3860384433
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1826389333
Short name T79
Test name
Test status
Simulation time 213705683 ps
CPU time 7.09 seconds
Started Jul 18 04:49:36 PM PDT 24
Finished Jul 18 04:49:45 PM PDT 24
Peak memory 248088 kb
Host smart-520559a9-2473-46c9-8282-022e02518148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18263
89333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1826389333
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3926075088
Short name T686
Test name
Test status
Simulation time 78257952 ps
CPU time 6.41 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 04:49:51 PM PDT 24
Peak memory 251428 kb
Host smart-d357a43b-b44a-4d71-b3e9-b800e336062b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39260
75088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3926075088
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3141941286
Short name T88
Test name
Test status
Simulation time 75613977495 ps
CPU time 1580.27 seconds
Started Jul 18 04:49:46 PM PDT 24
Finished Jul 18 05:16:08 PM PDT 24
Peak memory 288696 kb
Host smart-9c0b804b-da0c-4d5a-9695-afe40ab3dd6a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141941286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3141941286
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.735036062
Short name T407
Test name
Test status
Simulation time 48542143514 ps
CPU time 1472.29 seconds
Started Jul 18 04:49:36 PM PDT 24
Finished Jul 18 05:14:10 PM PDT 24
Peak memory 286024 kb
Host smart-a5f89b1f-7d97-400b-b62b-c3c106327b5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735036062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.735036062
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1730097724
Short name T423
Test name
Test status
Simulation time 651969619 ps
CPU time 8.59 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 04:49:53 PM PDT 24
Peak memory 248876 kb
Host smart-da83e619-3788-471b-a1a1-c0932f6d5710
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1730097724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1730097724
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1726116659
Short name T445
Test name
Test status
Simulation time 4879444155 ps
CPU time 80.82 seconds
Started Jul 18 04:49:36 PM PDT 24
Finished Jul 18 04:50:58 PM PDT 24
Peak memory 257204 kb
Host smart-c943844f-4754-4287-854d-c3aa0df94025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17261
16659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1726116659
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.442527071
Short name T527
Test name
Test status
Simulation time 594597396 ps
CPU time 28.12 seconds
Started Jul 18 04:49:34 PM PDT 24
Finished Jul 18 04:50:03 PM PDT 24
Peak memory 248308 kb
Host smart-66544fe6-814d-44e8-bfc2-d3eae52ae098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44252
7071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.442527071
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1269162234
Short name T14
Test name
Test status
Simulation time 29885682129 ps
CPU time 1281.92 seconds
Started Jul 18 04:49:41 PM PDT 24
Finished Jul 18 05:11:05 PM PDT 24
Peak memory 283828 kb
Host smart-6082d267-b77e-48d7-9262-ef80cf5638e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269162234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1269162234
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2459906131
Short name T138
Test name
Test status
Simulation time 16729358273 ps
CPU time 1015.92 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 05:06:42 PM PDT 24
Peak memory 265480 kb
Host smart-fe692292-869d-47d4-b74c-4ca0a3772213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459906131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2459906131
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2368634511
Short name T332
Test name
Test status
Simulation time 13913982534 ps
CPU time 585.56 seconds
Started Jul 18 04:49:38 PM PDT 24
Finished Jul 18 04:59:25 PM PDT 24
Peak memory 248984 kb
Host smart-ae3f4a7c-c342-497f-9565-171fafa17f2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368634511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2368634511
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1568454664
Short name T522
Test name
Test status
Simulation time 1370833913 ps
CPU time 33.1 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 04:50:17 PM PDT 24
Peak memory 256164 kb
Host smart-5d6b0904-b507-44ef-a902-db65332e0a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15684
54664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1568454664
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3963318144
Short name T479
Test name
Test status
Simulation time 1357773128 ps
CPU time 39.52 seconds
Started Jul 18 04:49:33 PM PDT 24
Finished Jul 18 04:50:14 PM PDT 24
Peak memory 249488 kb
Host smart-bc929a12-4b4f-4d2a-91eb-02a640e302b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39633
18144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3963318144
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3371614155
Short name T640
Test name
Test status
Simulation time 243380026 ps
CPU time 4.86 seconds
Started Jul 18 04:49:33 PM PDT 24
Finished Jul 18 04:49:39 PM PDT 24
Peak memory 240692 kb
Host smart-c0c8496c-5acd-49f3-bb06-02c3086df790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33716
14155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3371614155
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2324684671
Short name T426
Test name
Test status
Simulation time 848902709 ps
CPU time 5.01 seconds
Started Jul 18 04:49:41 PM PDT 24
Finished Jul 18 04:49:47 PM PDT 24
Peak memory 250900 kb
Host smart-40f6cfc2-308f-48fc-a53e-90f19f657e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23246
84671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2324684671
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3005472006
Short name T100
Test name
Test status
Simulation time 15196615013 ps
CPU time 1517.31 seconds
Started Jul 18 04:49:41 PM PDT 24
Finished Jul 18 05:15:00 PM PDT 24
Peak memory 289372 kb
Host smart-a1826fd5-7c59-46f2-80d7-14a0732d0007
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005472006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3005472006
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1663737951
Short name T211
Test name
Test status
Simulation time 365679577474 ps
CPU time 6351.05 seconds
Started Jul 18 04:49:47 PM PDT 24
Finished Jul 18 06:35:40 PM PDT 24
Peak memory 339176 kb
Host smart-37282e09-d323-4a8f-95a9-5acdd1e16389
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663737951 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1663737951
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1763571428
Short name T237
Test name
Test status
Simulation time 37082227 ps
CPU time 3.56 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 04:49:48 PM PDT 24
Peak memory 249144 kb
Host smart-a6199c22-511d-4238-877c-e8c0321580cf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1763571428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1763571428
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.4253584946
Short name T108
Test name
Test status
Simulation time 12439269909 ps
CPU time 1264.37 seconds
Started Jul 18 04:49:39 PM PDT 24
Finished Jul 18 05:10:45 PM PDT 24
Peak memory 289796 kb
Host smart-e2a00ef3-7a6d-4cde-be60-a59c7e449f50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253584946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.4253584946
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3150784438
Short name T435
Test name
Test status
Simulation time 779994349 ps
CPU time 8.86 seconds
Started Jul 18 04:49:40 PM PDT 24
Finished Jul 18 04:49:50 PM PDT 24
Peak memory 248816 kb
Host smart-e4772dab-709a-4075-8c45-71be2d2ae63e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3150784438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3150784438
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2871314022
Short name T622
Test name
Test status
Simulation time 396745626 ps
CPU time 25.4 seconds
Started Jul 18 04:49:41 PM PDT 24
Finished Jul 18 04:50:07 PM PDT 24
Peak memory 256608 kb
Host smart-1f67af27-0b27-403c-916d-1675380beb8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28713
14022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2871314022
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.199637575
Short name T82
Test name
Test status
Simulation time 304600446 ps
CPU time 10.13 seconds
Started Jul 18 04:49:39 PM PDT 24
Finished Jul 18 04:49:50 PM PDT 24
Peak memory 256180 kb
Host smart-f6277d21-1b07-44ad-b46d-e649c89cb483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19963
7575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.199637575
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.493706050
Short name T345
Test name
Test status
Simulation time 23252072529 ps
CPU time 1006.69 seconds
Started Jul 18 04:49:41 PM PDT 24
Finished Jul 18 05:06:29 PM PDT 24
Peak memory 273412 kb
Host smart-3acd66e0-ae8e-49be-abdd-ed325538adf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493706050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.493706050
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2866425067
Short name T512
Test name
Test status
Simulation time 35001539876 ps
CPU time 1136.34 seconds
Started Jul 18 04:49:41 PM PDT 24
Finished Jul 18 05:08:39 PM PDT 24
Peak memory 273480 kb
Host smart-bdf75547-38ce-4c48-8d5a-86defcb08c16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866425067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2866425067
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.73248398
Short name T327
Test name
Test status
Simulation time 9527011325 ps
CPU time 288.76 seconds
Started Jul 18 04:49:47 PM PDT 24
Finished Jul 18 04:54:37 PM PDT 24
Peak memory 249076 kb
Host smart-7eb85944-16bc-42c8-9f31-d087da6eb7dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73248398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.73248398
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.4143851968
Short name T384
Test name
Test status
Simulation time 1746532377 ps
CPU time 52.19 seconds
Started Jul 18 04:49:41 PM PDT 24
Finished Jul 18 04:50:35 PM PDT 24
Peak memory 248984 kb
Host smart-8aaac39c-d207-412d-b0aa-92562afb195c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41438
51968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.4143851968
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2128878660
Short name T659
Test name
Test status
Simulation time 394339620 ps
CPU time 26.39 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 04:50:11 PM PDT 24
Peak memory 256388 kb
Host smart-1fb2c4a8-0fb6-4747-9207-e55fc7619b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21288
78660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2128878660
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3000892884
Short name T572
Test name
Test status
Simulation time 658734853 ps
CPU time 29.28 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 04:50:14 PM PDT 24
Peak memory 248928 kb
Host smart-f0472154-6be1-408a-b911-7290afb17f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30008
92884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3000892884
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.101598023
Short name T93
Test name
Test status
Simulation time 26349392314 ps
CPU time 1489.08 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 05:14:35 PM PDT 24
Peak memory 289988 kb
Host smart-60d41e82-b64f-4877-ad34-a0564bb0d7bf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101598023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.101598023
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1304378259
Short name T519
Test name
Test status
Simulation time 138185548737 ps
CPU time 3674.83 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 349108 kb
Host smart-99d664ad-80c2-4b4f-aa95-bd3616d52493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304378259 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1304378259
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2027379134
Short name T34
Test name
Test status
Simulation time 43626504 ps
CPU time 3.77 seconds
Started Jul 18 04:49:45 PM PDT 24
Finished Jul 18 04:49:50 PM PDT 24
Peak memory 249136 kb
Host smart-66e9a8c1-c5dd-4064-971d-1f49424acf0e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2027379134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2027379134
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3212471128
Short name T23
Test name
Test status
Simulation time 144391694516 ps
CPU time 1574.15 seconds
Started Jul 18 04:49:39 PM PDT 24
Finished Jul 18 05:15:55 PM PDT 24
Peak memory 273192 kb
Host smart-1959d946-c1d8-4b0c-94b8-ee4f165f2bd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212471128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3212471128
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3223334871
Short name T249
Test name
Test status
Simulation time 5003232324 ps
CPU time 43.05 seconds
Started Jul 18 04:49:47 PM PDT 24
Finished Jul 18 04:50:32 PM PDT 24
Peak memory 249084 kb
Host smart-2adf919f-951a-48bb-938e-c37e5f7fd48d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3223334871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3223334871
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.872087655
Short name T388
Test name
Test status
Simulation time 2204876543 ps
CPU time 137.1 seconds
Started Jul 18 04:49:41 PM PDT 24
Finished Jul 18 04:52:00 PM PDT 24
Peak memory 257220 kb
Host smart-e61717ae-a3ff-479d-af81-aebcb4713339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87208
7655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.872087655
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1478191384
Short name T408
Test name
Test status
Simulation time 2494274228 ps
CPU time 35.37 seconds
Started Jul 18 04:49:48 PM PDT 24
Finished Jul 18 04:50:25 PM PDT 24
Peak memory 248912 kb
Host smart-a0bc3c7c-3f6e-494a-89ed-fcc9668f5701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14781
91384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1478191384
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2601638304
Short name T213
Test name
Test status
Simulation time 37895854336 ps
CPU time 1497.85 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 05:14:44 PM PDT 24
Peak memory 289128 kb
Host smart-d2ebcd12-b9c0-435e-a77c-6f98f0cb50dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601638304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2601638304
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.212870439
Short name T520
Test name
Test status
Simulation time 83701438022 ps
CPU time 1340.46 seconds
Started Jul 18 04:49:42 PM PDT 24
Finished Jul 18 05:12:04 PM PDT 24
Peak memory 273276 kb
Host smart-a2962de9-c8b6-453c-9f29-50ef17d4c79b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212870439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.212870439
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.4285471903
Short name T510
Test name
Test status
Simulation time 4812849443 ps
CPU time 60.68 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 04:50:47 PM PDT 24
Peak memory 256844 kb
Host smart-46bc2320-3aaf-4463-862d-640fedb4488e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42854
71903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.4285471903
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1764775434
Short name T607
Test name
Test status
Simulation time 803439158 ps
CPU time 27.13 seconds
Started Jul 18 04:49:35 PM PDT 24
Finished Jul 18 04:50:04 PM PDT 24
Peak memory 248660 kb
Host smart-291b82eb-27c6-44a3-b4cf-d5ba09d2f59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17647
75434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1764775434
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.251217443
Short name T73
Test name
Test status
Simulation time 653232509 ps
CPU time 27.77 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 04:50:14 PM PDT 24
Peak memory 257064 kb
Host smart-d5f1dbe6-574e-4752-bf34-f476b527eae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25121
7443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.251217443
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2827133085
Short name T566
Test name
Test status
Simulation time 184229791970 ps
CPU time 2527.12 seconds
Started Jul 18 04:49:41 PM PDT 24
Finished Jul 18 05:31:49 PM PDT 24
Peak memory 289536 kb
Host smart-6f554af9-2212-47c9-9ff7-8860a2eb4920
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827133085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2827133085
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3161665787
Short name T53
Test name
Test status
Simulation time 84731668082 ps
CPU time 8428.44 seconds
Started Jul 18 04:49:45 PM PDT 24
Finished Jul 18 07:10:16 PM PDT 24
Peak memory 371332 kb
Host smart-3f0887e1-5d48-40cb-9238-8d901f1627f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161665787 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3161665787
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.131973078
Short name T240
Test name
Test status
Simulation time 230255360 ps
CPU time 3.53 seconds
Started Jul 18 04:49:45 PM PDT 24
Finished Jul 18 04:49:50 PM PDT 24
Peak memory 249120 kb
Host smart-ce5d3fc0-73ee-4aaf-a701-fbd4b9d082d3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=131973078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.131973078
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1782386426
Short name T123
Test name
Test status
Simulation time 316186617829 ps
CPU time 2565.96 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 05:32:30 PM PDT 24
Peak memory 284576 kb
Host smart-2080e177-5b85-44aa-b4b3-73c68b3dec3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782386426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1782386426
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1564466005
Short name T662
Test name
Test status
Simulation time 386135141 ps
CPU time 18.09 seconds
Started Jul 18 04:49:49 PM PDT 24
Finished Jul 18 04:50:07 PM PDT 24
Peak memory 248852 kb
Host smart-90ba1911-145c-4e5f-91b7-fafd7ceb5c4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1564466005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1564466005
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2643599559
Short name T542
Test name
Test status
Simulation time 5990941920 ps
CPU time 181.02 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 04:52:47 PM PDT 24
Peak memory 251044 kb
Host smart-b664d212-6531-4467-83f9-5c3b5c1691e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26435
99559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2643599559
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.4148887259
Short name T658
Test name
Test status
Simulation time 2201961127 ps
CPU time 60.89 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 04:50:47 PM PDT 24
Peak memory 248404 kb
Host smart-d7b001e1-9a59-42f3-9c5c-71df4bf570de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41488
87259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.4148887259
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1373121225
Short name T466
Test name
Test status
Simulation time 152368650275 ps
CPU time 2108.53 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 05:24:54 PM PDT 24
Peak memory 273528 kb
Host smart-7fa3adb5-1839-4930-ba49-8eb73963d866
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373121225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1373121225
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.268793759
Short name T335
Test name
Test status
Simulation time 3858800323 ps
CPU time 150.39 seconds
Started Jul 18 04:49:45 PM PDT 24
Finished Jul 18 04:52:17 PM PDT 24
Peak memory 248800 kb
Host smart-4481e17e-e4fb-42a5-ac7f-43dfc34cc59e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268793759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.268793759
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2900440823
Short name T514
Test name
Test status
Simulation time 562960992 ps
CPU time 32.45 seconds
Started Jul 18 04:49:45 PM PDT 24
Finished Jul 18 04:50:19 PM PDT 24
Peak memory 256088 kb
Host smart-4591d545-7121-4862-9891-b61acf3d7554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29004
40823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2900440823
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3304484973
Short name T447
Test name
Test status
Simulation time 335489734 ps
CPU time 7.19 seconds
Started Jul 18 04:49:45 PM PDT 24
Finished Jul 18 04:49:54 PM PDT 24
Peak memory 248316 kb
Host smart-47d9b57e-055a-4e17-ab6a-f1f26a93a302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33044
84973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3304484973
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2795744957
Short name T584
Test name
Test status
Simulation time 83613789 ps
CPU time 3.17 seconds
Started Jul 18 04:49:38 PM PDT 24
Finished Jul 18 04:49:42 PM PDT 24
Peak memory 240196 kb
Host smart-cca7accc-ef9e-4bed-89f1-11f77407c9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27957
44957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2795744957
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.4217757620
Short name T518
Test name
Test status
Simulation time 578179592 ps
CPU time 36.22 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 04:50:23 PM PDT 24
Peak memory 248916 kb
Host smart-4c439b07-a40a-4f5e-a28a-9ccb7dd28cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42177
57620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.4217757620
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1367962822
Short name T54
Test name
Test status
Simulation time 15257658577 ps
CPU time 1179.42 seconds
Started Jul 18 04:49:45 PM PDT 24
Finished Jul 18 05:09:27 PM PDT 24
Peak memory 288724 kb
Host smart-5144fea5-1680-4644-8854-c8d173dec54d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367962822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1367962822
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.487308818
Short name T59
Test name
Test status
Simulation time 100252896362 ps
CPU time 9243.26 seconds
Started Jul 18 04:49:54 PM PDT 24
Finished Jul 18 07:23:59 PM PDT 24
Peak memory 394700 kb
Host smart-a8789cf1-417f-4568-8e98-ac43276cffdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487308818 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.487308818
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.979108863
Short name T244
Test name
Test status
Simulation time 54348167 ps
CPU time 4.01 seconds
Started Jul 18 04:49:53 PM PDT 24
Finished Jul 18 04:49:58 PM PDT 24
Peak memory 249068 kb
Host smart-4ba99071-0a60-4682-b6c2-c4c93f155e48
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=979108863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.979108863
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.396207930
Short name T474
Test name
Test status
Simulation time 13975196389 ps
CPU time 717.42 seconds
Started Jul 18 04:50:01 PM PDT 24
Finished Jul 18 05:02:00 PM PDT 24
Peak memory 267492 kb
Host smart-59f528d9-9db5-4915-8ec3-14300327ca10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396207930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.396207930
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.4053592484
Short name T610
Test name
Test status
Simulation time 955303631 ps
CPU time 40.36 seconds
Started Jul 18 04:49:55 PM PDT 24
Finished Jul 18 04:50:37 PM PDT 24
Peak memory 248868 kb
Host smart-d486b396-4efd-4a48-88c9-3e61d1a869cf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4053592484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4053592484
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.4138263980
Short name T556
Test name
Test status
Simulation time 11607673915 ps
CPU time 152.89 seconds
Started Jul 18 04:49:51 PM PDT 24
Finished Jul 18 04:52:25 PM PDT 24
Peak memory 251092 kb
Host smart-939ac84d-2fa9-4c84-b5aa-563afb1dd58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41382
63980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.4138263980
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.4059063257
Short name T481
Test name
Test status
Simulation time 2143524047 ps
CPU time 34.97 seconds
Started Jul 18 04:49:56 PM PDT 24
Finished Jul 18 04:50:33 PM PDT 24
Peak memory 248860 kb
Host smart-f4763911-afed-4213-8747-c951aa7dbdf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40590
63257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.4059063257
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.746387492
Short name T348
Test name
Test status
Simulation time 120894083504 ps
CPU time 1414.1 seconds
Started Jul 18 04:50:01 PM PDT 24
Finished Jul 18 05:13:37 PM PDT 24
Peak memory 273468 kb
Host smart-f83d1619-6c53-4337-85c8-4c58bad9d404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746387492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.746387492
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.864177668
Short name T456
Test name
Test status
Simulation time 84538383703 ps
CPU time 2359 seconds
Started Jul 18 04:49:59 PM PDT 24
Finished Jul 18 05:29:21 PM PDT 24
Peak memory 281732 kb
Host smart-b6b70203-a438-4a09-9aa1-7227d90c322e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864177668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.864177668
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3371950836
Short name T642
Test name
Test status
Simulation time 734584632 ps
CPU time 46.94 seconds
Started Jul 18 04:49:58 PM PDT 24
Finished Jul 18 04:50:46 PM PDT 24
Peak memory 256304 kb
Host smart-4391dc5a-fdf4-4943-9a0e-34ab293dc808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33719
50836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3371950836
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.720635867
Short name T651
Test name
Test status
Simulation time 510062198 ps
CPU time 39.85 seconds
Started Jul 18 04:49:59 PM PDT 24
Finished Jul 18 04:50:41 PM PDT 24
Peak memory 256628 kb
Host smart-676b20b1-0783-4849-889c-659b19423f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72063
5867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.720635867
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1050314701
Short name T75
Test name
Test status
Simulation time 1543361547 ps
CPU time 34.6 seconds
Started Jul 18 04:50:01 PM PDT 24
Finished Jul 18 04:50:37 PM PDT 24
Peak memory 248932 kb
Host smart-0ec21dad-64b2-4f7d-9e37-55178609bed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10503
14701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1050314701
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1848924165
Short name T594
Test name
Test status
Simulation time 865665846 ps
CPU time 38.07 seconds
Started Jul 18 04:49:57 PM PDT 24
Finished Jul 18 04:50:37 PM PDT 24
Peak memory 256776 kb
Host smart-0f511005-9643-43a9-92aa-4c00f82751b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18489
24165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1848924165
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.530687258
Short name T131
Test name
Test status
Simulation time 181472779 ps
CPU time 5.27 seconds
Started Jul 18 04:49:57 PM PDT 24
Finished Jul 18 04:50:04 PM PDT 24
Peak memory 251672 kb
Host smart-32e4be7d-64f5-4f88-9958-ffa195636118
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530687258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.530687258
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3179613478
Short name T226
Test name
Test status
Simulation time 148368809100 ps
CPU time 3639.58 seconds
Started Jul 18 04:49:55 PM PDT 24
Finished Jul 18 05:50:37 PM PDT 24
Peak memory 337724 kb
Host smart-26493f96-94c6-4384-a6f8-b1fa6ab857a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179613478 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3179613478
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1919955499
Short name T233
Test name
Test status
Simulation time 13674827 ps
CPU time 2.28 seconds
Started Jul 18 04:49:58 PM PDT 24
Finished Jul 18 04:50:01 PM PDT 24
Peak memory 249172 kb
Host smart-16ef7699-7c9f-4a7a-a7f6-38e7b217db20
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1919955499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1919955499
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1890248744
Short name T438
Test name
Test status
Simulation time 16477273115 ps
CPU time 1350.11 seconds
Started Jul 18 04:49:54 PM PDT 24
Finished Jul 18 05:12:25 PM PDT 24
Peak memory 289000 kb
Host smart-6f4261fe-fefb-48fd-b4a5-f4a3c750ee2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890248744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1890248744
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2586313917
Short name T671
Test name
Test status
Simulation time 525824599 ps
CPU time 9.12 seconds
Started Jul 18 04:49:52 PM PDT 24
Finished Jul 18 04:50:02 PM PDT 24
Peak memory 248912 kb
Host smart-edc9abb8-58e3-4278-ab6f-26bd9f4ef627
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2586313917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2586313917
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3269660327
Short name T441
Test name
Test status
Simulation time 3284557271 ps
CPU time 154.34 seconds
Started Jul 18 04:49:57 PM PDT 24
Finished Jul 18 04:52:33 PM PDT 24
Peak memory 252188 kb
Host smart-2e3cb578-5598-4665-8150-9273430dd3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32696
60327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3269660327
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2625506870
Short name T620
Test name
Test status
Simulation time 77966854727 ps
CPU time 1181.24 seconds
Started Jul 18 04:49:54 PM PDT 24
Finished Jul 18 05:09:37 PM PDT 24
Peak memory 289068 kb
Host smart-04eef340-ec1b-477a-938f-c0581b30b71b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625506870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2625506870
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1842335732
Short name T541
Test name
Test status
Simulation time 1803542741 ps
CPU time 79.61 seconds
Started Jul 18 04:49:56 PM PDT 24
Finished Jul 18 04:51:16 PM PDT 24
Peak memory 248872 kb
Host smart-3b5d0b8e-c309-423d-80e2-1006348215bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842335732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1842335732
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2569518175
Short name T406
Test name
Test status
Simulation time 550363436 ps
CPU time 15.15 seconds
Started Jul 18 04:49:54 PM PDT 24
Finished Jul 18 04:50:10 PM PDT 24
Peak memory 248836 kb
Host smart-47233701-ba25-412d-ba47-1334ef324752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25695
18175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2569518175
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3425268733
Short name T385
Test name
Test status
Simulation time 40869953 ps
CPU time 5.27 seconds
Started Jul 18 04:50:05 PM PDT 24
Finished Jul 18 04:50:12 PM PDT 24
Peak memory 248168 kb
Host smart-eee79975-1d01-4b2d-84c6-7f04415f64a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34252
68733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3425268733
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1427840361
Short name T443
Test name
Test status
Simulation time 180471202 ps
CPU time 12.89 seconds
Started Jul 18 04:49:59 PM PDT 24
Finished Jul 18 04:50:14 PM PDT 24
Peak memory 248832 kb
Host smart-0f24e611-c28b-424c-9fa0-16c3054a6238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14278
40361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1427840361
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3416781405
Short name T539
Test name
Test status
Simulation time 278473955 ps
CPU time 16.13 seconds
Started Jul 18 04:50:00 PM PDT 24
Finished Jul 18 04:50:18 PM PDT 24
Peak memory 249380 kb
Host smart-f6819715-f971-45fb-8bea-10fb89f4416f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34167
81405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3416781405
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1318262944
Short name T254
Test name
Test status
Simulation time 36729228112 ps
CPU time 2271.7 seconds
Started Jul 18 04:49:53 PM PDT 24
Finished Jul 18 05:27:46 PM PDT 24
Peak memory 289164 kb
Host smart-7776a948-2714-4007-9f0f-d5e466f61183
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318262944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1318262944
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3280680828
Short name T602
Test name
Test status
Simulation time 1212800251 ps
CPU time 8.95 seconds
Started Jul 18 04:49:56 PM PDT 24
Finished Jul 18 04:50:07 PM PDT 24
Peak memory 248992 kb
Host smart-fbb8b6b2-2280-42fe-a17f-bdc237d93464
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3280680828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3280680828
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1585579711
Short name T298
Test name
Test status
Simulation time 20739442616 ps
CPU time 158.91 seconds
Started Jul 18 04:49:54 PM PDT 24
Finished Jul 18 04:52:34 PM PDT 24
Peak memory 257232 kb
Host smart-34a74c89-0612-451a-8d49-4a38fe7e9fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15855
79711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1585579711
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2074324453
Short name T95
Test name
Test status
Simulation time 180166902 ps
CPU time 19.32 seconds
Started Jul 18 04:49:55 PM PDT 24
Finished Jul 18 04:50:15 PM PDT 24
Peak memory 248408 kb
Host smart-98dd3eff-a3bf-4a6e-a457-5ff99d6e2b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20743
24453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2074324453
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1653195663
Short name T343
Test name
Test status
Simulation time 210252376926 ps
CPU time 2811.91 seconds
Started Jul 18 04:50:02 PM PDT 24
Finished Jul 18 05:36:56 PM PDT 24
Peak memory 288952 kb
Host smart-f0ee0dff-039d-449e-9018-aa3446d0f98a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653195663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1653195663
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2463049519
Short name T448
Test name
Test status
Simulation time 99194005896 ps
CPU time 1331.14 seconds
Started Jul 18 04:49:59 PM PDT 24
Finished Jul 18 05:12:11 PM PDT 24
Peak memory 273612 kb
Host smart-53a26ef0-3725-4a1b-8348-0c86d3608a63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463049519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2463049519
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.4131741653
Short name T330
Test name
Test status
Simulation time 12159086880 ps
CPU time 435.4 seconds
Started Jul 18 04:49:55 PM PDT 24
Finished Jul 18 04:57:11 PM PDT 24
Peak memory 249008 kb
Host smart-b58417d9-e3d1-4559-8e29-362936cbb006
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131741653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.4131741653
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1475567628
Short name T506
Test name
Test status
Simulation time 484575575 ps
CPU time 16.41 seconds
Started Jul 18 04:50:00 PM PDT 24
Finished Jul 18 04:50:18 PM PDT 24
Peak memory 248908 kb
Host smart-a339b22c-b9d7-44ca-93c4-f180b46afc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14755
67628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1475567628
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.478867206
Short name T386
Test name
Test status
Simulation time 92873307 ps
CPU time 12.91 seconds
Started Jul 18 04:49:54 PM PDT 24
Finished Jul 18 04:50:08 PM PDT 24
Peak memory 256636 kb
Host smart-e99ae80c-fb91-4d3d-8a24-4efcf50b4096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47886
7206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.478867206
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.494696214
Short name T417
Test name
Test status
Simulation time 248738518 ps
CPU time 17.02 seconds
Started Jul 18 04:49:59 PM PDT 24
Finished Jul 18 04:50:18 PM PDT 24
Peak memory 248872 kb
Host smart-a1dd2af5-b2f6-47b3-bdc1-cd2a84975e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49469
6214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.494696214
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.285109199
Short name T390
Test name
Test status
Simulation time 947512277 ps
CPU time 30.7 seconds
Started Jul 18 04:49:57 PM PDT 24
Finished Jul 18 04:50:29 PM PDT 24
Peak memory 257048 kb
Host smart-ff6969ef-9140-4e55-85bb-6a649b0887a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28510
9199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.285109199
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3300748658
Short name T230
Test name
Test status
Simulation time 123460326 ps
CPU time 3.33 seconds
Started Jul 18 04:50:02 PM PDT 24
Finished Jul 18 04:50:07 PM PDT 24
Peak memory 249196 kb
Host smart-2e455d92-5bb5-4183-8ef5-0dad7295649d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3300748658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3300748658
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2836793077
Short name T425
Test name
Test status
Simulation time 662103776 ps
CPU time 16.7 seconds
Started Jul 18 04:50:02 PM PDT 24
Finished Jul 18 04:50:20 PM PDT 24
Peak memory 248932 kb
Host smart-ddd68951-9b17-4a3d-8eba-7179b2458f5d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2836793077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2836793077
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3419065854
Short name T437
Test name
Test status
Simulation time 9416280888 ps
CPU time 140.18 seconds
Started Jul 18 04:49:58 PM PDT 24
Finished Jul 18 04:52:19 PM PDT 24
Peak memory 257212 kb
Host smart-86a3073d-538b-4ef0-a993-0f05c094ce0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34190
65854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3419065854
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2066314589
Short name T442
Test name
Test status
Simulation time 1668737893 ps
CPU time 22.42 seconds
Started Jul 18 04:49:56 PM PDT 24
Finished Jul 18 04:50:20 PM PDT 24
Peak memory 256108 kb
Host smart-65331432-36d5-4634-a2af-45eae5274bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20663
14589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2066314589
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2047723530
Short name T344
Test name
Test status
Simulation time 37444488300 ps
CPU time 1560.67 seconds
Started Jul 18 04:49:55 PM PDT 24
Finished Jul 18 05:15:57 PM PDT 24
Peak memory 289092 kb
Host smart-3ce697f3-99fe-45b9-9ba6-b8daaaed622d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047723530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2047723530
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3845304324
Short name T552
Test name
Test status
Simulation time 42860380667 ps
CPU time 1441.62 seconds
Started Jul 18 04:50:00 PM PDT 24
Finished Jul 18 05:14:04 PM PDT 24
Peak memory 273588 kb
Host smart-c2b6e2ad-2a17-4cf5-a5f6-0a9bb028f9ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845304324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3845304324
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1630237759
Short name T621
Test name
Test status
Simulation time 34320368033 ps
CPU time 357.58 seconds
Started Jul 18 04:50:04 PM PDT 24
Finished Jul 18 04:56:03 PM PDT 24
Peak memory 249112 kb
Host smart-749e5181-f59d-43ea-a05e-bbcc349c2a53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630237759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1630237759
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.193607049
Short name T375
Test name
Test status
Simulation time 644991983 ps
CPU time 29.59 seconds
Started Jul 18 04:49:57 PM PDT 24
Finished Jul 18 04:50:28 PM PDT 24
Peak memory 248936 kb
Host smart-57b6e8f1-341c-406f-85d5-b8a1e1675aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19360
7049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.193607049
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2236654623
Short name T125
Test name
Test status
Simulation time 3273795525 ps
CPU time 50.4 seconds
Started Jul 18 04:50:00 PM PDT 24
Finished Jul 18 04:50:53 PM PDT 24
Peak memory 249392 kb
Host smart-3005ccb0-aba1-4c7b-9154-28e5fd3477cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22366
54623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2236654623
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1743299263
Short name T33
Test name
Test status
Simulation time 6277032260 ps
CPU time 36.33 seconds
Started Jul 18 04:49:56 PM PDT 24
Finished Jul 18 04:50:33 PM PDT 24
Peak memory 249008 kb
Host smart-ca2eb419-9d19-4300-b7f3-691471905ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17432
99263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1743299263
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2205939738
Short name T536
Test name
Test status
Simulation time 228869358 ps
CPU time 4.61 seconds
Started Jul 18 04:49:54 PM PDT 24
Finished Jul 18 04:49:59 PM PDT 24
Peak memory 251264 kb
Host smart-82330b27-a95e-41d2-86c9-df5d4d4591e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22059
39738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2205939738
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3801330869
Short name T287
Test name
Test status
Simulation time 31415275818 ps
CPU time 399.01 seconds
Started Jul 18 04:50:05 PM PDT 24
Finished Jul 18 04:56:46 PM PDT 24
Peak memory 257300 kb
Host smart-ae82a364-a58a-468f-b263-2210c3c87259
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801330869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3801330869
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2252294386
Short name T243
Test name
Test status
Simulation time 80943686 ps
CPU time 3.89 seconds
Started Jul 18 04:50:03 PM PDT 24
Finished Jul 18 04:50:08 PM PDT 24
Peak memory 248712 kb
Host smart-74892573-b0ca-48a0-a5d0-43ad70d1bce9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2252294386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2252294386
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1267554468
Short name T357
Test name
Test status
Simulation time 31776101312 ps
CPU time 1929.06 seconds
Started Jul 18 04:50:09 PM PDT 24
Finished Jul 18 05:22:20 PM PDT 24
Peak memory 289532 kb
Host smart-9c75fc1b-3710-483d-b48f-957dad3d78f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267554468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1267554468
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3101560514
Short name T652
Test name
Test status
Simulation time 2657580846 ps
CPU time 54.96 seconds
Started Jul 18 04:50:09 PM PDT 24
Finished Jul 18 04:51:05 PM PDT 24
Peak memory 248920 kb
Host smart-0d4e1ffc-9e5c-4a3d-a3cc-d4ff38c6c117
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3101560514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3101560514
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.184110319
Short name T534
Test name
Test status
Simulation time 7304344018 ps
CPU time 112.85 seconds
Started Jul 18 04:50:06 PM PDT 24
Finished Jul 18 04:52:00 PM PDT 24
Peak memory 256716 kb
Host smart-395d77c7-e20d-44da-a609-3647e7ac0f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18411
0319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.184110319
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.4123590213
Short name T669
Test name
Test status
Simulation time 753164708 ps
CPU time 12.5 seconds
Started Jul 18 04:50:08 PM PDT 24
Finished Jul 18 04:50:21 PM PDT 24
Peak memory 253920 kb
Host smart-d830d858-500d-43fe-ae34-6103219a99bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41235
90213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.4123590213
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2629121027
Short name T358
Test name
Test status
Simulation time 232399541629 ps
CPU time 2410.09 seconds
Started Jul 18 04:49:59 PM PDT 24
Finished Jul 18 05:30:12 PM PDT 24
Peak memory 289572 kb
Host smart-90749004-4c26-49ca-8b4e-efdb6f56c313
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629121027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2629121027
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2171869417
Short name T579
Test name
Test status
Simulation time 30211654257 ps
CPU time 1174.43 seconds
Started Jul 18 04:50:06 PM PDT 24
Finished Jul 18 05:09:42 PM PDT 24
Peak memory 289324 kb
Host smart-d143073f-00d2-4d3a-8827-8d8af7657bd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171869417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2171869417
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3231965318
Short name T322
Test name
Test status
Simulation time 7182763216 ps
CPU time 296.54 seconds
Started Jul 18 04:50:08 PM PDT 24
Finished Jul 18 04:55:06 PM PDT 24
Peak memory 248972 kb
Host smart-cfa45744-c042-4f7e-874d-b4af94624d23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231965318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3231965318
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1736012365
Short name T428
Test name
Test status
Simulation time 1251930528 ps
CPU time 33.08 seconds
Started Jul 18 04:50:02 PM PDT 24
Finished Jul 18 04:50:36 PM PDT 24
Peak memory 256540 kb
Host smart-b405ff5c-d40e-424f-88ae-1e57da03836b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17360
12365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1736012365
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2878942027
Short name T32
Test name
Test status
Simulation time 225664170 ps
CPU time 21.57 seconds
Started Jul 18 04:50:05 PM PDT 24
Finished Jul 18 04:50:29 PM PDT 24
Peak memory 256592 kb
Host smart-6bf8f7ae-2e5d-42bb-842c-5c4a44be9f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28789
42027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2878942027
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2131422655
Short name T288
Test name
Test status
Simulation time 178787387 ps
CPU time 17.67 seconds
Started Jul 18 04:49:59 PM PDT 24
Finished Jul 18 04:50:18 PM PDT 24
Peak memory 256300 kb
Host smart-e6d197aa-0607-43a4-b2df-0a84f8fd0f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21314
22655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2131422655
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.100797052
Short name T625
Test name
Test status
Simulation time 195741165 ps
CPU time 18.31 seconds
Started Jul 18 04:50:05 PM PDT 24
Finished Jul 18 04:50:25 PM PDT 24
Peak memory 256972 kb
Host smart-64d0a959-188a-4d18-90b2-5de473a4f48c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10079
7052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.100797052
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3807411562
Short name T294
Test name
Test status
Simulation time 57985795505 ps
CPU time 1556.8 seconds
Started Jul 18 04:50:06 PM PDT 24
Finished Jul 18 05:16:05 PM PDT 24
Peak memory 289832 kb
Host smart-a31bd3bc-e71b-499d-a24d-68335fea1b11
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807411562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3807411562
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3380948036
Short name T212
Test name
Test status
Simulation time 45215157239 ps
CPU time 2848.89 seconds
Started Jul 18 04:49:57 PM PDT 24
Finished Jul 18 05:37:28 PM PDT 24
Peak memory 306060 kb
Host smart-427973e4-84c4-4a6b-b912-4a9eed52b93f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380948036 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3380948036
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3328100308
Short name T234
Test name
Test status
Simulation time 13223843 ps
CPU time 2.55 seconds
Started Jul 18 04:48:47 PM PDT 24
Finished Jul 18 04:48:52 PM PDT 24
Peak memory 249084 kb
Host smart-be352cfd-c772-4f59-a79e-f5e112793e1e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3328100308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3328100308
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1706690229
Short name T697
Test name
Test status
Simulation time 65935578824 ps
CPU time 1579.89 seconds
Started Jul 18 04:48:52 PM PDT 24
Finished Jul 18 05:15:14 PM PDT 24
Peak memory 289368 kb
Host smart-f08947d9-4e50-4808-ac31-c1489b20c8fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706690229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1706690229
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.808836474
Short name T590
Test name
Test status
Simulation time 2176985838 ps
CPU time 16.18 seconds
Started Jul 18 04:48:48 PM PDT 24
Finished Jul 18 04:49:06 PM PDT 24
Peak memory 248960 kb
Host smart-13a42a32-ec0d-4c8d-ad31-bb8bd668b44e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=808836474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.808836474
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.670120496
Short name T598
Test name
Test status
Simulation time 7231541793 ps
CPU time 115.31 seconds
Started Jul 18 04:48:51 PM PDT 24
Finished Jul 18 04:50:48 PM PDT 24
Peak memory 256728 kb
Host smart-e2f3ff8b-a5e0-4d88-9337-726a8a32a74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67012
0496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.670120496
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3166319812
Short name T414
Test name
Test status
Simulation time 1967975832 ps
CPU time 63.66 seconds
Started Jul 18 04:48:48 PM PDT 24
Finished Jul 18 04:49:54 PM PDT 24
Peak memory 256940 kb
Host smart-d9a6fd11-8d9e-40db-9572-9adb67b46c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31663
19812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3166319812
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1682609605
Short name T455
Test name
Test status
Simulation time 30845999444 ps
CPU time 1152.68 seconds
Started Jul 18 04:48:52 PM PDT 24
Finished Jul 18 05:08:06 PM PDT 24
Peak memory 289224 kb
Host smart-be6c0805-dc3b-42cc-b6cf-08c040156320
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682609605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1682609605
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2200675525
Short name T526
Test name
Test status
Simulation time 23020239243 ps
CPU time 1433.42 seconds
Started Jul 18 04:48:52 PM PDT 24
Finished Jul 18 05:12:48 PM PDT 24
Peak memory 273012 kb
Host smart-15a7cc84-2c3f-46ea-9f69-956b865c8999
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200675525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2200675525
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4231463933
Short name T517
Test name
Test status
Simulation time 9031349259 ps
CPU time 190.83 seconds
Started Jul 18 04:48:52 PM PDT 24
Finished Jul 18 04:52:04 PM PDT 24
Peak memory 247952 kb
Host smart-83590c04-fa8c-4450-8826-420809ca856a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231463933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4231463933
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2620894956
Short name T595
Test name
Test status
Simulation time 5194946625 ps
CPU time 61.62 seconds
Started Jul 18 04:48:48 PM PDT 24
Finished Jul 18 04:49:52 PM PDT 24
Peak memory 249044 kb
Host smart-9ba68dcc-cffc-49f1-8af7-83285b098b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26208
94956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2620894956
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.888308797
Short name T36
Test name
Test status
Simulation time 419340943 ps
CPU time 13.7 seconds
Started Jul 18 04:48:50 PM PDT 24
Finished Jul 18 04:49:06 PM PDT 24
Peak memory 257112 kb
Host smart-e21dd4d3-c5b2-4dd1-8641-061abb9d1d87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88830
8797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.888308797
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.38286950
Short name T29
Test name
Test status
Simulation time 355270432 ps
CPU time 22.43 seconds
Started Jul 18 04:48:49 PM PDT 24
Finished Jul 18 04:49:13 PM PDT 24
Peak memory 271288 kb
Host smart-77bc1783-1962-4073-bc6e-75f4359818d8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=38286950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.38286950
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3351525874
Short name T643
Test name
Test status
Simulation time 7913017094 ps
CPU time 51.92 seconds
Started Jul 18 04:48:50 PM PDT 24
Finished Jul 18 04:49:44 PM PDT 24
Peak memory 257232 kb
Host smart-521e4197-c167-4dda-b802-d5041f487dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33515
25874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3351525874
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.4140135445
Short name T77
Test name
Test status
Simulation time 607081722 ps
CPU time 33.42 seconds
Started Jul 18 04:48:51 PM PDT 24
Finished Jul 18 04:49:26 PM PDT 24
Peak memory 256868 kb
Host smart-5cdaf510-6556-4cfa-a0dd-a55ab23192de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41401
35445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4140135445
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1180720093
Short name T430
Test name
Test status
Simulation time 572459315 ps
CPU time 43.93 seconds
Started Jul 18 04:48:52 PM PDT 24
Finished Jul 18 04:49:38 PM PDT 24
Peak memory 257064 kb
Host smart-809a3b5a-c9f6-4883-a49f-42abebb6ad12
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180720093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1180720093
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2847630278
Short name T618
Test name
Test status
Simulation time 18947382412 ps
CPU time 263.18 seconds
Started Jul 18 04:50:13 PM PDT 24
Finished Jul 18 04:54:37 PM PDT 24
Peak memory 252224 kb
Host smart-3a30c708-dd9f-47d0-a80d-f65a7a703577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28476
30278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2847630278
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.133290376
Short name T564
Test name
Test status
Simulation time 217893362 ps
CPU time 17.49 seconds
Started Jul 18 04:50:04 PM PDT 24
Finished Jul 18 04:50:23 PM PDT 24
Peak memory 257352 kb
Host smart-d49cd8fc-3a4a-4036-bc2b-b6e436d88e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13329
0376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.133290376
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.615106089
Short name T250
Test name
Test status
Simulation time 110353483516 ps
CPU time 1123.79 seconds
Started Jul 18 04:50:09 PM PDT 24
Finished Jul 18 05:08:54 PM PDT 24
Peak memory 265416 kb
Host smart-afcb2161-da08-4adf-89c1-52da62e67194
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615106089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.615106089
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3574187993
Short name T3
Test name
Test status
Simulation time 105687959345 ps
CPU time 922.58 seconds
Started Jul 18 04:50:09 PM PDT 24
Finished Jul 18 05:05:33 PM PDT 24
Peak memory 273748 kb
Host smart-4dae4b8a-cade-42e5-b886-48ac1939d102
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574187993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3574187993
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.4123955294
Short name T70
Test name
Test status
Simulation time 23204032083 ps
CPU time 132.84 seconds
Started Jul 18 04:50:03 PM PDT 24
Finished Jul 18 04:52:18 PM PDT 24
Peak memory 249012 kb
Host smart-278f6ba7-7675-42bc-b9a5-48b51cc020dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123955294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.4123955294
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1142094564
Short name T561
Test name
Test status
Simulation time 5225492035 ps
CPU time 77.25 seconds
Started Jul 18 04:50:09 PM PDT 24
Finished Jul 18 04:51:28 PM PDT 24
Peak memory 257116 kb
Host smart-0e3bab2b-03f4-43ee-a05e-5e3ea9c20f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11420
94564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1142094564
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2294420774
Short name T133
Test name
Test status
Simulation time 1659220711 ps
CPU time 56.44 seconds
Started Jul 18 04:50:00 PM PDT 24
Finished Jul 18 04:50:58 PM PDT 24
Peak memory 248300 kb
Host smart-c4ab9d49-c0b2-4630-97e3-7544a9ff414d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22944
20774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2294420774
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1311389388
Short name T80
Test name
Test status
Simulation time 569008974 ps
CPU time 42.27 seconds
Started Jul 18 04:50:03 PM PDT 24
Finished Jul 18 04:50:47 PM PDT 24
Peak memory 256068 kb
Host smart-dd9395b3-49d4-4483-b39f-ad4ad952998a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13113
89388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1311389388
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1137430592
Short name T420
Test name
Test status
Simulation time 987757753 ps
CPU time 21.1 seconds
Started Jul 18 04:50:13 PM PDT 24
Finished Jul 18 04:50:35 PM PDT 24
Peak memory 249344 kb
Host smart-5841f14e-dc9a-47e6-9ab5-78b383bb60be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11374
30592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1137430592
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2914534433
Short name T89
Test name
Test status
Simulation time 162359203833 ps
CPU time 2737.65 seconds
Started Jul 18 04:50:11 PM PDT 24
Finished Jul 18 05:35:50 PM PDT 24
Peak memory 289216 kb
Host smart-29f0ce68-f3de-4492-b130-7b117480f207
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914534433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2914534433
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.4192696523
Short name T210
Test name
Test status
Simulation time 106297626961 ps
CPU time 1706.13 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 05:18:45 PM PDT 24
Peak memory 301844 kb
Host smart-e13a44e0-32a7-400b-9ae8-d8a4a15f3196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192696523 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.4192696523
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3608608782
Short name T147
Test name
Test status
Simulation time 35465657758 ps
CPU time 2164.49 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 05:26:21 PM PDT 24
Peak memory 281692 kb
Host smart-6ebb916b-4566-49da-9068-33a976544bd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608608782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3608608782
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3867556945
Short name T650
Test name
Test status
Simulation time 1774726769 ps
CPU time 137.36 seconds
Started Jul 18 04:50:00 PM PDT 24
Finished Jul 18 04:52:20 PM PDT 24
Peak memory 256484 kb
Host smart-66232872-f737-49d3-b9e5-70587aeafca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38675
56945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3867556945
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.787294818
Short name T491
Test name
Test status
Simulation time 4841142993 ps
CPU time 60.59 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 04:51:20 PM PDT 24
Peak memory 257208 kb
Host smart-cc53baa8-5215-438c-9296-76f8c3d87845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78729
4818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.787294818
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3789940295
Short name T314
Test name
Test status
Simulation time 6201499667 ps
CPU time 631.68 seconds
Started Jul 18 04:50:08 PM PDT 24
Finished Jul 18 05:00:40 PM PDT 24
Peak memory 272800 kb
Host smart-a74ddd24-38a4-40f3-8d0a-c118ce67e0be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789940295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3789940295
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.757092499
Short name T667
Test name
Test status
Simulation time 57164005037 ps
CPU time 2350.84 seconds
Started Jul 18 04:50:08 PM PDT 24
Finished Jul 18 05:29:20 PM PDT 24
Peak memory 289796 kb
Host smart-e6a0c8e3-610c-4272-8b0c-fd1947763530
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757092499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.757092499
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.487348413
Short name T324
Test name
Test status
Simulation time 11316437777 ps
CPU time 152.8 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 04:52:52 PM PDT 24
Peak memory 248824 kb
Host smart-befa358e-7598-4e37-a60a-b61b8d5eb0b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487348413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.487348413
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.500947992
Short name T614
Test name
Test status
Simulation time 1163152587 ps
CPU time 36.54 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 04:50:55 PM PDT 24
Peak memory 248824 kb
Host smart-8e66a3c1-2962-4a6e-a2e5-8b7900763e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50094
7992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.500947992
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3407057856
Short name T103
Test name
Test status
Simulation time 846392610 ps
CPU time 44.03 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 04:51:00 PM PDT 24
Peak memory 248176 kb
Host smart-5f89f2a0-6fb7-4f7f-a747-d022124fea15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34070
57856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3407057856
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1573520812
Short name T46
Test name
Test status
Simulation time 992661107 ps
CPU time 60.02 seconds
Started Jul 18 04:50:09 PM PDT 24
Finished Jul 18 04:51:10 PM PDT 24
Peak memory 248864 kb
Host smart-467963d5-fb70-490f-8a8d-00a654b22dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15735
20812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1573520812
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.815190967
Short name T255
Test name
Test status
Simulation time 1441797416 ps
CPU time 22.39 seconds
Started Jul 18 04:50:08 PM PDT 24
Finished Jul 18 04:50:32 PM PDT 24
Peak memory 255728 kb
Host smart-f5ff5fec-6526-4d51-9f9b-dae88aebcdfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81519
0967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.815190967
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.753701166
Short name T124
Test name
Test status
Simulation time 81320020950 ps
CPU time 2362.01 seconds
Started Jul 18 04:49:58 PM PDT 24
Finished Jul 18 05:29:22 PM PDT 24
Peak memory 289028 kb
Host smart-e9b9da19-219d-4d70-b18f-67e5b95042f4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753701166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.753701166
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4019038182
Short name T465
Test name
Test status
Simulation time 65312148815 ps
CPU time 3764.57 seconds
Started Jul 18 04:49:59 PM PDT 24
Finished Jul 18 05:52:45 PM PDT 24
Peak memory 337952 kb
Host smart-97cbb0c4-ded0-4e53-846e-81024307a0a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019038182 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4019038182
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1146408147
Short name T459
Test name
Test status
Simulation time 88436798837 ps
CPU time 2591.23 seconds
Started Jul 18 04:49:53 PM PDT 24
Finished Jul 18 05:33:05 PM PDT 24
Peak memory 281848 kb
Host smart-efb86af3-cab4-48c1-8298-4f234c2c2e95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146408147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1146408147
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2989751696
Short name T267
Test name
Test status
Simulation time 35879827201 ps
CPU time 143.14 seconds
Started Jul 18 04:49:59 PM PDT 24
Finished Jul 18 04:52:23 PM PDT 24
Peak memory 251556 kb
Host smart-97622155-b18a-428d-a62a-712b132ce886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29897
51696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2989751696
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4157430627
Short name T87
Test name
Test status
Simulation time 3169709480 ps
CPU time 53.5 seconds
Started Jul 18 04:50:03 PM PDT 24
Finished Jul 18 04:50:58 PM PDT 24
Peak memory 248928 kb
Host smart-eeb762d8-1d53-4cb3-b165-90f501565726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41574
30627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4157430627
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1610785311
Short name T356
Test name
Test status
Simulation time 9506203335 ps
CPU time 676.4 seconds
Started Jul 18 04:49:56 PM PDT 24
Finished Jul 18 05:01:14 PM PDT 24
Peak memory 272940 kb
Host smart-80b03361-0eff-4d18-ab99-77fbdcccfcbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610785311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1610785311
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3635469504
Short name T547
Test name
Test status
Simulation time 179903295883 ps
CPU time 1693.86 seconds
Started Jul 18 04:50:05 PM PDT 24
Finished Jul 18 05:18:20 PM PDT 24
Peak memory 272840 kb
Host smart-ba79260e-a57e-46eb-a704-967a8c3b5e8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635469504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3635469504
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2575278311
Short name T685
Test name
Test status
Simulation time 13248678451 ps
CPU time 267.57 seconds
Started Jul 18 04:50:03 PM PDT 24
Finished Jul 18 04:54:32 PM PDT 24
Peak memory 249092 kb
Host smart-8e4f0795-f157-4b64-be97-86860bee57bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575278311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2575278311
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.560471245
Short name T521
Test name
Test status
Simulation time 462035010 ps
CPU time 24.8 seconds
Started Jul 18 04:50:03 PM PDT 24
Finished Jul 18 04:50:29 PM PDT 24
Peak memory 256216 kb
Host smart-d1e3fe9a-d66a-4619-9f4d-b76b591cc6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56047
1245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.560471245
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.270061608
Short name T65
Test name
Test status
Simulation time 4238740823 ps
CPU time 35.75 seconds
Started Jul 18 04:50:00 PM PDT 24
Finished Jul 18 04:50:38 PM PDT 24
Peak memory 256332 kb
Host smart-937573f6-7956-41ed-8b2b-32c6cf07b523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27006
1608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.270061608
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1569149689
Short name T495
Test name
Test status
Simulation time 398658954 ps
CPU time 28.42 seconds
Started Jul 18 04:50:05 PM PDT 24
Finished Jul 18 04:50:34 PM PDT 24
Peak memory 248924 kb
Host smart-e6fb40f2-12e7-4134-8cb0-b219313eec71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15691
49689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1569149689
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3538673299
Short name T371
Test name
Test status
Simulation time 147548138 ps
CPU time 3.86 seconds
Started Jul 18 04:50:02 PM PDT 24
Finished Jul 18 04:50:07 PM PDT 24
Peak memory 251060 kb
Host smart-cdd206e3-c826-43d4-911a-21cb96ac0d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35386
73299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3538673299
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2523376034
Short name T52
Test name
Test status
Simulation time 113016973802 ps
CPU time 2005.88 seconds
Started Jul 18 04:50:05 PM PDT 24
Finished Jul 18 05:23:33 PM PDT 24
Peak memory 289952 kb
Host smart-74925e70-529a-48ad-a586-c15523ae930f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523376034 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2523376034
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2185935498
Short name T62
Test name
Test status
Simulation time 10999242708 ps
CPU time 1132.28 seconds
Started Jul 18 04:50:12 PM PDT 24
Finished Jul 18 05:09:05 PM PDT 24
Peak memory 284688 kb
Host smart-48ae94f2-fde6-4003-94e6-2a6401abc3f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185935498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2185935498
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2445561368
Short name T431
Test name
Test status
Simulation time 1337875870 ps
CPU time 101.18 seconds
Started Jul 18 04:50:09 PM PDT 24
Finished Jul 18 04:51:52 PM PDT 24
Peak memory 256232 kb
Host smart-4ca46df1-b961-41d3-b1f7-147165b40ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24455
61368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2445561368
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1491497837
Short name T675
Test name
Test status
Simulation time 162371090 ps
CPU time 15.89 seconds
Started Jul 18 04:50:12 PM PDT 24
Finished Jul 18 04:50:28 PM PDT 24
Peak memory 248844 kb
Host smart-d96a6b72-b58d-4c13-bae0-5ca36d2fccbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14914
97837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1491497837
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3122957637
Short name T574
Test name
Test status
Simulation time 22211930856 ps
CPU time 787.8 seconds
Started Jul 18 04:50:05 PM PDT 24
Finished Jul 18 05:03:15 PM PDT 24
Peak memory 272908 kb
Host smart-260671b8-d1fc-47d8-94f1-d740e7c88319
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122957637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3122957637
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.809512219
Short name T61
Test name
Test status
Simulation time 74194822633 ps
CPU time 2203.73 seconds
Started Jul 18 04:50:06 PM PDT 24
Finished Jul 18 05:26:51 PM PDT 24
Peak memory 283524 kb
Host smart-dcb98296-be7b-4d36-bbf4-9341d5d1b192
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809512219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.809512219
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2013713865
Short name T325
Test name
Test status
Simulation time 13726760575 ps
CPU time 303.76 seconds
Started Jul 18 04:49:59 PM PDT 24
Finished Jul 18 04:55:05 PM PDT 24
Peak memory 256032 kb
Host smart-3241513b-29bc-48df-83d1-1c641dbc6c16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013713865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2013713865
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3701052794
Short name T372
Test name
Test status
Simulation time 284656925 ps
CPU time 15.48 seconds
Started Jul 18 04:50:02 PM PDT 24
Finished Jul 18 04:50:19 PM PDT 24
Peak memory 248968 kb
Host smart-2014cb1a-25bf-437c-8e98-097f6b3431a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37010
52794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3701052794
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1274832337
Short name T700
Test name
Test status
Simulation time 1032038001 ps
CPU time 31.44 seconds
Started Jul 18 04:50:06 PM PDT 24
Finished Jul 18 04:50:39 PM PDT 24
Peak memory 248088 kb
Host smart-a0d808fb-ad9b-4c25-aa33-1320afc3e29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12748
32337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1274832337
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3740325632
Short name T42
Test name
Test status
Simulation time 4546763153 ps
CPU time 69.14 seconds
Started Jul 18 04:50:08 PM PDT 24
Finished Jul 18 04:51:18 PM PDT 24
Peak memory 256632 kb
Host smart-18222cbb-8c5f-4aed-a43d-2f8fd1604149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37403
25632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3740325632
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2645402977
Short name T563
Test name
Test status
Simulation time 1364046745 ps
CPU time 29.31 seconds
Started Jul 18 04:50:05 PM PDT 24
Finished Jul 18 04:50:35 PM PDT 24
Peak memory 257028 kb
Host smart-5a2a141c-4769-4537-8934-f560fdea13ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26454
02977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2645402977
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.77447007
Short name T565
Test name
Test status
Simulation time 8216480511 ps
CPU time 85.69 seconds
Started Jul 18 04:50:12 PM PDT 24
Finished Jul 18 04:51:38 PM PDT 24
Peak memory 257204 kb
Host smart-356211b6-bb35-4c25-86cd-490352d40270
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77447007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_hand
ler_stress_all.77447007
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.143748710
Short name T699
Test name
Test status
Simulation time 52891795659 ps
CPU time 1800.86 seconds
Started Jul 18 04:50:04 PM PDT 24
Finished Jul 18 05:20:06 PM PDT 24
Peak memory 305476 kb
Host smart-74482035-0359-4f0a-b963-7fffc9f60511
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143748710 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.143748710
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1779373164
Short name T611
Test name
Test status
Simulation time 2145246417 ps
CPU time 136.62 seconds
Started Jul 18 04:50:03 PM PDT 24
Finished Jul 18 04:52:21 PM PDT 24
Peak memory 256652 kb
Host smart-19ae5629-8b31-475d-a7db-60c356dc2206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17793
73164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1779373164
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2759066945
Short name T559
Test name
Test status
Simulation time 489759523 ps
CPU time 25.85 seconds
Started Jul 18 04:50:13 PM PDT 24
Finished Jul 18 04:50:40 PM PDT 24
Peak memory 248832 kb
Host smart-bca7a6c3-f3a2-42dc-97b9-bc4ef2b6584f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27590
66945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2759066945
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2075580966
Short name T628
Test name
Test status
Simulation time 61351939356 ps
CPU time 1140.55 seconds
Started Jul 18 04:50:13 PM PDT 24
Finished Jul 18 05:09:14 PM PDT 24
Peak memory 272696 kb
Host smart-792ab30d-8acf-4eb4-91df-e40fea4ddad9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075580966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2075580966
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2857073007
Short name T112
Test name
Test status
Simulation time 25884073665 ps
CPU time 1094.46 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 05:08:32 PM PDT 24
Peak memory 272992 kb
Host smart-db8de100-90fa-4715-8f0b-12b10d5175cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857073007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2857073007
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2609793550
Short name T583
Test name
Test status
Simulation time 3813773348 ps
CPU time 77.88 seconds
Started Jul 18 04:50:12 PM PDT 24
Finished Jul 18 04:51:31 PM PDT 24
Peak memory 253632 kb
Host smart-ef9984f5-a813-4df6-8934-db175b988ef0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609793550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2609793550
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2121056918
Short name T451
Test name
Test status
Simulation time 1087583087 ps
CPU time 19.13 seconds
Started Jul 18 04:50:08 PM PDT 24
Finished Jul 18 04:50:28 PM PDT 24
Peak memory 248892 kb
Host smart-50e37e9b-0d4a-4ca6-a682-55f74425b62d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21210
56918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2121056918
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3120137593
Short name T122
Test name
Test status
Simulation time 212506728 ps
CPU time 14.06 seconds
Started Jul 18 04:50:09 PM PDT 24
Finished Jul 18 04:50:25 PM PDT 24
Peak memory 248884 kb
Host smart-d5c96058-d315-4c6e-8a01-44e523a9c887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31201
37593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3120137593
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.44010154
Short name T136
Test name
Test status
Simulation time 638343465 ps
CPU time 9.6 seconds
Started Jul 18 04:50:03 PM PDT 24
Finished Jul 18 04:50:14 PM PDT 24
Peak memory 251080 kb
Host smart-dad1fe71-9922-4e58-8f01-4e0fc6c2dc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44010
154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.44010154
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.658694518
Short name T569
Test name
Test status
Simulation time 5880860964 ps
CPU time 751.48 seconds
Started Jul 18 04:50:24 PM PDT 24
Finished Jul 18 05:02:57 PM PDT 24
Peak memory 265748 kb
Host smart-1be80d62-f87b-4f10-a633-46b64f9c60d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658694518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.658694518
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.538548789
Short name T493
Test name
Test status
Simulation time 2030316853 ps
CPU time 86.35 seconds
Started Jul 18 04:50:19 PM PDT 24
Finished Jul 18 04:51:46 PM PDT 24
Peak memory 256608 kb
Host smart-dcd80b36-720d-4922-a98e-04704f71893f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53854
8789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.538548789
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3527780356
Short name T653
Test name
Test status
Simulation time 784721179 ps
CPU time 47.11 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 04:51:06 PM PDT 24
Peak memory 257116 kb
Host smart-419df925-1d76-49fc-a22c-375d2222eb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35277
80356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3527780356
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1303092700
Short name T351
Test name
Test status
Simulation time 181600153620 ps
CPU time 1802.04 seconds
Started Jul 18 04:50:19 PM PDT 24
Finished Jul 18 05:20:22 PM PDT 24
Peak memory 273264 kb
Host smart-8377575c-17ab-4783-82e8-d617ec106a62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303092700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1303092700
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1995979079
Short name T380
Test name
Test status
Simulation time 172233632621 ps
CPU time 2741.29 seconds
Started Jul 18 04:50:25 PM PDT 24
Finished Jul 18 05:36:07 PM PDT 24
Peak memory 287464 kb
Host smart-a2a3012e-b22a-4c33-ab63-346e9f97ec81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995979079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1995979079
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2527640506
Short name T35
Test name
Test status
Simulation time 1594014510 ps
CPU time 24.1 seconds
Started Jul 18 04:50:30 PM PDT 24
Finished Jul 18 04:50:54 PM PDT 24
Peak memory 248832 kb
Host smart-463fb259-c1c0-467c-9caf-13547325ab2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25276
40506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2527640506
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2794309864
Short name T568
Test name
Test status
Simulation time 1053092083 ps
CPU time 28.25 seconds
Started Jul 18 04:50:14 PM PDT 24
Finished Jul 18 04:50:43 PM PDT 24
Peak memory 248200 kb
Host smart-b1b5f36d-1667-4470-913f-4f1ee35258de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27943
09864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2794309864
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2511963078
Short name T311
Test name
Test status
Simulation time 1106453277 ps
CPU time 36.59 seconds
Started Jul 18 04:50:30 PM PDT 24
Finished Jul 18 04:51:07 PM PDT 24
Peak memory 256628 kb
Host smart-998b1121-556b-480b-aef5-5bab2052651f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25119
63078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2511963078
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1749245803
Short name T377
Test name
Test status
Simulation time 4332833757 ps
CPU time 33.94 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 04:50:51 PM PDT 24
Peak memory 256296 kb
Host smart-8cefaecb-ec07-4bd3-beb2-69e85da28d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17492
45803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1749245803
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3272260389
Short name T270
Test name
Test status
Simulation time 6408484893 ps
CPU time 155.19 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 04:52:53 PM PDT 24
Peak memory 257228 kb
Host smart-7d25bacc-508e-40d0-81cd-d33921ff03d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272260389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3272260389
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1424969173
Short name T113
Test name
Test status
Simulation time 84408668433 ps
CPU time 2557.24 seconds
Started Jul 18 04:50:24 PM PDT 24
Finished Jul 18 05:33:02 PM PDT 24
Peak memory 289100 kb
Host smart-3b4770cb-e5be-4ba5-8910-77b10bf406a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424969173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1424969173
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.2443034214
Short name T416
Test name
Test status
Simulation time 2902985612 ps
CPU time 196.2 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 04:53:34 PM PDT 24
Peak memory 251036 kb
Host smart-0b440103-d07c-4981-9e09-39f3b897f9f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24430
34214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.2443034214
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.4111606783
Short name T90
Test name
Test status
Simulation time 1352282622 ps
CPU time 21.36 seconds
Started Jul 18 04:50:29 PM PDT 24
Finished Jul 18 04:50:51 PM PDT 24
Peak memory 248832 kb
Host smart-a6cb427a-b721-4275-b224-da575eb436ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41116
06783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.4111606783
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.243712704
Short name T353
Test name
Test status
Simulation time 19802746000 ps
CPU time 922.94 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 05:05:41 PM PDT 24
Peak memory 273004 kb
Host smart-8782cf51-3c7d-4c7e-9eea-542056480755
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243712704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.243712704
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1773185963
Short name T504
Test name
Test status
Simulation time 77313487790 ps
CPU time 2524.07 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 05:32:21 PM PDT 24
Peak memory 289988 kb
Host smart-22d5aed2-0da8-4224-b115-25d4418381c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773185963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1773185963
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.636071543
Short name T340
Test name
Test status
Simulation time 28186315917 ps
CPU time 332.57 seconds
Started Jul 18 04:50:30 PM PDT 24
Finished Jul 18 04:56:04 PM PDT 24
Peak memory 248724 kb
Host smart-36cc0599-01fc-4616-a492-ed9ae38c9c89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636071543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.636071543
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2344761301
Short name T554
Test name
Test status
Simulation time 3678002102 ps
CPU time 58.9 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 04:51:15 PM PDT 24
Peak memory 248864 kb
Host smart-a3bbc235-904f-4759-8d31-e8ee6e100e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23447
61301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2344761301
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.432520184
Short name T144
Test name
Test status
Simulation time 273114790 ps
CPU time 28.48 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 04:50:46 PM PDT 24
Peak memory 255460 kb
Host smart-4045655f-808b-4a03-bd84-6a131088c872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43252
0184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.432520184
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3178561944
Short name T461
Test name
Test status
Simulation time 1104196917 ps
CPU time 21.56 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 04:50:40 PM PDT 24
Peak memory 248832 kb
Host smart-deaa0b2e-3dcb-44a4-9ed9-d2e7834bc9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31785
61944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3178561944
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2965056184
Short name T473
Test name
Test status
Simulation time 202604881 ps
CPU time 13.65 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 04:50:31 PM PDT 24
Peak memory 248820 kb
Host smart-da1a376a-4405-4c84-bf88-bb1cfcd370b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29650
56184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2965056184
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3559493029
Short name T101
Test name
Test status
Simulation time 19228462745 ps
CPU time 576.2 seconds
Started Jul 18 04:50:31 PM PDT 24
Finished Jul 18 05:00:08 PM PDT 24
Peak memory 265340 kb
Host smart-b32ec279-b783-4934-9e40-9efa244319f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559493029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3559493029
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.93394289
Short name T114
Test name
Test status
Simulation time 14354880233 ps
CPU time 732.6 seconds
Started Jul 18 04:50:17 PM PDT 24
Finished Jul 18 05:02:32 PM PDT 24
Peak memory 273288 kb
Host smart-0705d9e3-e957-4030-9fe0-51e6630dd9f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93394289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.93394289
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1959075211
Short name T422
Test name
Test status
Simulation time 9807565993 ps
CPU time 152.54 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 04:52:49 PM PDT 24
Peak memory 257216 kb
Host smart-d13c61b5-32a5-40f2-be1b-aecb337c45cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19590
75211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1959075211
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1785213913
Short name T86
Test name
Test status
Simulation time 605974220 ps
CPU time 29.35 seconds
Started Jul 18 04:50:17 PM PDT 24
Finished Jul 18 04:50:48 PM PDT 24
Peak memory 256812 kb
Host smart-fadcf4ed-7f22-43cd-b833-6190e807f718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17852
13913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1785213913
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3410338579
Short name T15
Test name
Test status
Simulation time 8915441371 ps
CPU time 781.39 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 05:03:18 PM PDT 24
Peak memory 272524 kb
Host smart-c1e0b9e7-da8d-4ea2-9e3d-dde7de155eb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410338579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3410338579
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2853942361
Short name T656
Test name
Test status
Simulation time 12643099274 ps
CPU time 522.19 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 04:59:00 PM PDT 24
Peak memory 255736 kb
Host smart-d88c6097-fa67-420a-9d28-6c0918f3b63f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853942361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2853942361
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.4241879776
Short name T501
Test name
Test status
Simulation time 195793808 ps
CPU time 5.49 seconds
Started Jul 18 04:50:25 PM PDT 24
Finished Jul 18 04:50:31 PM PDT 24
Peak memory 249208 kb
Host smart-d89896ff-6cec-49cd-b94b-652c3da47045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42418
79776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.4241879776
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3924159673
Short name T450
Test name
Test status
Simulation time 824632972 ps
CPU time 57.97 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 04:51:16 PM PDT 24
Peak memory 248920 kb
Host smart-987b82ff-be78-4649-bf3b-693ca4553047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39241
59673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3924159673
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3958530023
Short name T257
Test name
Test status
Simulation time 1091394539 ps
CPU time 18.89 seconds
Started Jul 18 04:50:18 PM PDT 24
Finished Jul 18 04:50:38 PM PDT 24
Peak memory 248512 kb
Host smart-a55ee7f0-aa02-4551-b83d-b1a50b2a9c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
30023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3958530023
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.793899747
Short name T488
Test name
Test status
Simulation time 226917844 ps
CPU time 9.51 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 04:50:26 PM PDT 24
Peak memory 251928 kb
Host smart-cde7d606-f9b7-40e9-8e8f-b4f7b7660d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79389
9747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.793899747
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2753174683
Short name T115
Test name
Test status
Simulation time 15237692679 ps
CPU time 1683.48 seconds
Started Jul 18 04:50:19 PM PDT 24
Finished Jul 18 05:18:24 PM PDT 24
Peak memory 290008 kb
Host smart-f0b12a59-a4ae-4b2d-bfef-632fef78060e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753174683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2753174683
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3291754176
Short name T105
Test name
Test status
Simulation time 127950806913 ps
CPU time 1128.28 seconds
Started Jul 18 04:50:30 PM PDT 24
Finished Jul 18 05:09:19 PM PDT 24
Peak memory 285580 kb
Host smart-a5c29f31-fd8f-46fe-af04-03698b01fadf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291754176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3291754176
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.4171512754
Short name T630
Test name
Test status
Simulation time 10189975498 ps
CPU time 159.21 seconds
Started Jul 18 04:50:23 PM PDT 24
Finished Jul 18 04:53:03 PM PDT 24
Peak memory 256812 kb
Host smart-f0b6ee09-07d2-430e-93be-9ea6e9274b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41715
12754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.4171512754
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2458120197
Short name T680
Test name
Test status
Simulation time 1788710409 ps
CPU time 7.51 seconds
Started Jul 18 04:50:24 PM PDT 24
Finished Jul 18 04:50:32 PM PDT 24
Peak memory 253112 kb
Host smart-a7a053bd-3873-416a-875f-ba16cb2dd772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24581
20197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2458120197
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1836514121
Short name T8
Test name
Test status
Simulation time 26709563802 ps
CPU time 1425.85 seconds
Started Jul 18 04:50:31 PM PDT 24
Finished Jul 18 05:14:17 PM PDT 24
Peak memory 281772 kb
Host smart-49bd9cba-1ad0-47f3-b7bc-0650902d7c06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836514121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1836514121
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.656847751
Short name T81
Test name
Test status
Simulation time 75548002934 ps
CPU time 1316.87 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 05:12:45 PM PDT 24
Peak memory 273028 kb
Host smart-c95250ca-61b1-45a0-a3a3-24c741ef2604
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656847751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.656847751
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3534053073
Short name T462
Test name
Test status
Simulation time 6799007400 ps
CPU time 285.24 seconds
Started Jul 18 04:50:16 PM PDT 24
Finished Jul 18 04:55:03 PM PDT 24
Peak memory 255772 kb
Host smart-9d0660a5-fca0-42f7-8e50-18ad8e5f434c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534053073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3534053073
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2245153518
Short name T379
Test name
Test status
Simulation time 81467505 ps
CPU time 8.39 seconds
Started Jul 18 04:50:17 PM PDT 24
Finished Jul 18 04:50:28 PM PDT 24
Peak memory 248988 kb
Host smart-64064936-d89d-4c95-a5d4-c8a5c0848181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22451
53518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2245153518
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2388141324
Short name T129
Test name
Test status
Simulation time 105927622 ps
CPU time 8.32 seconds
Started Jul 18 04:50:17 PM PDT 24
Finished Jul 18 04:50:28 PM PDT 24
Peak memory 248992 kb
Host smart-34a2ca35-5e49-4c74-b970-147a1fc5de55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23881
41324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2388141324
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.866417291
Short name T291
Test name
Test status
Simulation time 2974971022 ps
CPU time 39.37 seconds
Started Jul 18 04:50:15 PM PDT 24
Finished Jul 18 04:50:56 PM PDT 24
Peak memory 256200 kb
Host smart-1134b661-0877-4f2e-bf9a-8afdaf38d082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86641
7291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.866417291
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1634272801
Short name T376
Test name
Test status
Simulation time 370283474 ps
CPU time 30.47 seconds
Started Jul 18 04:50:30 PM PDT 24
Finished Jul 18 04:51:01 PM PDT 24
Peak memory 256004 kb
Host smart-af29a12b-a759-4e87-8826-222b548b8545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16342
72801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1634272801
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2984298053
Short name T411
Test name
Test status
Simulation time 33157036769 ps
CPU time 788.45 seconds
Started Jul 18 04:50:44 PM PDT 24
Finished Jul 18 05:03:53 PM PDT 24
Peak memory 273404 kb
Host smart-6a3c9f3d-02df-4a06-8e19-cb142f03e37a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984298053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2984298053
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.438068248
Short name T562
Test name
Test status
Simulation time 139865146983 ps
CPU time 2264.71 seconds
Started Jul 18 04:50:48 PM PDT 24
Finished Jul 18 05:28:35 PM PDT 24
Peak memory 289188 kb
Host smart-057950d6-cd05-46f0-8443-f948f815b071
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438068248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.438068248
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2032182032
Short name T63
Test name
Test status
Simulation time 5901916736 ps
CPU time 237.35 seconds
Started Jul 18 04:50:44 PM PDT 24
Finished Jul 18 04:54:42 PM PDT 24
Peak memory 257232 kb
Host smart-a09af577-128f-4617-8146-60350fc62f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20321
82032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2032182032
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2217295851
Short name T603
Test name
Test status
Simulation time 3365620044 ps
CPU time 50.34 seconds
Started Jul 18 04:50:44 PM PDT 24
Finished Jul 18 04:51:36 PM PDT 24
Peak memory 256944 kb
Host smart-33c82f84-f82f-4ac5-81be-a31b4d741fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22172
95851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2217295851
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1667723275
Short name T37
Test name
Test status
Simulation time 11789124198 ps
CPU time 1010.46 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 05:07:39 PM PDT 24
Peak memory 271848 kb
Host smart-acb40cea-f604-4ab6-87de-a507a25a2091
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667723275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1667723275
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2269997075
Short name T515
Test name
Test status
Simulation time 13442476388 ps
CPU time 544.12 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 04:59:52 PM PDT 24
Peak memory 249056 kb
Host smart-f91838c6-305b-4310-8e8f-9e3f6704a7f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269997075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2269997075
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1268529926
Short name T670
Test name
Test status
Simulation time 3850202311 ps
CPU time 49.45 seconds
Started Jul 18 04:50:44 PM PDT 24
Finished Jul 18 04:51:35 PM PDT 24
Peak memory 256500 kb
Host smart-99334bdf-d26c-4e08-874f-b39f744e9884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12685
29926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1268529926
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3401753493
Short name T106
Test name
Test status
Simulation time 1659880185 ps
CPU time 54.55 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 04:51:43 PM PDT 24
Peak memory 248752 kb
Host smart-31c98819-dfa8-4c08-8c2a-a10b88b499ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34017
53493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3401753493
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1073958722
Short name T654
Test name
Test status
Simulation time 133016774 ps
CPU time 10.08 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 04:50:57 PM PDT 24
Peak memory 248980 kb
Host smart-3a078543-ec7a-4d1c-851e-f133101c5ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10739
58722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1073958722
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1150317203
Short name T374
Test name
Test status
Simulation time 117234474 ps
CPU time 5.56 seconds
Started Jul 18 04:50:44 PM PDT 24
Finished Jul 18 04:50:51 PM PDT 24
Peak memory 249112 kb
Host smart-795d953a-4b3c-49ae-ad5f-019c5a5d3806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11503
17203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1150317203
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.679502811
Short name T215
Test name
Test status
Simulation time 392787264 ps
CPU time 7.6 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 04:50:56 PM PDT 24
Peak memory 251876 kb
Host smart-9f98f445-a1c8-40d0-8466-267c65c582c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679502811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.679502811
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3468344505
Short name T596
Test name
Test status
Simulation time 95071253491 ps
CPU time 5109 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 06:15:59 PM PDT 24
Peak memory 347408 kb
Host smart-03de701a-c26a-4f2d-861f-f81c3b584280
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468344505 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3468344505
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.664923046
Short name T235
Test name
Test status
Simulation time 60388965 ps
CPU time 3.14 seconds
Started Jul 18 04:49:12 PM PDT 24
Finished Jul 18 04:49:17 PM PDT 24
Peak memory 249144 kb
Host smart-a9748a0f-4f90-41a7-a03b-fdef5aa02ec9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=664923046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.664923046
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.486976583
Short name T549
Test name
Test status
Simulation time 29481784215 ps
CPU time 710.93 seconds
Started Jul 18 04:49:11 PM PDT 24
Finished Jul 18 05:01:03 PM PDT 24
Peak memory 272676 kb
Host smart-c31ed32a-3293-4fa4-9ac0-aa833e317123
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486976583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.486976583
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2712572075
Short name T638
Test name
Test status
Simulation time 242198199 ps
CPU time 12.7 seconds
Started Jul 18 04:49:18 PM PDT 24
Finished Jul 18 04:49:32 PM PDT 24
Peak memory 248884 kb
Host smart-2af85968-192a-44b7-a0e4-92aeb9e7b7a5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2712572075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2712572075
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1015736688
Short name T44
Test name
Test status
Simulation time 10653822008 ps
CPU time 162.29 seconds
Started Jul 18 04:49:10 PM PDT 24
Finished Jul 18 04:51:54 PM PDT 24
Peak memory 256524 kb
Host smart-72e8a9b4-f9ad-4ef4-ac38-718f972a154e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10157
36688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1015736688
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2423780306
Short name T477
Test name
Test status
Simulation time 1668756714 ps
CPU time 27.5 seconds
Started Jul 18 04:49:16 PM PDT 24
Finished Jul 18 04:49:45 PM PDT 24
Peak memory 248444 kb
Host smart-59666ee3-d389-4a97-90f2-ee28022ec6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24237
80306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2423780306
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2091054088
Short name T580
Test name
Test status
Simulation time 254343986457 ps
CPU time 1899.36 seconds
Started Jul 18 04:49:11 PM PDT 24
Finished Jul 18 05:20:51 PM PDT 24
Peak memory 268540 kb
Host smart-fe0ca9e4-888c-405c-b287-8f38145fe752
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091054088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2091054088
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2451969253
Short name T378
Test name
Test status
Simulation time 52863072463 ps
CPU time 1205.96 seconds
Started Jul 18 04:49:16 PM PDT 24
Finished Jul 18 05:09:24 PM PDT 24
Peak memory 281720 kb
Host smart-ef7329f2-a42a-48cb-bee4-3c9da232adb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451969253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2451969253
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3774474120
Short name T333
Test name
Test status
Simulation time 11572319111 ps
CPU time 481 seconds
Started Jul 18 04:49:12 PM PDT 24
Finished Jul 18 04:57:14 PM PDT 24
Peak memory 249080 kb
Host smart-c06b02f0-c08a-4312-8767-6317f82e2a75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774474120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3774474120
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.999748291
Short name T639
Test name
Test status
Simulation time 4079484709 ps
CPU time 50.87 seconds
Started Jul 18 04:49:12 PM PDT 24
Finished Jul 18 04:50:05 PM PDT 24
Peak memory 256332 kb
Host smart-2b6094b7-fc26-4a42-8a88-67636bfbc158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99974
8291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.999748291
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2665459734
Short name T313
Test name
Test status
Simulation time 243952017 ps
CPU time 10.55 seconds
Started Jul 18 04:49:13 PM PDT 24
Finished Jul 18 04:49:25 PM PDT 24
Peak memory 256852 kb
Host smart-0c3f66d2-1b7c-486b-ad18-37f4e609cd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26654
59734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2665459734
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2361971195
Short name T30
Test name
Test status
Simulation time 469288129 ps
CPU time 25.88 seconds
Started Jul 18 04:49:10 PM PDT 24
Finished Jul 18 04:49:37 PM PDT 24
Peak memory 267896 kb
Host smart-a6189f73-66f2-47b8-b8be-801ff1a19eef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2361971195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2361971195
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3859150685
Short name T145
Test name
Test status
Simulation time 299232641 ps
CPU time 19.44 seconds
Started Jul 18 04:49:10 PM PDT 24
Finished Jul 18 04:49:31 PM PDT 24
Peak memory 256400 kb
Host smart-626a7120-92dd-437a-b17e-006b7d421e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38591
50685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3859150685
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1038683814
Short name T382
Test name
Test status
Simulation time 946786776 ps
CPU time 54.26 seconds
Started Jul 18 04:48:50 PM PDT 24
Finished Jul 18 04:49:46 PM PDT 24
Peak memory 256832 kb
Host smart-b4e85fa3-600e-4885-adc2-85baae9c6ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10386
83814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1038683814
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2948303796
Short name T272
Test name
Test status
Simulation time 31093854369 ps
CPU time 1369.8 seconds
Started Jul 18 04:49:10 PM PDT 24
Finished Jul 18 05:12:02 PM PDT 24
Peak memory 289732 kb
Host smart-040fc579-95d3-40c8-94f3-508c7b529928
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948303796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2948303796
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2227731675
Short name T310
Test name
Test status
Simulation time 550036446013 ps
CPU time 1863.63 seconds
Started Jul 18 04:50:50 PM PDT 24
Finished Jul 18 05:21:56 PM PDT 24
Peak memory 282860 kb
Host smart-be7a7b22-0bc2-4888-89cf-b418de8a14a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227731675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2227731675
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3314210020
Short name T696
Test name
Test status
Simulation time 1811181729 ps
CPU time 98.49 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 04:52:28 PM PDT 24
Peak memory 257068 kb
Host smart-f1156b7a-e4dc-42c4-98a0-562092979b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33142
10020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3314210020
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2713434550
Short name T84
Test name
Test status
Simulation time 153476332 ps
CPU time 7.45 seconds
Started Jul 18 04:50:44 PM PDT 24
Finished Jul 18 04:50:54 PM PDT 24
Peak memory 248320 kb
Host smart-60525da8-7248-467e-ae63-02b8f7aff933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27134
34550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2713434550
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.391487173
Short name T334
Test name
Test status
Simulation time 147898298902 ps
CPU time 2309.16 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 05:29:19 PM PDT 24
Peak memory 289776 kb
Host smart-e1f81687-5099-4700-98b3-230ed715379e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391487173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.391487173
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1766064015
Short name T398
Test name
Test status
Simulation time 25157094283 ps
CPU time 1474.97 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 05:15:25 PM PDT 24
Peak memory 289920 kb
Host smart-435dcf0a-6d89-496c-a577-ac70b3d9bd25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766064015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1766064015
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3033545650
Short name T338
Test name
Test status
Simulation time 8207676197 ps
CPU time 87.05 seconds
Started Jul 18 04:50:48 PM PDT 24
Finished Jul 18 04:52:18 PM PDT 24
Peak memory 253764 kb
Host smart-cd556db9-3f56-4c17-98ac-ec4c8f9859c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033545650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3033545650
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4081728548
Short name T440
Test name
Test status
Simulation time 1653661885 ps
CPU time 15.8 seconds
Started Jul 18 04:50:49 PM PDT 24
Finished Jul 18 04:51:07 PM PDT 24
Peak memory 248948 kb
Host smart-1bb8cab2-179f-4a4d-97f7-fd40334f7ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40817
28548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4081728548
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.4263832693
Short name T497
Test name
Test status
Simulation time 261324164 ps
CPU time 24.02 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 04:51:11 PM PDT 24
Peak memory 248180 kb
Host smart-a1faa21c-b414-468f-91ae-ac54762bcba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42638
32693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.4263832693
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.2741308331
Short name T274
Test name
Test status
Simulation time 181731410 ps
CPU time 21.03 seconds
Started Jul 18 04:50:47 PM PDT 24
Finished Jul 18 04:51:11 PM PDT 24
Peak memory 248536 kb
Host smart-ed17ac6b-c69d-4d56-a655-c19457225e1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27413
08331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2741308331
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2197837443
Short name T498
Test name
Test status
Simulation time 846102704 ps
CPU time 46.72 seconds
Started Jul 18 04:50:47 PM PDT 24
Finished Jul 18 04:51:37 PM PDT 24
Peak memory 257048 kb
Host smart-6e684d4f-4c54-4623-8309-5b13b7b85c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21978
37443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2197837443
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.7755488
Short name T47
Test name
Test status
Simulation time 37049255700 ps
CPU time 2291.8 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 05:29:01 PM PDT 24
Peak memory 289976 kb
Host smart-f3e0e3cd-3038-47ef-8c1a-e026224d2895
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7755488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handl
er_stress_all.7755488
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2839408419
Short name T50
Test name
Test status
Simulation time 36588667608 ps
CPU time 3712.98 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 05:52:41 PM PDT 24
Peak memory 321944 kb
Host smart-5dff57c1-cf59-479c-8330-0c82856fc04f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839408419 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2839408419
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2150202081
Short name T403
Test name
Test status
Simulation time 44708062237 ps
CPU time 2505.21 seconds
Started Jul 18 04:50:44 PM PDT 24
Finished Jul 18 05:32:31 PM PDT 24
Peak memory 285692 kb
Host smart-a906daf0-62c6-4957-bef1-a01c15955306
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150202081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2150202081
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.546296843
Short name T266
Test name
Test status
Simulation time 3375177445 ps
CPU time 138.99 seconds
Started Jul 18 04:50:49 PM PDT 24
Finished Jul 18 04:53:11 PM PDT 24
Peak memory 252124 kb
Host smart-9b92d787-2d9e-40fa-904c-d9bf26a92618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54629
6843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.546296843
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.4052840602
Short name T457
Test name
Test status
Simulation time 180755686 ps
CPU time 10.51 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 04:50:59 PM PDT 24
Peak memory 248296 kb
Host smart-ad5942e2-b830-41e0-b8df-655b9ba9499e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40528
40602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4052840602
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3759826863
Short name T331
Test name
Test status
Simulation time 21303262579 ps
CPU time 1355.04 seconds
Started Jul 18 04:50:44 PM PDT 24
Finished Jul 18 05:13:19 PM PDT 24
Peak memory 272932 kb
Host smart-ce6a6bf6-b0de-4e76-8b03-6ecd65cd851f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759826863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3759826863
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1218314196
Short name T16
Test name
Test status
Simulation time 21754588692 ps
CPU time 1128.81 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 05:09:38 PM PDT 24
Peak memory 287240 kb
Host smart-d9d3ae9b-8b63-4302-b10d-1640cdbc89c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218314196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1218314196
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3647590426
Short name T319
Test name
Test status
Simulation time 8242205907 ps
CPU time 349.98 seconds
Started Jul 18 04:50:47 PM PDT 24
Finished Jul 18 04:56:40 PM PDT 24
Peak memory 256420 kb
Host smart-2446aa3d-0dd9-467f-952a-5fb9eeac9120
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647590426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3647590426
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2981340898
Short name T492
Test name
Test status
Simulation time 1153665067 ps
CPU time 70.5 seconds
Started Jul 18 04:50:47 PM PDT 24
Finished Jul 18 04:52:01 PM PDT 24
Peak memory 256100 kb
Host smart-04d1ba6b-3630-421b-b45d-ec5778e714a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29813
40898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2981340898
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1294977201
Short name T41
Test name
Test status
Simulation time 7252972985 ps
CPU time 28.75 seconds
Started Jul 18 04:50:44 PM PDT 24
Finished Jul 18 04:51:15 PM PDT 24
Peak memory 257000 kb
Host smart-71e42be4-dcc3-4659-b435-062b45e83aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12949
77201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1294977201
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.4124122377
Short name T432
Test name
Test status
Simulation time 1229911440 ps
CPU time 38.25 seconds
Started Jul 18 04:50:44 PM PDT 24
Finished Jul 18 04:51:23 PM PDT 24
Peak memory 256236 kb
Host smart-38897dda-46bf-4115-995a-fd5c824bad97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41241
22377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.4124122377
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.399275517
Short name T475
Test name
Test status
Simulation time 34470654202 ps
CPU time 2012.02 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 05:24:21 PM PDT 24
Peak memory 289972 kb
Host smart-fbff17b9-3f05-4bb3-a772-43227c024982
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399275517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.399275517
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.753582298
Short name T227
Test name
Test status
Simulation time 106867534849 ps
CPU time 9629.27 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 07:31:17 PM PDT 24
Peak memory 420292 kb
Host smart-f05564df-2d80-42c7-ab69-e0c311cf2523
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753582298 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.753582298
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2362081536
Short name T599
Test name
Test status
Simulation time 27295189154 ps
CPU time 742.94 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 05:03:10 PM PDT 24
Peak memory 265448 kb
Host smart-9bb0d3e6-0079-4a97-a03a-6120db75d39b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362081536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2362081536
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1460989800
Short name T265
Test name
Test status
Simulation time 4812506734 ps
CPU time 240.59 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 04:54:47 PM PDT 24
Peak memory 257224 kb
Host smart-bae2783d-ce15-4a96-90dd-11153f740786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14609
89800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1460989800
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.4143273806
Short name T470
Test name
Test status
Simulation time 488896483 ps
CPU time 32.78 seconds
Started Jul 18 04:50:48 PM PDT 24
Finished Jul 18 04:51:23 PM PDT 24
Peak memory 248860 kb
Host smart-98c615ce-d7fe-4e79-9bd9-96db83a4b4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41432
73806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.4143273806
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.4115524028
Short name T127
Test name
Test status
Simulation time 17367455034 ps
CPU time 1506.44 seconds
Started Jul 18 04:50:49 PM PDT 24
Finished Jul 18 05:15:58 PM PDT 24
Peak memory 289376 kb
Host smart-ab491720-944d-4cad-af36-870fed50c5f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115524028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4115524028
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1336637713
Short name T528
Test name
Test status
Simulation time 24249179497 ps
CPU time 1569.12 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 05:16:59 PM PDT 24
Peak memory 273536 kb
Host smart-181cf089-f9b5-4be0-93a0-506386b40e78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336637713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1336637713
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3526390955
Short name T318
Test name
Test status
Simulation time 7564595872 ps
CPU time 294.32 seconds
Started Jul 18 04:50:48 PM PDT 24
Finished Jul 18 04:55:45 PM PDT 24
Peak memory 247856 kb
Host smart-838d22de-c51a-49ff-956a-e6e9266cbea1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526390955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3526390955
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1531604502
Short name T434
Test name
Test status
Simulation time 831477486 ps
CPU time 18.51 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 04:51:06 PM PDT 24
Peak memory 256748 kb
Host smart-2467c4c5-33c2-4cdd-aacb-2c8d189429ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15316
04502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1531604502
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2477515859
Short name T102
Test name
Test status
Simulation time 798030243 ps
CPU time 48.23 seconds
Started Jul 18 04:50:44 PM PDT 24
Finished Jul 18 04:51:33 PM PDT 24
Peak memory 249476 kb
Host smart-ec8cb19e-96ca-498f-b9b5-26bcf3dbf0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24775
15859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2477515859
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.289685852
Short name T74
Test name
Test status
Simulation time 1373083546 ps
CPU time 40.23 seconds
Started Jul 18 04:50:45 PM PDT 24
Finished Jul 18 04:51:28 PM PDT 24
Peak memory 248492 kb
Host smart-198e9203-7ae5-4fba-82c3-115b3ea0cde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28968
5852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.289685852
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.164761268
Short name T478
Test name
Test status
Simulation time 2542517060 ps
CPU time 36.93 seconds
Started Jul 18 04:50:48 PM PDT 24
Finished Jul 18 04:51:28 PM PDT 24
Peak memory 257112 kb
Host smart-420895c6-2ce4-41a3-b268-f680d5abb988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16476
1268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.164761268
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2865897312
Short name T280
Test name
Test status
Simulation time 10797884276 ps
CPU time 988.07 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 05:07:17 PM PDT 24
Peak memory 289164 kb
Host smart-fd6cdc6d-fa86-4abe-a418-54dd558938db
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865897312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2865897312
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.449829167
Short name T110
Test name
Test status
Simulation time 18232120617 ps
CPU time 2053.18 seconds
Started Jul 18 04:50:48 PM PDT 24
Finished Jul 18 05:25:05 PM PDT 24
Peak memory 305664 kb
Host smart-5a7b4b7e-57a6-4ccf-aa14-ebbe817155a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449829167 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.449829167
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.184083890
Short name T560
Test name
Test status
Simulation time 21447751633 ps
CPU time 272.76 seconds
Started Jul 18 04:50:48 PM PDT 24
Finished Jul 18 04:55:24 PM PDT 24
Peak memory 256772 kb
Host smart-c85c47ba-86b4-43ff-aec9-92ada27f4d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18408
3890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.184083890
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3997937946
Short name T551
Test name
Test status
Simulation time 269155886 ps
CPU time 21.38 seconds
Started Jul 18 04:50:48 PM PDT 24
Finished Jul 18 04:51:13 PM PDT 24
Peak memory 255992 kb
Host smart-3825edf6-29d4-43e6-8d15-ec697fb439c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39979
37946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3997937946
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3677701785
Short name T424
Test name
Test status
Simulation time 33457691513 ps
CPU time 1803.37 seconds
Started Jul 18 04:51:08 PM PDT 24
Finished Jul 18 05:21:12 PM PDT 24
Peak memory 284268 kb
Host smart-eba4a150-393d-4276-9966-a45b55bb6fdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677701785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3677701785
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.598142725
Short name T513
Test name
Test status
Simulation time 9183140825 ps
CPU time 367.27 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 04:56:57 PM PDT 24
Peak memory 248928 kb
Host smart-1fc61a1a-6aa4-4696-9ed9-48bb29a6243f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598142725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.598142725
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1475309918
Short name T78
Test name
Test status
Simulation time 1465282027 ps
CPU time 23.87 seconds
Started Jul 18 04:50:51 PM PDT 24
Finished Jul 18 04:51:16 PM PDT 24
Peak memory 257004 kb
Host smart-5e93487a-bb70-4f10-9446-fedd08ca8394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14753
09918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1475309918
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2654677280
Short name T120
Test name
Test status
Simulation time 2864072388 ps
CPU time 52.4 seconds
Started Jul 18 04:50:47 PM PDT 24
Finished Jul 18 04:51:43 PM PDT 24
Peak memory 248936 kb
Host smart-c697a7f0-91f9-4d69-88f7-1b64f4215d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26546
77280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2654677280
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2386838156
Short name T516
Test name
Test status
Simulation time 226893183 ps
CPU time 3.29 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 04:50:53 PM PDT 24
Peak memory 248920 kb
Host smart-eaae9054-8863-42ce-8f38-3aeab5643c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23868
38156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2386838156
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4180620873
Short name T509
Test name
Test status
Simulation time 913638716 ps
CPU time 24.59 seconds
Started Jul 18 04:50:46 PM PDT 24
Finished Jul 18 04:51:14 PM PDT 24
Peak memory 248900 kb
Host smart-d695f225-a2f9-4c06-8557-5d53fdb39bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41806
20873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4180620873
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3031107830
Short name T104
Test name
Test status
Simulation time 39071950139 ps
CPU time 2494.53 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 05:32:48 PM PDT 24
Peak memory 290048 kb
Host smart-71b58f1f-f1e4-4fef-82ca-ad222647cbef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031107830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3031107830
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2104863064
Short name T609
Test name
Test status
Simulation time 16798476649 ps
CPU time 1059.88 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 05:08:50 PM PDT 24
Peak memory 272992 kb
Host smart-cfcf7c71-5517-4e2b-8b9b-c6dae32861a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104863064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2104863064
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.886618442
Short name T531
Test name
Test status
Simulation time 2643069142 ps
CPU time 113.73 seconds
Started Jul 18 04:51:07 PM PDT 24
Finished Jul 18 04:53:02 PM PDT 24
Peak memory 256612 kb
Host smart-ea5be6d1-e144-4f03-a0c4-fad981d908ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88661
8442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.886618442
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3676231328
Short name T702
Test name
Test status
Simulation time 137556416 ps
CPU time 14.26 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 04:51:29 PM PDT 24
Peak memory 248476 kb
Host smart-5b61a6e0-d1c6-483e-a7f7-40f34fa17dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36762
31328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3676231328
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2266302472
Short name T111
Test name
Test status
Simulation time 13769509409 ps
CPU time 1176.47 seconds
Started Jul 18 04:51:10 PM PDT 24
Finished Jul 18 05:10:49 PM PDT 24
Peak memory 290004 kb
Host smart-67ffdc64-706e-4df1-9b47-9663da7ad461
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266302472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2266302472
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.439490608
Short name T321
Test name
Test status
Simulation time 6870266539 ps
CPU time 144.64 seconds
Started Jul 18 04:51:07 PM PDT 24
Finished Jul 18 04:53:33 PM PDT 24
Peak memory 249080 kb
Host smart-b011a2a6-496b-45d7-b40f-7434967e15dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439490608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.439490608
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3029689418
Short name T458
Test name
Test status
Simulation time 1519342960 ps
CPU time 41.38 seconds
Started Jul 18 04:51:08 PM PDT 24
Finished Jul 18 04:51:51 PM PDT 24
Peak memory 248852 kb
Host smart-08fdf543-0585-4f69-ac53-347084e470e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30296
89418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3029689418
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.396923906
Short name T535
Test name
Test status
Simulation time 822435306 ps
CPU time 51.23 seconds
Started Jul 18 04:51:15 PM PDT 24
Finished Jul 18 04:52:08 PM PDT 24
Peak memory 256956 kb
Host smart-9d50444d-efdf-4084-bbdf-fc201240f672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39692
3906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.396923906
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1112529908
Short name T687
Test name
Test status
Simulation time 156061041 ps
CPU time 18.22 seconds
Started Jul 18 04:51:07 PM PDT 24
Finished Jul 18 04:51:26 PM PDT 24
Peak memory 248908 kb
Host smart-88bfdde8-9ffa-4e4c-82bf-0d10601163c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11125
29908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1112529908
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.4270259847
Short name T500
Test name
Test status
Simulation time 267816699 ps
CPU time 14.98 seconds
Started Jul 18 04:51:10 PM PDT 24
Finished Jul 18 04:51:28 PM PDT 24
Peak memory 248824 kb
Host smart-28667618-718b-4ee9-b417-37df3f31f340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42702
59847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.4270259847
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1354692845
Short name T271
Test name
Test status
Simulation time 274855850 ps
CPU time 15.75 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 04:51:26 PM PDT 24
Peak memory 248256 kb
Host smart-ebac98cd-c98f-492b-95e7-4005f8f80778
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354692845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1354692845
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.4280226841
Short name T278
Test name
Test status
Simulation time 13220461017 ps
CPU time 762.73 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 05:03:53 PM PDT 24
Peak memory 282308 kb
Host smart-47999f1e-2109-447d-a27a-7ece3c642d2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280226841 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.4280226841
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1931513392
Short name T315
Test name
Test status
Simulation time 83801782402 ps
CPU time 1324.03 seconds
Started Jul 18 04:51:07 PM PDT 24
Finished Jul 18 05:13:12 PM PDT 24
Peak memory 273500 kb
Host smart-8cc5dcbe-161e-43c1-99b4-6dd62f6ed96d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931513392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1931513392
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2229404028
Short name T433
Test name
Test status
Simulation time 460828982 ps
CPU time 25.72 seconds
Started Jul 18 04:51:08 PM PDT 24
Finished Jul 18 04:51:35 PM PDT 24
Peak memory 248212 kb
Host smart-44961ec1-d21c-4cd6-ada1-6d70ff1f6521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22294
04028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2229404028
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1063681780
Short name T404
Test name
Test status
Simulation time 1142071836 ps
CPU time 23.82 seconds
Started Jul 18 04:51:08 PM PDT 24
Finished Jul 18 04:51:33 PM PDT 24
Peak memory 256604 kb
Host smart-00602560-99f8-498f-8a0d-a2ec40d2ff3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10636
81780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1063681780
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2616136211
Short name T137
Test name
Test status
Simulation time 210227188027 ps
CPU time 2825.15 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 05:38:16 PM PDT 24
Peak memory 289228 kb
Host smart-eb8eff97-3f52-4eb2-bb71-230b2011f899
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616136211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2616136211
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1193803526
Short name T360
Test name
Test status
Simulation time 40810444368 ps
CPU time 2474.68 seconds
Started Jul 18 04:51:08 PM PDT 24
Finished Jul 18 05:32:24 PM PDT 24
Peak memory 285664 kb
Host smart-8754e483-2d4e-492e-bce8-54962e2914d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193803526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1193803526
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3509551603
Short name T600
Test name
Test status
Simulation time 5240493546 ps
CPU time 206.36 seconds
Started Jul 18 04:51:15 PM PDT 24
Finished Jul 18 04:54:43 PM PDT 24
Peak memory 249012 kb
Host smart-f2501872-349d-4993-aac3-cee69567c05a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509551603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3509551603
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3221996666
Short name T608
Test name
Test status
Simulation time 472881065 ps
CPU time 7.33 seconds
Started Jul 18 04:51:10 PM PDT 24
Finished Jul 18 04:51:20 PM PDT 24
Peak memory 248952 kb
Host smart-22c652d9-41e1-4f2f-8b75-507bf559ca04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32219
96666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3221996666
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2318530253
Short name T661
Test name
Test status
Simulation time 1236885837 ps
CPU time 28.61 seconds
Started Jul 18 04:51:10 PM PDT 24
Finished Jul 18 04:51:41 PM PDT 24
Peak memory 248444 kb
Host smart-58be0c53-4c39-45f8-a720-853b184bbb3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23185
30253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2318530253
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2890532519
Short name T1
Test name
Test status
Simulation time 194434623 ps
CPU time 11.74 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 04:51:23 PM PDT 24
Peak memory 249040 kb
Host smart-145c20f5-6700-41b4-80fd-ca9f11e1f8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28905
32519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2890532519
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.242605742
Short name T85
Test name
Test status
Simulation time 3968824462 ps
CPU time 52.01 seconds
Started Jul 18 04:51:08 PM PDT 24
Finished Jul 18 04:52:02 PM PDT 24
Peak memory 256232 kb
Host smart-64f8e40e-06db-41d4-94fa-90a065ae57ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24260
5742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.242605742
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2447755007
Short name T57
Test name
Test status
Simulation time 23352883287 ps
CPU time 1338.07 seconds
Started Jul 18 04:51:12 PM PDT 24
Finished Jul 18 05:13:33 PM PDT 24
Peak memory 273128 kb
Host smart-e71cb968-7b56-492b-9631-51a2bf90985c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447755007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2447755007
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3227076069
Short name T43
Test name
Test status
Simulation time 2440657589 ps
CPU time 104.9 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 04:52:56 PM PDT 24
Peak memory 256784 kb
Host smart-c11110d8-dc89-4800-8dae-f4c17b66edb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32270
76069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3227076069
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2281735439
Short name T690
Test name
Test status
Simulation time 4472815704 ps
CPU time 68.15 seconds
Started Jul 18 04:51:15 PM PDT 24
Finished Jul 18 04:52:25 PM PDT 24
Peak memory 249048 kb
Host smart-7e052a8e-721b-4f54-80e0-d173a680a920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22817
35439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2281735439
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2198303317
Short name T31
Test name
Test status
Simulation time 17945354950 ps
CPU time 826.16 seconds
Started Jul 18 04:51:14 PM PDT 24
Finished Jul 18 05:05:03 PM PDT 24
Peak memory 273592 kb
Host smart-ed8f0e08-efbe-4653-949d-5fe596941ba7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198303317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2198303317
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.807211888
Short name T410
Test name
Test status
Simulation time 10411971095 ps
CPU time 1039.9 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 05:08:31 PM PDT 24
Peak memory 288388 kb
Host smart-7c227ef9-0409-4eb2-b0ef-a1992b3bfc1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807211888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.807211888
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2554503184
Short name T326
Test name
Test status
Simulation time 18177720252 ps
CPU time 446.6 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 04:58:37 PM PDT 24
Peak memory 257172 kb
Host smart-9db8d3af-7861-4af9-a1ee-f6ee013ecef3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554503184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2554503184
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2822075383
Short name T546
Test name
Test status
Simulation time 77886368 ps
CPU time 3.15 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 04:51:14 PM PDT 24
Peak memory 240660 kb
Host smart-200827dc-2993-4189-aefa-5f54d8fbb108
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28220
75383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2822075383
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2459156876
Short name T142
Test name
Test status
Simulation time 882434745 ps
CPU time 20.69 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 04:51:31 PM PDT 24
Peak memory 255992 kb
Host smart-1136d33e-8df1-4b3f-a34f-688784d997c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24591
56876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2459156876
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2336447016
Short name T624
Test name
Test status
Simulation time 914162567 ps
CPU time 26.42 seconds
Started Jul 18 04:51:08 PM PDT 24
Finished Jul 18 04:51:36 PM PDT 24
Peak memory 248652 kb
Host smart-3ba403fc-3ba9-4dd6-b70d-bbc77d61a309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23364
47016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2336447016
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3707048275
Short name T18
Test name
Test status
Simulation time 325614810 ps
CPU time 28.21 seconds
Started Jul 18 04:51:08 PM PDT 24
Finished Jul 18 04:51:38 PM PDT 24
Peak memory 257148 kb
Host smart-aa8634d2-1b32-48c8-9f08-814fbee0cdc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37070
48275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3707048275
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2159229641
Short name T682
Test name
Test status
Simulation time 1783057455 ps
CPU time 111.7 seconds
Started Jul 18 04:51:09 PM PDT 24
Finished Jul 18 04:53:03 PM PDT 24
Peak memory 257172 kb
Host smart-a0456ffd-0e03-45e5-9132-5b63b769f262
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159229641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2159229641
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3370761709
Short name T543
Test name
Test status
Simulation time 14752194317 ps
CPU time 1069.7 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 05:09:04 PM PDT 24
Peak memory 282104 kb
Host smart-7b770155-6ddd-462a-bcaa-ab780fffeb91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370761709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3370761709
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1701486437
Short name T252
Test name
Test status
Simulation time 16891826259 ps
CPU time 237.27 seconds
Started Jul 18 04:51:08 PM PDT 24
Finished Jul 18 04:55:06 PM PDT 24
Peak memory 257296 kb
Host smart-f4c65c0d-4913-45f3-ba83-7ae685461008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17014
86437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1701486437
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1770648213
Short name T247
Test name
Test status
Simulation time 2829703443 ps
CPU time 47.17 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 04:52:02 PM PDT 24
Peak memory 257160 kb
Host smart-29f44d68-b8c7-4971-89d3-2f3b5c23013b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17706
48213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1770648213
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2426166933
Short name T412
Test name
Test status
Simulation time 126230843696 ps
CPU time 1945.13 seconds
Started Jul 18 04:51:08 PM PDT 24
Finished Jul 18 05:23:35 PM PDT 24
Peak memory 289980 kb
Host smart-44a2f255-3913-4f4c-bf37-3a982d5bc2bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426166933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2426166933
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.4214802399
Short name T342
Test name
Test status
Simulation time 10894409540 ps
CPU time 448.48 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 04:58:42 PM PDT 24
Peak memory 248880 kb
Host smart-a6d54b21-b05d-4f3c-aa4a-cf05b27bc545
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214802399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.4214802399
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1838471787
Short name T487
Test name
Test status
Simulation time 238822161 ps
CPU time 15.17 seconds
Started Jul 18 04:51:13 PM PDT 24
Finished Jul 18 04:51:31 PM PDT 24
Peak memory 248888 kb
Host smart-7907c001-407c-495b-b178-c645df42fecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18384
71787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1838471787
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3681220470
Short name T132
Test name
Test status
Simulation time 1789580887 ps
CPU time 46.16 seconds
Started Jul 18 04:51:12 PM PDT 24
Finished Jul 18 04:52:01 PM PDT 24
Peak memory 249228 kb
Host smart-9adfb795-9fec-4a59-816c-9dd70c6eedcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36812
20470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3681220470
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.119028463
Short name T695
Test name
Test status
Simulation time 685069211 ps
CPU time 43.04 seconds
Started Jul 18 04:51:14 PM PDT 24
Finished Jul 18 04:52:00 PM PDT 24
Peak memory 256500 kb
Host smart-8edbc2ba-26bf-4bc4-bffa-37c518833a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11902
8463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.119028463
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3477625369
Short name T383
Test name
Test status
Simulation time 625263031 ps
CPU time 13.68 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 04:51:27 PM PDT 24
Peak memory 255056 kb
Host smart-123b3d1c-64ce-4a74-bf8e-85eae95a45cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34776
25369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3477625369
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3759660077
Short name T460
Test name
Test status
Simulation time 23150222365 ps
CPU time 280 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 04:55:53 PM PDT 24
Peak memory 257228 kb
Host smart-47e71960-c2c1-454a-9523-d95060de82b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759660077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3759660077
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3196022591
Short name T664
Test name
Test status
Simulation time 34543821303 ps
CPU time 1821.07 seconds
Started Jul 18 04:51:16 PM PDT 24
Finished Jul 18 05:21:38 PM PDT 24
Peak memory 273672 kb
Host smart-7bc9c9e3-557b-48b0-bc8c-997d9cfa3d6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196022591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3196022591
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1554488386
Short name T494
Test name
Test status
Simulation time 2302125273 ps
CPU time 115.92 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 04:53:10 PM PDT 24
Peak memory 257168 kb
Host smart-645641b5-5e1b-4f5b-b41d-a8851490d4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15544
88386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1554488386
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.62878200
Short name T637
Test name
Test status
Simulation time 175516741 ps
CPU time 13.43 seconds
Started Jul 18 04:51:13 PM PDT 24
Finished Jul 18 04:51:29 PM PDT 24
Peak memory 254840 kb
Host smart-f93b55ca-d8a8-468b-a037-2038f63d6ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62878
200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.62878200
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3204207508
Short name T359
Test name
Test status
Simulation time 68189233106 ps
CPU time 1422.98 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 05:14:57 PM PDT 24
Peak memory 281824 kb
Host smart-47898b0b-5b62-4e70-b237-ae35cb426ac8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204207508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3204207508
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1607781138
Short name T586
Test name
Test status
Simulation time 58422718500 ps
CPU time 2775.29 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 05:37:29 PM PDT 24
Peak memory 289656 kb
Host smart-ba355722-fb98-4338-900f-4498980b85a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607781138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1607781138
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.855346517
Short name T293
Test name
Test status
Simulation time 783456394 ps
CPU time 54.44 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 04:52:08 PM PDT 24
Peak memory 256184 kb
Host smart-e8e875ed-77d4-433a-abdf-b3bcdddc4a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85534
6517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.855346517
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3957398867
Short name T530
Test name
Test status
Simulation time 2711267480 ps
CPU time 50.01 seconds
Started Jul 18 04:51:17 PM PDT 24
Finished Jul 18 04:52:08 PM PDT 24
Peak memory 248880 kb
Host smart-e4ba41a7-3147-4f96-83ea-110859b084dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573
98867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3957398867
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.525665452
Short name T674
Test name
Test status
Simulation time 329954713 ps
CPU time 20.99 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 04:51:35 PM PDT 24
Peak memory 256384 kb
Host smart-4a550ac5-5805-47b5-9f5c-f202e018fdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52566
5452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.525665452
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.599908699
Short name T209
Test name
Test status
Simulation time 332891908191 ps
CPU time 6564.63 seconds
Started Jul 18 04:51:17 PM PDT 24
Finished Jul 18 06:40:43 PM PDT 24
Peak memory 395532 kb
Host smart-45739faa-671b-426c-b800-1d3424c44f8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599908699 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.599908699
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2990780792
Short name T48
Test name
Test status
Simulation time 87684692096 ps
CPU time 1116.91 seconds
Started Jul 18 04:51:13 PM PDT 24
Finished Jul 18 05:09:53 PM PDT 24
Peak memory 273440 kb
Host smart-62ee84ba-f833-4ebd-9def-a88137e7bb6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990780792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2990780792
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2199968001
Short name T469
Test name
Test status
Simulation time 1367768653 ps
CPU time 88.43 seconds
Started Jul 18 04:51:14 PM PDT 24
Finished Jul 18 04:52:45 PM PDT 24
Peak memory 256608 kb
Host smart-3593bb28-d27c-4856-a88a-bbe950421947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21999
68001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2199968001
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.4272148018
Short name T419
Test name
Test status
Simulation time 254320776 ps
CPU time 3.8 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 04:51:18 PM PDT 24
Peak memory 251872 kb
Host smart-c3cd989f-f222-4d45-b410-70ef7ce70281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42721
48018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4272148018
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2980105852
Short name T7
Test name
Test status
Simulation time 85689747842 ps
CPU time 1324.85 seconds
Started Jul 18 04:51:13 PM PDT 24
Finished Jul 18 05:13:21 PM PDT 24
Peak memory 289372 kb
Host smart-2d0d4e73-1216-4d49-af2c-eba3ef7240fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980105852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2980105852
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.592650884
Short name T27
Test name
Test status
Simulation time 119148357724 ps
CPU time 1766.5 seconds
Started Jul 18 04:51:14 PM PDT 24
Finished Jul 18 05:20:43 PM PDT 24
Peak memory 273524 kb
Host smart-be08339f-2893-424c-a0b4-553f36aaaf69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592650884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.592650884
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2357508472
Short name T139
Test name
Test status
Simulation time 6744589033 ps
CPU time 270.31 seconds
Started Jul 18 04:51:14 PM PDT 24
Finished Jul 18 04:55:47 PM PDT 24
Peak memory 249008 kb
Host smart-73ac91bc-d793-467e-9cee-7877b280e712
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357508472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2357508472
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2591479206
Short name T616
Test name
Test status
Simulation time 414198523 ps
CPU time 28.73 seconds
Started Jul 18 04:51:17 PM PDT 24
Finished Jul 18 04:51:47 PM PDT 24
Peak memory 256476 kb
Host smart-8e802170-cc6a-4932-8ade-cdfd3dad5576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25914
79206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2591479206
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3114416266
Short name T646
Test name
Test status
Simulation time 42444568 ps
CPU time 6.52 seconds
Started Jul 18 04:51:13 PM PDT 24
Finished Jul 18 04:51:22 PM PDT 24
Peak memory 248456 kb
Host smart-da68c728-8687-4c31-b7d2-8e3aa69429d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31144
16266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3114416266
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.342619654
Short name T523
Test name
Test status
Simulation time 948639620 ps
CPU time 16.66 seconds
Started Jul 18 04:51:14 PM PDT 24
Finished Jul 18 04:51:33 PM PDT 24
Peak memory 253608 kb
Host smart-add537ba-f2ab-4b3b-96b7-4f16d4098df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34261
9654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.342619654
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1165892823
Short name T550
Test name
Test status
Simulation time 954967003 ps
CPU time 17.43 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 04:51:31 PM PDT 24
Peak memory 255124 kb
Host smart-defd1ab3-597d-4ca5-bad4-0fda950b59aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11658
92823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1165892823
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.715009447
Short name T96
Test name
Test status
Simulation time 200362485013 ps
CPU time 2554.2 seconds
Started Jul 18 04:51:10 PM PDT 24
Finished Jul 18 05:33:47 PM PDT 24
Peak memory 289824 kb
Host smart-1b300e68-f278-43ff-9c4a-e6bc03cbd1d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715009447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.715009447
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.978750703
Short name T229
Test name
Test status
Simulation time 132751132 ps
CPU time 3.78 seconds
Started Jul 18 04:49:16 PM PDT 24
Finished Jul 18 04:49:21 PM PDT 24
Peak memory 248980 kb
Host smart-07b08a3a-d981-4f2c-a50f-acfa024f928d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=978750703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.978750703
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3618354982
Short name T116
Test name
Test status
Simulation time 204810078893 ps
CPU time 2949.36 seconds
Started Jul 18 04:49:15 PM PDT 24
Finished Jul 18 05:38:26 PM PDT 24
Peak memory 288556 kb
Host smart-9d22551a-85ff-484c-9fed-e1cf3c041ac6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618354982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3618354982
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1742594535
Short name T246
Test name
Test status
Simulation time 2057827000 ps
CPU time 25.17 seconds
Started Jul 18 04:49:12 PM PDT 24
Finished Jul 18 04:49:39 PM PDT 24
Peak memory 248812 kb
Host smart-b1949c5e-7d2c-4e39-bd6a-76083a38e5c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1742594535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1742594535
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2394224721
Short name T468
Test name
Test status
Simulation time 3619004795 ps
CPU time 213.65 seconds
Started Jul 18 04:49:16 PM PDT 24
Finished Jul 18 04:52:51 PM PDT 24
Peak memory 257108 kb
Host smart-b62b3528-bf55-49c1-9a3f-240ea08f711b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23942
24721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2394224721
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.138179670
Short name T525
Test name
Test status
Simulation time 1044367864 ps
CPU time 20.02 seconds
Started Jul 18 04:49:13 PM PDT 24
Finished Jul 18 04:49:34 PM PDT 24
Peak memory 248844 kb
Host smart-9b8ff3f3-fa18-48b8-aaf6-8d903dedef69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13817
9670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.138179670
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2050274219
Short name T355
Test name
Test status
Simulation time 15056668735 ps
CPU time 1312.31 seconds
Started Jul 18 04:49:18 PM PDT 24
Finished Jul 18 05:11:11 PM PDT 24
Peak memory 283572 kb
Host smart-290059c0-1c61-4903-be35-914135bbbdc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050274219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2050274219
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2845123204
Short name T657
Test name
Test status
Simulation time 59146404739 ps
CPU time 1952.64 seconds
Started Jul 18 04:49:12 PM PDT 24
Finished Jul 18 05:21:47 PM PDT 24
Peak memory 285620 kb
Host smart-26448cf9-75bf-4a50-a1c4-fbc3b74ab4ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845123204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2845123204
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.26736865
Short name T668
Test name
Test status
Simulation time 5272881296 ps
CPU time 220.75 seconds
Started Jul 18 04:49:15 PM PDT 24
Finished Jul 18 04:52:58 PM PDT 24
Peak memory 249048 kb
Host smart-484e1bf6-d5cb-48c7-99a1-34b014e0ddcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26736865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.26736865
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.4166887685
Short name T644
Test name
Test status
Simulation time 434615150 ps
CPU time 12.71 seconds
Started Jul 18 04:49:13 PM PDT 24
Finished Jul 18 04:49:27 PM PDT 24
Peak memory 248956 kb
Host smart-9e7419d7-d194-4f30-8b2a-f90ca2ccbe26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41668
87685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.4166887685
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3730442595
Short name T485
Test name
Test status
Simulation time 2588212341 ps
CPU time 21.42 seconds
Started Jul 18 04:49:08 PM PDT 24
Finished Jul 18 04:49:30 PM PDT 24
Peak memory 256908 kb
Host smart-c069e16c-2876-4a3c-88f9-3a100c128fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37304
42595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3730442595
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.443907668
Short name T13
Test name
Test status
Simulation time 321276769 ps
CPU time 11.5 seconds
Started Jul 18 04:49:14 PM PDT 24
Finished Jul 18 04:49:27 PM PDT 24
Peak memory 267212 kb
Host smart-e8d9bb87-34c9-4881-8f3f-c1854028f584
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=443907668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.443907668
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.182084362
Short name T578
Test name
Test status
Simulation time 384808591 ps
CPU time 8.65 seconds
Started Jul 18 04:49:15 PM PDT 24
Finished Jul 18 04:49:25 PM PDT 24
Peak memory 248940 kb
Host smart-3143cd98-65a4-4c0d-9c34-eec3cd081f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18208
4362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.182084362
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.385372157
Short name T463
Test name
Test status
Simulation time 510363596 ps
CPU time 26.94 seconds
Started Jul 18 04:49:12 PM PDT 24
Finished Jul 18 04:49:41 PM PDT 24
Peak memory 248864 kb
Host smart-327f1e07-b18f-495a-bd67-d2e57f7e7476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38537
2157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.385372157
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2054977299
Short name T284
Test name
Test status
Simulation time 83158199168 ps
CPU time 1382.45 seconds
Started Jul 18 04:49:17 PM PDT 24
Finished Jul 18 05:12:21 PM PDT 24
Peak memory 305724 kb
Host smart-ae48966e-d988-4f1c-81c0-9ac72e902aeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054977299 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2054977299
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.993409722
Short name T214
Test name
Test status
Simulation time 18971881588 ps
CPU time 1616.24 seconds
Started Jul 18 04:51:24 PM PDT 24
Finished Jul 18 05:18:21 PM PDT 24
Peak memory 289048 kb
Host smart-3cf1c022-7d93-44eb-9ff9-a5b48fc7057f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993409722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.993409722
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3796657044
Short name T472
Test name
Test status
Simulation time 5025798659 ps
CPU time 68.26 seconds
Started Jul 18 04:51:23 PM PDT 24
Finished Jul 18 04:52:32 PM PDT 24
Peak memory 256684 kb
Host smart-7c271c96-9b63-44a4-a94f-201a1e0f4598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37966
57044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3796657044
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.448701299
Short name T94
Test name
Test status
Simulation time 469510383 ps
CPU time 18.95 seconds
Started Jul 18 04:51:23 PM PDT 24
Finished Jul 18 04:51:43 PM PDT 24
Peak memory 254104 kb
Host smart-cb511f70-670b-4dc7-abc7-a632214e4a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44870
1299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.448701299
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1890890413
Short name T415
Test name
Test status
Simulation time 34274256798 ps
CPU time 850.03 seconds
Started Jul 18 04:51:23 PM PDT 24
Finished Jul 18 05:05:34 PM PDT 24
Peak memory 273384 kb
Host smart-5dc2c068-d348-4a3e-a33b-02d7aff9f5f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890890413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1890890413
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1663236100
Short name T4
Test name
Test status
Simulation time 40067594374 ps
CPU time 2145.49 seconds
Started Jul 18 04:51:12 PM PDT 24
Finished Jul 18 05:27:01 PM PDT 24
Peak memory 282772 kb
Host smart-c0513d0f-b5c0-491a-a576-8cb2c6eb5d71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663236100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1663236100
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1834085967
Short name T581
Test name
Test status
Simulation time 2065351460 ps
CPU time 46.78 seconds
Started Jul 18 04:51:24 PM PDT 24
Finished Jul 18 04:52:11 PM PDT 24
Peak memory 248928 kb
Host smart-0a22ac97-44d8-41b8-934b-a77cf8762521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18340
85967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1834085967
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.20121767
Short name T429
Test name
Test status
Simulation time 143706772 ps
CPU time 15.37 seconds
Started Jul 18 04:51:14 PM PDT 24
Finished Jul 18 04:51:32 PM PDT 24
Peak memory 248276 kb
Host smart-b76b44a4-69c1-43d6-a271-d30356d82ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20121
767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.20121767
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2268369042
Short name T502
Test name
Test status
Simulation time 441188239 ps
CPU time 12.7 seconds
Started Jul 18 04:51:13 PM PDT 24
Finished Jul 18 04:51:28 PM PDT 24
Peak memory 249388 kb
Host smart-2b574a3c-5139-469b-ba85-6fb47dbc83c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22683
69042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2268369042
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1095267133
Short name T524
Test name
Test status
Simulation time 1686780756 ps
CPU time 51.56 seconds
Started Jul 18 04:51:13 PM PDT 24
Finished Jul 18 04:52:08 PM PDT 24
Peak memory 257060 kb
Host smart-21429605-187e-4a4a-8bf9-336dd5ae88f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10952
67133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1095267133
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3522919621
Short name T619
Test name
Test status
Simulation time 125118142238 ps
CPU time 1792.48 seconds
Started Jul 18 04:51:11 PM PDT 24
Finished Jul 18 05:21:05 PM PDT 24
Peak memory 289592 kb
Host smart-f11f10bd-f5ee-4694-9615-6dec0b54385a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522919621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3522919621
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.118841964
Short name T641
Test name
Test status
Simulation time 1085541417 ps
CPU time 84 seconds
Started Jul 18 04:51:10 PM PDT 24
Finished Jul 18 04:52:36 PM PDT 24
Peak memory 257092 kb
Host smart-303b836a-b8a8-4ac8-b6d4-a613cbd101b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11884
1964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.118841964
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1224723504
Short name T684
Test name
Test status
Simulation time 141091816 ps
CPU time 3.69 seconds
Started Jul 18 04:51:13 PM PDT 24
Finished Jul 18 04:51:20 PM PDT 24
Peak memory 249132 kb
Host smart-9802731c-c7af-485e-acdf-4be930a65f58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12247
23504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1224723504
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2421275538
Short name T439
Test name
Test status
Simulation time 76591330991 ps
CPU time 1204.25 seconds
Started Jul 18 04:51:19 PM PDT 24
Finished Jul 18 05:11:24 PM PDT 24
Peak memory 287596 kb
Host smart-6dc7ae66-ea4e-4884-8ae8-90d627549e2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421275538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2421275538
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3352606333
Short name T300
Test name
Test status
Simulation time 5945524896 ps
CPU time 710.22 seconds
Started Jul 18 04:51:10 PM PDT 24
Finished Jul 18 05:03:02 PM PDT 24
Peak memory 273464 kb
Host smart-5b40b26c-10c2-4d6a-9c04-511610936663
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352606333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3352606333
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2141874491
Short name T248
Test name
Test status
Simulation time 15706271066 ps
CPU time 615.83 seconds
Started Jul 18 04:51:10 PM PDT 24
Finished Jul 18 05:01:28 PM PDT 24
Peak memory 256976 kb
Host smart-a8fe490b-924e-4697-9136-c3495d3210a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141874491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2141874491
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.97870056
Short name T480
Test name
Test status
Simulation time 1710025727 ps
CPU time 35.62 seconds
Started Jul 18 04:51:14 PM PDT 24
Finished Jul 18 04:51:52 PM PDT 24
Peak memory 256544 kb
Host smart-3e508f44-60d6-45cc-ae9b-bcb7c74abab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97870
056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.97870056
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2298588060
Short name T593
Test name
Test status
Simulation time 47777800 ps
CPU time 4.36 seconds
Started Jul 18 04:51:14 PM PDT 24
Finished Jul 18 04:51:21 PM PDT 24
Peak memory 240764 kb
Host smart-1d7412ee-9e6b-4f02-b57e-c110e3b73060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22985
88060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2298588060
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3222905027
Short name T648
Test name
Test status
Simulation time 299290371 ps
CPU time 10.89 seconds
Started Jul 18 04:51:19 PM PDT 24
Finished Jul 18 04:51:30 PM PDT 24
Peak memory 248152 kb
Host smart-02714cdb-5793-4d94-be72-bb9b24411ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32229
05027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3222905027
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.755913888
Short name T387
Test name
Test status
Simulation time 76828135 ps
CPU time 6.37 seconds
Started Jul 18 04:51:13 PM PDT 24
Finished Jul 18 04:51:22 PM PDT 24
Peak memory 251280 kb
Host smart-f0806937-1488-4129-9725-0836473ecc69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75591
3888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.755913888
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3132947583
Short name T483
Test name
Test status
Simulation time 8996582753 ps
CPU time 734.28 seconds
Started Jul 18 04:51:31 PM PDT 24
Finished Jul 18 05:03:46 PM PDT 24
Peak memory 289972 kb
Host smart-1d604f8e-b9cf-4072-8c3d-6df1cc761a16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132947583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3132947583
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2734894397
Short name T555
Test name
Test status
Simulation time 3911430561 ps
CPU time 119.06 seconds
Started Jul 18 04:51:37 PM PDT 24
Finished Jul 18 04:53:37 PM PDT 24
Peak memory 256660 kb
Host smart-c473da92-771e-4093-8176-46bd1bb518ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27348
94397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2734894397
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1304659322
Short name T92
Test name
Test status
Simulation time 1182420647 ps
CPU time 16.44 seconds
Started Jul 18 04:51:33 PM PDT 24
Finished Jul 18 04:51:50 PM PDT 24
Peak memory 256236 kb
Host smart-f9d4ed63-aa20-4a4e-a1ed-9bb1a42d07a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13046
59322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1304659322
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2755841204
Short name T76
Test name
Test status
Simulation time 242466868583 ps
CPU time 3422.32 seconds
Started Jul 18 04:51:34 PM PDT 24
Finished Jul 18 05:48:39 PM PDT 24
Peak memory 289216 kb
Host smart-31bdc2f8-db7e-4e4d-bdda-9c798ec76865
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755841204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2755841204
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.47080215
Short name T508
Test name
Test status
Simulation time 64286115262 ps
CPU time 1534.9 seconds
Started Jul 18 04:51:34 PM PDT 24
Finished Jul 18 05:17:10 PM PDT 24
Peak memory 289296 kb
Host smart-f1d4b45f-863f-4538-9b36-9310d05ef2d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47080215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.47080215
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3204974495
Short name T307
Test name
Test status
Simulation time 2926867954 ps
CPU time 116.86 seconds
Started Jul 18 04:51:35 PM PDT 24
Finished Jul 18 04:53:33 PM PDT 24
Peak memory 248932 kb
Host smart-56073805-228c-4fd9-8369-dc6e527cdd96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204974495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3204974495
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.359961945
Short name T39
Test name
Test status
Simulation time 64207371 ps
CPU time 6.87 seconds
Started Jul 18 04:51:31 PM PDT 24
Finished Jul 18 04:51:39 PM PDT 24
Peak memory 248892 kb
Host smart-10d600eb-a444-4e2c-841d-f5be696d11e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35996
1945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.359961945
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3724689065
Short name T396
Test name
Test status
Simulation time 492508631 ps
CPU time 30.64 seconds
Started Jul 18 04:51:33 PM PDT 24
Finished Jul 18 04:52:05 PM PDT 24
Peak memory 256216 kb
Host smart-72d1ca0d-c225-4a2f-beae-32f1657764b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37246
89065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3724689065
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1733441770
Short name T532
Test name
Test status
Simulation time 371803635 ps
CPU time 23.89 seconds
Started Jul 18 04:51:35 PM PDT 24
Finished Jul 18 04:52:00 PM PDT 24
Peak memory 248700 kb
Host smart-c04d325a-991c-406a-baf6-4b3484707468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17334
41770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1733441770
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2233337147
Short name T677
Test name
Test status
Simulation time 1038098987 ps
CPU time 6.95 seconds
Started Jul 18 04:51:43 PM PDT 24
Finished Jul 18 04:51:51 PM PDT 24
Peak memory 251648 kb
Host smart-4062bb02-d382-4b95-bf9c-876e22f1a080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22333
37147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2233337147
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.987658837
Short name T393
Test name
Test status
Simulation time 32869868308 ps
CPU time 1054.4 seconds
Started Jul 18 04:51:35 PM PDT 24
Finished Jul 18 05:09:11 PM PDT 24
Peak memory 290052 kb
Host smart-15f0c8ae-b21b-4b7a-838d-b95070364c0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987658837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.987658837
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2055729751
Short name T698
Test name
Test status
Simulation time 53799226639 ps
CPU time 1549.25 seconds
Started Jul 18 04:51:35 PM PDT 24
Finished Jul 18 05:17:26 PM PDT 24
Peak memory 289712 kb
Host smart-1714a0cf-565f-4b0b-9458-771b32636996
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055729751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2055729751
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2092713828
Short name T421
Test name
Test status
Simulation time 17086049159 ps
CPU time 246.4 seconds
Started Jul 18 04:51:30 PM PDT 24
Finished Jul 18 04:55:37 PM PDT 24
Peak memory 257216 kb
Host smart-9a97482d-33d7-4242-bd95-dc92b1f9c26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20927
13828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2092713828
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3710761504
Short name T673
Test name
Test status
Simulation time 823720748 ps
CPU time 53.42 seconds
Started Jul 18 04:51:34 PM PDT 24
Finished Jul 18 04:52:29 PM PDT 24
Peak memory 256128 kb
Host smart-18222dad-95b0-430b-9caa-8c5ca27f7040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37107
61504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3710761504
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3761646217
Short name T361
Test name
Test status
Simulation time 204943339149 ps
CPU time 1936 seconds
Started Jul 18 04:51:43 PM PDT 24
Finished Jul 18 05:24:00 PM PDT 24
Peak memory 273576 kb
Host smart-37b163ad-8fdf-401b-81a0-82968e564b3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761646217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3761646217
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1656038900
Short name T303
Test name
Test status
Simulation time 35497985441 ps
CPU time 958.65 seconds
Started Jul 18 04:51:43 PM PDT 24
Finished Jul 18 05:07:43 PM PDT 24
Peak memory 273600 kb
Host smart-c9b98fff-03c4-401d-ae58-9e5a6af2b8ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656038900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1656038900
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3401947885
Short name T306
Test name
Test status
Simulation time 45691400309 ps
CPU time 476.08 seconds
Started Jul 18 04:51:34 PM PDT 24
Finished Jul 18 04:59:31 PM PDT 24
Peak memory 248992 kb
Host smart-87510deb-a260-4f97-83d3-5fcc5b39dd16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401947885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3401947885
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2397010084
Short name T647
Test name
Test status
Simulation time 427309022 ps
CPU time 36.94 seconds
Started Jul 18 04:51:32 PM PDT 24
Finished Jul 18 04:52:09 PM PDT 24
Peak memory 256400 kb
Host smart-61cdfddc-08e1-46af-86b1-65bff48c3d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23970
10084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2397010084
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3612748938
Short name T117
Test name
Test status
Simulation time 1001438536 ps
CPU time 11.2 seconds
Started Jul 18 04:51:33 PM PDT 24
Finished Jul 18 04:51:45 PM PDT 24
Peak memory 256700 kb
Host smart-8ab384db-38a2-4afe-a03c-09290ab9fd19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36127
48938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3612748938
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.4154345913
Short name T2
Test name
Test status
Simulation time 637024121 ps
CPU time 39.71 seconds
Started Jul 18 04:51:38 PM PDT 24
Finished Jul 18 04:52:18 PM PDT 24
Peak memory 256544 kb
Host smart-ca8219c3-d404-4150-9d9a-304f8b5ad131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41543
45913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.4154345913
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1411330736
Short name T452
Test name
Test status
Simulation time 1969268056 ps
CPU time 12.13 seconds
Started Jul 18 04:51:33 PM PDT 24
Finished Jul 18 04:51:47 PM PDT 24
Peak memory 257064 kb
Host smart-a1adcc48-9a8d-4b95-bc7e-7670a7fd8658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14113
30736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1411330736
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.932645409
Short name T635
Test name
Test status
Simulation time 57099243051 ps
CPU time 1877.07 seconds
Started Jul 18 04:51:32 PM PDT 24
Finished Jul 18 05:22:51 PM PDT 24
Peak memory 305112 kb
Host smart-2c477edc-0dcd-4bfc-a1e2-6cab0f2623a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932645409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.932645409
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.634547906
Short name T629
Test name
Test status
Simulation time 181408227975 ps
CPU time 1741.62 seconds
Started Jul 18 04:51:33 PM PDT 24
Finished Jul 18 05:20:36 PM PDT 24
Peak memory 272844 kb
Host smart-656ab11d-3247-4a99-a371-996c1c9a23d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634547906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.634547906
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3174155290
Short name T40
Test name
Test status
Simulation time 753534266 ps
CPU time 55.09 seconds
Started Jul 18 04:51:33 PM PDT 24
Finished Jul 18 04:52:29 PM PDT 24
Peak memory 257052 kb
Host smart-84de1097-90aa-47b0-b14f-464695d9fc66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31741
55290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3174155290
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.269508298
Short name T83
Test name
Test status
Simulation time 601133778 ps
CPU time 10.94 seconds
Started Jul 18 04:51:43 PM PDT 24
Finished Jul 18 04:51:55 PM PDT 24
Peak memory 253432 kb
Host smart-f73fb8ab-92a6-4958-a5f9-f37e9e37bda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26950
8298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.269508298
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1752733543
Short name T121
Test name
Test status
Simulation time 150412834237 ps
CPU time 1267.74 seconds
Started Jul 18 04:51:35 PM PDT 24
Finished Jul 18 05:12:45 PM PDT 24
Peak memory 281868 kb
Host smart-f4c29022-3f4f-463d-aeec-b12c0a6bce01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752733543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1752733543
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3391702129
Short name T312
Test name
Test status
Simulation time 60995439239 ps
CPU time 1756.01 seconds
Started Jul 18 04:51:34 PM PDT 24
Finished Jul 18 05:20:51 PM PDT 24
Peak memory 273676 kb
Host smart-95e7b9fc-7214-4e4e-b4ec-d4e4053be5c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391702129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3391702129
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.173924742
Short name T613
Test name
Test status
Simulation time 13227920649 ps
CPU time 525.09 seconds
Started Jul 18 04:51:32 PM PDT 24
Finished Jul 18 05:00:18 PM PDT 24
Peak memory 256184 kb
Host smart-a352970e-e0c3-4612-8b71-aef3f77ab04b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173924742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.173924742
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1738796946
Short name T219
Test name
Test status
Simulation time 319251377 ps
CPU time 12.21 seconds
Started Jul 18 04:51:35 PM PDT 24
Finished Jul 18 04:51:48 PM PDT 24
Peak memory 248932 kb
Host smart-f953ccbc-85cf-4434-aee6-d1e9e4459e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17387
96946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1738796946
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3164966267
Short name T217
Test name
Test status
Simulation time 738066213 ps
CPU time 51.88 seconds
Started Jul 18 04:51:34 PM PDT 24
Finished Jul 18 04:52:28 PM PDT 24
Peak memory 257092 kb
Host smart-938688b0-1df4-4042-9cc8-ec6e8982237e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31649
66267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3164966267
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1304252531
Short name T701
Test name
Test status
Simulation time 221693938 ps
CPU time 14.56 seconds
Started Jul 18 04:51:33 PM PDT 24
Finished Jul 18 04:51:49 PM PDT 24
Peak memory 255976 kb
Host smart-5b052857-d61d-487a-a967-9ac7d8e82d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13042
52531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1304252531
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2153191231
Short name T693
Test name
Test status
Simulation time 84117806971 ps
CPU time 5545.62 seconds
Started Jul 18 04:51:35 PM PDT 24
Finished Jul 18 06:24:03 PM PDT 24
Peak memory 322240 kb
Host smart-c744ce31-6449-4dce-be59-c3d442e6a0ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153191231 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2153191231
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3317856777
Short name T130
Test name
Test status
Simulation time 9816979310 ps
CPU time 853.11 seconds
Started Jul 18 04:51:35 PM PDT 24
Finished Jul 18 05:05:50 PM PDT 24
Peak memory 272904 kb
Host smart-5bce90f9-9290-4357-a910-20401b9f6b13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317856777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3317856777
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2122798529
Short name T216
Test name
Test status
Simulation time 2434188373 ps
CPU time 52.21 seconds
Started Jul 18 04:51:37 PM PDT 24
Finished Jul 18 04:52:31 PM PDT 24
Peak memory 256504 kb
Host smart-7e59304f-5074-4f16-9be8-d65c8c9b42bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21227
98529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2122798529
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3010263690
Short name T678
Test name
Test status
Simulation time 76235736 ps
CPU time 2.8 seconds
Started Jul 18 04:51:42 PM PDT 24
Finished Jul 18 04:51:45 PM PDT 24
Peak memory 249632 kb
Host smart-39c545fe-d9ce-46eb-a2d0-541e8f07f345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30102
63690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3010263690
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.4197570094
Short name T336
Test name
Test status
Simulation time 51960628069 ps
CPU time 824.27 seconds
Started Jul 18 04:51:41 PM PDT 24
Finished Jul 18 05:05:26 PM PDT 24
Peak memory 273868 kb
Host smart-420df977-bfcc-4dff-ba46-3ada43525c89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197570094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.4197570094
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2655652058
Short name T399
Test name
Test status
Simulation time 108524241593 ps
CPU time 1747.1 seconds
Started Jul 18 04:51:50 PM PDT 24
Finished Jul 18 05:20:59 PM PDT 24
Peak memory 273616 kb
Host smart-1561f789-56d1-4895-889f-f9c492398682
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655652058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2655652058
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1664203788
Short name T679
Test name
Test status
Simulation time 19545042529 ps
CPU time 437.21 seconds
Started Jul 18 04:51:37 PM PDT 24
Finished Jul 18 04:58:55 PM PDT 24
Peak memory 255916 kb
Host smart-6015b7fb-0860-48e3-b8b0-f0525033dff0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664203788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1664203788
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.391340831
Short name T373
Test name
Test status
Simulation time 75415720 ps
CPU time 7.83 seconds
Started Jul 18 04:51:31 PM PDT 24
Finished Jul 18 04:51:40 PM PDT 24
Peak memory 248832 kb
Host smart-04c326ad-ff87-4160-9bba-c0146ab8cdfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39134
0831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.391340831
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3332124428
Short name T591
Test name
Test status
Simulation time 323194827 ps
CPU time 15.89 seconds
Started Jul 18 04:51:43 PM PDT 24
Finished Jul 18 04:52:00 PM PDT 24
Peak memory 248920 kb
Host smart-3162e489-dce3-4efd-8ff6-c280ba44f665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33321
24428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3332124428
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3701498410
Short name T119
Test name
Test status
Simulation time 1657553474 ps
CPU time 64.29 seconds
Started Jul 18 04:51:41 PM PDT 24
Finished Jul 18 04:52:46 PM PDT 24
Peak memory 249172 kb
Host smart-3ef79e1e-4416-43f3-94b4-f0b9bd313fd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37014
98410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3701498410
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3834852572
Short name T585
Test name
Test status
Simulation time 243655003 ps
CPU time 10.14 seconds
Started Jul 18 04:51:35 PM PDT 24
Finished Jul 18 04:51:47 PM PDT 24
Peak memory 248820 kb
Host smart-25aa502a-8d49-4643-9f1e-9e5e42009d9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38348
52572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3834852572
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1228451312
Short name T592
Test name
Test status
Simulation time 127987872369 ps
CPU time 4370.91 seconds
Started Jul 18 04:51:50 PM PDT 24
Finished Jul 18 06:04:42 PM PDT 24
Peak memory 319640 kb
Host smart-565492b5-36ff-4d66-aeb6-83d87d3f319b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228451312 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1228451312
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2121473211
Short name T427
Test name
Test status
Simulation time 40216735539 ps
CPU time 1098.5 seconds
Started Jul 18 04:51:51 PM PDT 24
Finished Jul 18 05:10:11 PM PDT 24
Peak memory 285120 kb
Host smart-b4288039-2443-4dbe-bc46-088f84336d18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121473211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2121473211
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.723524403
Short name T617
Test name
Test status
Simulation time 1113308594 ps
CPU time 89.71 seconds
Started Jul 18 04:51:49 PM PDT 24
Finished Jul 18 04:53:20 PM PDT 24
Peak memory 256972 kb
Host smart-8439ae97-bd6c-4ae7-aa8f-4215d1662cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72352
4403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.723524403
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2294047885
Short name T394
Test name
Test status
Simulation time 108008857 ps
CPU time 7.26 seconds
Started Jul 18 04:51:53 PM PDT 24
Finished Jul 18 04:52:01 PM PDT 24
Peak memory 248440 kb
Host smart-b1f288b0-1967-416e-8b41-acf3521a1a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22940
47885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2294047885
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1279727936
Short name T337
Test name
Test status
Simulation time 450857288511 ps
CPU time 2449.81 seconds
Started Jul 18 04:51:48 PM PDT 24
Finished Jul 18 05:32:40 PM PDT 24
Peak memory 289216 kb
Host smart-fa0cc3c6-4a36-4d99-bd31-264abc1a3f42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279727936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1279727936
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.58136505
Short name T601
Test name
Test status
Simulation time 74070460388 ps
CPU time 2129.15 seconds
Started Jul 18 04:52:06 PM PDT 24
Finished Jul 18 05:27:37 PM PDT 24
Peak memory 289708 kb
Host smart-e3066b33-2875-4f51-ad85-3a1892403eb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58136505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.58136505
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3183550500
Short name T672
Test name
Test status
Simulation time 20997705353 ps
CPU time 98.47 seconds
Started Jul 18 04:51:53 PM PDT 24
Finished Jul 18 04:53:32 PM PDT 24
Peak memory 248924 kb
Host smart-2fbe85d7-a82f-4bab-bbf9-1d9c30e5aba1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183550500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3183550500
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1319168018
Short name T38
Test name
Test status
Simulation time 976881763 ps
CPU time 52.16 seconds
Started Jul 18 04:51:48 PM PDT 24
Finished Jul 18 04:52:41 PM PDT 24
Peak memory 248892 kb
Host smart-07efb119-e481-453a-aa17-d0886461500b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13191
68018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1319168018
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3512937
Short name T567
Test name
Test status
Simulation time 1382120473 ps
CPU time 37.41 seconds
Started Jul 18 04:51:49 PM PDT 24
Finished Jul 18 04:52:28 PM PDT 24
Peak memory 256488 kb
Host smart-4618f0f0-4472-46f2-be16-05963ae8e462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35129
37 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3512937
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.341013427
Short name T283
Test name
Test status
Simulation time 3485019041 ps
CPU time 21.56 seconds
Started Jul 18 04:51:49 PM PDT 24
Finished Jul 18 04:52:12 PM PDT 24
Peak memory 256180 kb
Host smart-76b3ba84-4013-4f52-8bdb-5764e2542cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34101
3427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.341013427
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2986059575
Short name T253
Test name
Test status
Simulation time 232851972 ps
CPU time 11.51 seconds
Started Jul 18 04:51:50 PM PDT 24
Finished Jul 18 04:52:03 PM PDT 24
Peak memory 256052 kb
Host smart-9449785c-8864-46f5-ae57-6d2710a219c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29860
59575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2986059575
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.147644617
Short name T279
Test name
Test status
Simulation time 283372557926 ps
CPU time 2442.55 seconds
Started Jul 18 04:51:49 PM PDT 24
Finished Jul 18 05:32:33 PM PDT 24
Peak memory 284892 kb
Host smart-f012cb4d-2c99-4898-b8f8-d50687558b08
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147644617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.147644617
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.907647570
Short name T476
Test name
Test status
Simulation time 229096518509 ps
CPU time 3145.69 seconds
Started Jul 18 04:51:51 PM PDT 24
Finished Jul 18 05:44:19 PM PDT 24
Peak memory 289996 kb
Host smart-296cece3-a7a9-400f-a3ad-4eb65c5d5921
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907647570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.907647570
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1744458084
Short name T418
Test name
Test status
Simulation time 421215693 ps
CPU time 36.81 seconds
Started Jul 18 04:51:47 PM PDT 24
Finished Jul 18 04:52:25 PM PDT 24
Peak memory 257168 kb
Host smart-7d630153-4fd9-48cd-b1c4-42ebc7fae5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17444
58084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1744458084
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3945345762
Short name T597
Test name
Test status
Simulation time 393795278 ps
CPU time 5.07 seconds
Started Jul 18 04:51:50 PM PDT 24
Finished Jul 18 04:51:57 PM PDT 24
Peak memory 240260 kb
Host smart-74b8e890-1061-4310-a67c-72ce1ae43eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39453
45762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3945345762
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1199720376
Short name T692
Test name
Test status
Simulation time 8636416613 ps
CPU time 703.55 seconds
Started Jul 18 04:51:50 PM PDT 24
Finished Jul 18 05:03:35 PM PDT 24
Peak memory 266528 kb
Host smart-6ac69267-c945-42d7-a42a-d9accdc6c79d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199720376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1199720376
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1356191233
Short name T558
Test name
Test status
Simulation time 23561300542 ps
CPU time 539.37 seconds
Started Jul 18 04:51:48 PM PDT 24
Finished Jul 18 05:00:48 PM PDT 24
Peak memory 248972 kb
Host smart-951f02df-2cab-4cc0-8843-905f942d2756
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356191233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1356191233
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2011472484
Short name T409
Test name
Test status
Simulation time 1586998864 ps
CPU time 29.21 seconds
Started Jul 18 04:52:05 PM PDT 24
Finished Jul 18 04:52:36 PM PDT 24
Peak memory 256152 kb
Host smart-1a583d11-501e-4191-9e7d-873ff0d6bfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20114
72484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2011472484
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3880851465
Short name T691
Test name
Test status
Simulation time 651836049 ps
CPU time 19.74 seconds
Started Jul 18 04:51:49 PM PDT 24
Finished Jul 18 04:52:10 PM PDT 24
Peak memory 256216 kb
Host smart-eab39ee4-66dd-4441-a087-fe6d286e5738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38808
51465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3880851465
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2053072389
Short name T277
Test name
Test status
Simulation time 495914520 ps
CPU time 38.78 seconds
Started Jul 18 04:52:02 PM PDT 24
Finished Jul 18 04:52:41 PM PDT 24
Peak memory 248884 kb
Host smart-9d420946-19ec-49f2-ae3f-73219ca2a8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20530
72389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2053072389
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2467792330
Short name T400
Test name
Test status
Simulation time 53442615 ps
CPU time 3.98 seconds
Started Jul 18 04:52:05 PM PDT 24
Finished Jul 18 04:52:11 PM PDT 24
Peak memory 251692 kb
Host smart-54d1be1a-6c55-4083-88b1-b146e38aac86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24677
92330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2467792330
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3164580724
Short name T395
Test name
Test status
Simulation time 15170864755 ps
CPU time 1104.38 seconds
Started Jul 18 04:52:02 PM PDT 24
Finished Jul 18 05:10:27 PM PDT 24
Peak memory 272380 kb
Host smart-c5574736-c2c3-42a2-86aa-6a41e9e604b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164580724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3164580724
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.4063920645
Short name T577
Test name
Test status
Simulation time 1518060863 ps
CPU time 67.14 seconds
Started Jul 18 04:52:02 PM PDT 24
Finished Jul 18 04:53:10 PM PDT 24
Peak memory 257024 kb
Host smart-4a92687d-4dfc-430e-8ab1-2f4c61442394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40639
20645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.4063920645
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1952118508
Short name T482
Test name
Test status
Simulation time 733916872 ps
CPU time 46.57 seconds
Started Jul 18 04:51:49 PM PDT 24
Finished Jul 18 04:52:37 PM PDT 24
Peak memory 248884 kb
Host smart-dba48070-d9ee-41df-a6b4-9840c6f54d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19521
18508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1952118508
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3126800764
Short name T505
Test name
Test status
Simulation time 81019904421 ps
CPU time 2154.93 seconds
Started Jul 18 04:51:53 PM PDT 24
Finished Jul 18 05:27:49 PM PDT 24
Peak memory 289928 kb
Host smart-1937cf66-328c-47a6-a4cf-857dda5d0623
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126800764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3126800764
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.692479390
Short name T631
Test name
Test status
Simulation time 73429195970 ps
CPU time 681.12 seconds
Started Jul 18 04:51:50 PM PDT 24
Finished Jul 18 05:03:13 PM PDT 24
Peak memory 273116 kb
Host smart-13293bc8-118c-42ae-8b2f-4debf023573d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692479390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.692479390
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1951069515
Short name T397
Test name
Test status
Simulation time 370727868 ps
CPU time 24.87 seconds
Started Jul 18 04:52:06 PM PDT 24
Finished Jul 18 04:52:33 PM PDT 24
Peak memory 248924 kb
Host smart-4c585c9e-91ea-4983-b3ad-f2b9813bb411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19510
69515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1951069515
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.679660841
Short name T489
Test name
Test status
Simulation time 418847649 ps
CPU time 21.97 seconds
Started Jul 18 04:51:51 PM PDT 24
Finished Jul 18 04:52:15 PM PDT 24
Peak memory 248920 kb
Host smart-519e5344-addd-4b07-b3dd-99a50d58452f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67966
0841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.679660841
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1194070652
Short name T91
Test name
Test status
Simulation time 3502391075 ps
CPU time 33.58 seconds
Started Jul 18 04:51:51 PM PDT 24
Finished Jul 18 04:52:26 PM PDT 24
Peak memory 248704 kb
Host smart-979f2867-6259-40bb-9a1d-de36dd94422b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11940
70652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1194070652
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1247830538
Short name T612
Test name
Test status
Simulation time 3070400515 ps
CPU time 43.6 seconds
Started Jul 18 04:51:48 PM PDT 24
Finished Jul 18 04:52:33 PM PDT 24
Peak memory 256136 kb
Host smart-22f54ea6-02a5-4a31-ad89-4c3f7098142f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12478
30538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1247830538
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3391339159
Short name T51
Test name
Test status
Simulation time 247763010557 ps
CPU time 3881.77 seconds
Started Jul 18 04:52:06 PM PDT 24
Finished Jul 18 05:56:49 PM PDT 24
Peak memory 306336 kb
Host smart-9e19766f-2ac2-49d7-a68d-16f5890ec5c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391339159 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3391339159
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.4082048552
Short name T218
Test name
Test status
Simulation time 9728277231 ps
CPU time 892.42 seconds
Started Jul 18 04:52:07 PM PDT 24
Finished Jul 18 05:07:00 PM PDT 24
Peak memory 289360 kb
Host smart-b341cff5-043d-4068-ad8f-1294bc13f1f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082048552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.4082048552
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.886125579
Short name T467
Test name
Test status
Simulation time 15584993041 ps
CPU time 166.55 seconds
Started Jul 18 04:52:02 PM PDT 24
Finished Jul 18 04:54:49 PM PDT 24
Peak memory 257124 kb
Host smart-433e07ca-4615-495f-a02e-a3751656ddc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88612
5579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.886125579
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3694157911
Short name T538
Test name
Test status
Simulation time 1378790160 ps
CPU time 40.55 seconds
Started Jul 18 04:52:02 PM PDT 24
Finished Jul 18 04:52:44 PM PDT 24
Peak memory 257072 kb
Host smart-5a314f51-6f30-4ee4-a126-dc4959ddff41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36941
57911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3694157911
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.9143141
Short name T354
Test name
Test status
Simulation time 170803682323 ps
CPU time 2369.27 seconds
Started Jul 18 04:52:07 PM PDT 24
Finished Jul 18 05:31:38 PM PDT 24
Peak memory 285596 kb
Host smart-0279be16-6844-42e0-87c8-57062471d9fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9143141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.9143141
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.1194433190
Short name T632
Test name
Test status
Simulation time 23739873780 ps
CPU time 1485.58 seconds
Started Jul 18 04:52:04 PM PDT 24
Finished Jul 18 05:16:51 PM PDT 24
Peak memory 289080 kb
Host smart-0f7c2cd3-3dc3-4a40-84a1-5e4a1f79d295
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194433190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.1194433190
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.4273238518
Short name T5
Test name
Test status
Simulation time 85705792071 ps
CPU time 346.21 seconds
Started Jul 18 04:52:03 PM PDT 24
Finished Jul 18 04:57:50 PM PDT 24
Peak memory 249056 kb
Host smart-70a02bd9-b969-4d27-b9e3-2b52b69d4c13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273238518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.4273238518
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.363587768
Short name T301
Test name
Test status
Simulation time 1520374179 ps
CPU time 23.04 seconds
Started Jul 18 04:52:06 PM PDT 24
Finished Jul 18 04:52:30 PM PDT 24
Peak memory 248920 kb
Host smart-a8da4de6-91e1-474f-b84b-7c397c3a7789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36358
7768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.363587768
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3681006273
Short name T128
Test name
Test status
Simulation time 2843277617 ps
CPU time 35.64 seconds
Started Jul 18 04:52:06 PM PDT 24
Finished Jul 18 04:52:43 PM PDT 24
Peak memory 248904 kb
Host smart-87a19cee-5c89-4738-a7e5-d892e911bae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36810
06273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3681006273
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.4229302650
Short name T545
Test name
Test status
Simulation time 1590164733 ps
CPU time 17.11 seconds
Started Jul 18 04:52:03 PM PDT 24
Finished Jul 18 04:52:21 PM PDT 24
Peak memory 256164 kb
Host smart-1e4f71f7-0ef1-478c-bc83-e1b3801354aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42293
02650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4229302650
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2573059819
Short name T649
Test name
Test status
Simulation time 497524462 ps
CPU time 9.3 seconds
Started Jul 18 04:51:51 PM PDT 24
Finished Jul 18 04:52:02 PM PDT 24
Peak memory 251540 kb
Host smart-239c0889-859f-4c5f-9884-da120afcae2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25730
59819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2573059819
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.353311712
Short name T107
Test name
Test status
Simulation time 44962255182 ps
CPU time 2446.77 seconds
Started Jul 18 04:52:01 PM PDT 24
Finished Jul 18 05:32:49 PM PDT 24
Peak memory 290220 kb
Host smart-97a93f23-53cf-4e7e-a94e-c8dc048bd51a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353311712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han
dler_stress_all.353311712
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.522599062
Short name T548
Test name
Test status
Simulation time 129639233404 ps
CPU time 3902.93 seconds
Started Jul 18 04:52:06 PM PDT 24
Finished Jul 18 05:57:10 PM PDT 24
Peak memory 339296 kb
Host smart-7a7de371-a7e4-47c2-91d8-408844909cf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522599062 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.522599062
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3512799132
Short name T245
Test name
Test status
Simulation time 174985883 ps
CPU time 3.84 seconds
Started Jul 18 04:49:12 PM PDT 24
Finished Jul 18 04:49:18 PM PDT 24
Peak memory 249148 kb
Host smart-8edd8eb0-ced4-48d4-8e42-51bbdb2973cc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3512799132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3512799132
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.870233841
Short name T666
Test name
Test status
Simulation time 8902214138 ps
CPU time 862.68 seconds
Started Jul 18 04:49:15 PM PDT 24
Finished Jul 18 05:03:40 PM PDT 24
Peak memory 281808 kb
Host smart-8f27b284-be85-4890-9720-f08a8792ad4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870233841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.870233841
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2466753410
Short name T576
Test name
Test status
Simulation time 518304552 ps
CPU time 9.31 seconds
Started Jul 18 04:49:18 PM PDT 24
Finished Jul 18 04:49:28 PM PDT 24
Peak memory 248856 kb
Host smart-8e487a18-7efb-4045-a2f6-cea6165bb1ca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2466753410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2466753410
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.154510951
Short name T615
Test name
Test status
Simulation time 17829089727 ps
CPU time 114.8 seconds
Started Jul 18 04:49:11 PM PDT 24
Finished Jul 18 04:51:07 PM PDT 24
Peak memory 257200 kb
Host smart-1ababe6d-76d8-4cf5-87a7-54bd8d130862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15451
0951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.154510951
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1571715601
Short name T529
Test name
Test status
Simulation time 137068166 ps
CPU time 10.86 seconds
Started Jul 18 04:49:14 PM PDT 24
Finished Jul 18 04:49:26 PM PDT 24
Peak memory 257112 kb
Host smart-fd4c7c63-c425-4292-a46a-add481e4271f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15717
15601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1571715601
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3183415650
Short name T347
Test name
Test status
Simulation time 51865483931 ps
CPU time 1243.41 seconds
Started Jul 18 04:49:15 PM PDT 24
Finished Jul 18 05:10:00 PM PDT 24
Peak memory 286028 kb
Host smart-72a5a96d-fb34-4c0c-9e7f-6a3bea77fbbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183415650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3183415650
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2095436271
Short name T391
Test name
Test status
Simulation time 28845947188 ps
CPU time 1908.45 seconds
Started Jul 18 04:49:16 PM PDT 24
Finished Jul 18 05:21:06 PM PDT 24
Peak memory 283360 kb
Host smart-4284ee04-2d9b-40c4-a5f8-da87ffa9ab53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095436271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2095436271
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.703549186
Short name T503
Test name
Test status
Simulation time 29805045315 ps
CPU time 307.13 seconds
Started Jul 18 04:49:12 PM PDT 24
Finished Jul 18 04:54:21 PM PDT 24
Peak memory 248004 kb
Host smart-1c38741d-e5cc-4498-8edd-571665b3fb66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703549186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.703549186
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3951330692
Short name T444
Test name
Test status
Simulation time 255044628 ps
CPU time 16.39 seconds
Started Jul 18 04:49:14 PM PDT 24
Finished Jul 18 04:49:32 PM PDT 24
Peak memory 257044 kb
Host smart-31dd0286-302c-4aca-a8c0-80404549131e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39513
30692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3951330692
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2617959104
Short name T604
Test name
Test status
Simulation time 3374152373 ps
CPU time 53.05 seconds
Started Jul 18 04:49:16 PM PDT 24
Finished Jul 18 04:50:11 PM PDT 24
Peak memory 256696 kb
Host smart-39dd1165-7897-46ef-ad86-3ce69c6a257e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26179
59104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2617959104
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2425800446
Short name T681
Test name
Test status
Simulation time 485041618 ps
CPU time 9.46 seconds
Started Jul 18 04:49:18 PM PDT 24
Finished Jul 18 04:49:28 PM PDT 24
Peak memory 251752 kb
Host smart-6587beb9-3ab0-4eeb-842d-0b49e1d12765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24258
00446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2425800446
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1482589764
Short name T511
Test name
Test status
Simulation time 697404759 ps
CPU time 30.93 seconds
Started Jul 18 04:49:18 PM PDT 24
Finished Jul 18 04:49:50 PM PDT 24
Peak memory 249104 kb
Host smart-226a613c-7bff-4aa7-a5da-5b17eba84856
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14825
89764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1482589764
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.146543879
Short name T582
Test name
Test status
Simulation time 271824752041 ps
CPU time 2842.17 seconds
Started Jul 18 04:49:15 PM PDT 24
Finished Jul 18 05:36:40 PM PDT 24
Peak memory 289660 kb
Host smart-a8b1d11d-d65b-4d53-b861-0b524d804194
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146543879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.146543879
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2505448981
Short name T56
Test name
Test status
Simulation time 38664446155 ps
CPU time 981.87 seconds
Started Jul 18 04:49:11 PM PDT 24
Finished Jul 18 05:05:34 PM PDT 24
Peak memory 273696 kb
Host smart-5c47af56-a530-4bac-bb77-1772d055a53e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505448981 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2505448981
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1467789657
Short name T242
Test name
Test status
Simulation time 44067450 ps
CPU time 3.86 seconds
Started Jul 18 04:49:16 PM PDT 24
Finished Jul 18 04:49:21 PM PDT 24
Peak memory 249120 kb
Host smart-721d24cf-456a-46cb-8799-0ebd18bd4a1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1467789657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1467789657
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.4044852145
Short name T316
Test name
Test status
Simulation time 39314828761 ps
CPU time 2102.81 seconds
Started Jul 18 04:49:18 PM PDT 24
Finished Jul 18 05:24:22 PM PDT 24
Peak memory 281728 kb
Host smart-873938c5-7b5e-4e69-9476-d52c9ef1638b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044852145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.4044852145
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3152459153
Short name T401
Test name
Test status
Simulation time 16861088088 ps
CPU time 225.3 seconds
Started Jul 18 04:49:12 PM PDT 24
Finished Jul 18 04:52:59 PM PDT 24
Peak memory 257308 kb
Host smart-54e056a9-1f07-4036-aa29-198503dac7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31524
59153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3152459153
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2541124927
Short name T389
Test name
Test status
Simulation time 126862022 ps
CPU time 8.06 seconds
Started Jul 18 04:49:15 PM PDT 24
Finished Jul 18 04:49:25 PM PDT 24
Peak memory 248836 kb
Host smart-cfe10d47-ac4b-4530-ab0b-91c01a1057df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25411
24927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2541124927
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1368888689
Short name T663
Test name
Test status
Simulation time 17304183194 ps
CPU time 780.62 seconds
Started Jul 18 04:49:13 PM PDT 24
Finished Jul 18 05:02:15 PM PDT 24
Peak memory 273440 kb
Host smart-9ca90fa6-fc43-4b69-8cc9-965852bcb26d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368888689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1368888689
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3317232341
Short name T329
Test name
Test status
Simulation time 9224851643 ps
CPU time 385.95 seconds
Started Jul 18 04:49:10 PM PDT 24
Finished Jul 18 04:55:37 PM PDT 24
Peak memory 248988 kb
Host smart-41267976-57db-42d1-8d18-f686940838e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317232341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3317232341
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.129006976
Short name T449
Test name
Test status
Simulation time 316906923 ps
CPU time 6.62 seconds
Started Jul 18 04:49:14 PM PDT 24
Finished Jul 18 04:49:22 PM PDT 24
Peak memory 248916 kb
Host smart-216f4153-9a4a-4f2a-b9a7-58aec30556c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12900
6976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.129006976
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2659569754
Short name T413
Test name
Test status
Simulation time 2171533014 ps
CPU time 30.28 seconds
Started Jul 18 04:49:16 PM PDT 24
Finished Jul 18 04:49:48 PM PDT 24
Peak memory 256656 kb
Host smart-43a56ff2-9194-4130-bdfb-9d0e85c85646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26595
69754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2659569754
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.201397661
Short name T58
Test name
Test status
Simulation time 1357428491 ps
CPU time 19.87 seconds
Started Jul 18 04:49:18 PM PDT 24
Finished Jul 18 04:49:39 PM PDT 24
Peak memory 248280 kb
Host smart-8888dc1b-39c3-46c6-b7f2-752685308e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20139
7661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.201397661
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.955694516
Short name T453
Test name
Test status
Simulation time 3073955669 ps
CPU time 42 seconds
Started Jul 18 04:49:11 PM PDT 24
Finished Jul 18 04:49:55 PM PDT 24
Peak memory 257012 kb
Host smart-c4a5425b-00db-4bc2-bf31-d7fb0550c227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95569
4516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.955694516
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2948763288
Short name T575
Test name
Test status
Simulation time 89400760732 ps
CPU time 2530.71 seconds
Started Jul 18 04:49:16 PM PDT 24
Finished Jul 18 05:31:29 PM PDT 24
Peak memory 289644 kb
Host smart-b39e624b-7818-45e8-b87f-5080e13c76fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948763288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2948763288
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1065334792
Short name T72
Test name
Test status
Simulation time 15293213 ps
CPU time 2.66 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 04:49:47 PM PDT 24
Peak memory 249224 kb
Host smart-6d29a2c1-4525-4792-b144-cc285e1229a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1065334792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1065334792
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.4068570873
Short name T655
Test name
Test status
Simulation time 15841848983 ps
CPU time 1041.37 seconds
Started Jul 18 04:49:14 PM PDT 24
Finished Jul 18 05:06:37 PM PDT 24
Peak memory 273064 kb
Host smart-78660ccf-ad62-4d5c-a41f-cf9d4a9157df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068570873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.4068570873
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.110730191
Short name T533
Test name
Test status
Simulation time 1086999199 ps
CPU time 44.13 seconds
Started Jul 18 04:49:37 PM PDT 24
Finished Jul 18 04:50:23 PM PDT 24
Peak memory 248892 kb
Host smart-731e86de-84b2-411e-bb23-2f4efc1b0a09
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=110730191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.110730191
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1729094984
Short name T571
Test name
Test status
Simulation time 3621839734 ps
CPU time 225.04 seconds
Started Jul 18 04:49:15 PM PDT 24
Finished Jul 18 04:53:02 PM PDT 24
Peak memory 256416 kb
Host smart-ccae2dc1-7c55-4593-8c15-685641696a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17290
94984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1729094984
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.133404198
Short name T589
Test name
Test status
Simulation time 374701318 ps
CPU time 33.85 seconds
Started Jul 18 04:49:16 PM PDT 24
Finished Jul 18 04:49:51 PM PDT 24
Peak memory 256944 kb
Host smart-1d690193-f712-4957-a3ea-c9d1ccec6fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13340
4198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.133404198
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.575837516
Short name T341
Test name
Test status
Simulation time 37911877424 ps
CPU time 374.69 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 04:55:59 PM PDT 24
Peak memory 248860 kb
Host smart-69ca83fd-b6a8-4c5e-b101-a9b45e305007
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575837516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.575837516
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3170800723
Short name T292
Test name
Test status
Simulation time 602313455 ps
CPU time 14.87 seconds
Started Jul 18 04:49:18 PM PDT 24
Finished Jul 18 04:49:34 PM PDT 24
Peak memory 248920 kb
Host smart-21b1a155-f35a-4873-835d-768bb5d806b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31708
00723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3170800723
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1839790840
Short name T55
Test name
Test status
Simulation time 1130673001 ps
CPU time 34.03 seconds
Started Jul 18 04:49:14 PM PDT 24
Finished Jul 18 04:49:50 PM PDT 24
Peak memory 248768 kb
Host smart-f66465fd-e13e-4251-88da-4f754ee71c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18397
90840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1839790840
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2107818977
Short name T281
Test name
Test status
Simulation time 320160213 ps
CPU time 19.09 seconds
Started Jul 18 04:49:14 PM PDT 24
Finished Jul 18 04:49:35 PM PDT 24
Peak memory 257084 kb
Host smart-43cbd4ab-8564-4df5-87a2-6e64da1868f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21078
18977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2107818977
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.369217633
Short name T381
Test name
Test status
Simulation time 1355694209 ps
CPU time 27.57 seconds
Started Jul 18 04:49:20 PM PDT 24
Finished Jul 18 04:49:48 PM PDT 24
Peak memory 248908 kb
Host smart-5d04551b-544e-4b4a-9692-cd86dd16a439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36921
7633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.369217633
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2260168412
Short name T299
Test name
Test status
Simulation time 39018427482 ps
CPU time 2562.27 seconds
Started Jul 18 04:49:35 PM PDT 24
Finished Jul 18 05:32:18 PM PDT 24
Peak memory 289932 kb
Host smart-c1eb8ddf-d010-4e92-8339-354ec148e306
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260168412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2260168412
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2954570087
Short name T259
Test name
Test status
Simulation time 62029795035 ps
CPU time 1737.58 seconds
Started Jul 18 04:49:37 PM PDT 24
Finished Jul 18 05:18:36 PM PDT 24
Peak memory 289748 kb
Host smart-4da48948-db65-462d-98ed-c1561051b961
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954570087 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2954570087
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1406956790
Short name T231
Test name
Test status
Simulation time 13436049 ps
CPU time 2.23 seconds
Started Jul 18 04:49:36 PM PDT 24
Finished Jul 18 04:49:40 PM PDT 24
Peak memory 249144 kb
Host smart-15f1ef06-4760-4a0a-91a7-9eab9895df71
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1406956790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1406956790
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1602124889
Short name T436
Test name
Test status
Simulation time 44595633575 ps
CPU time 1814.31 seconds
Started Jul 18 04:49:37 PM PDT 24
Finished Jul 18 05:19:53 PM PDT 24
Peak memory 285696 kb
Host smart-9d0c4da1-c8ca-4d6c-a711-92af841e7310
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602124889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1602124889
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3196557777
Short name T66
Test name
Test status
Simulation time 2410905016 ps
CPU time 13.12 seconds
Started Jul 18 04:49:47 PM PDT 24
Finished Jul 18 04:50:01 PM PDT 24
Peak memory 249036 kb
Host smart-eefe327c-babe-4a8d-a6fd-8c67739da42f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3196557777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3196557777
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2064968789
Short name T689
Test name
Test status
Simulation time 9040333748 ps
CPU time 142.63 seconds
Started Jul 18 04:49:34 PM PDT 24
Finished Jul 18 04:51:58 PM PDT 24
Peak memory 256832 kb
Host smart-368c6423-2932-443d-b3f7-c882646eb88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20649
68789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2064968789
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3759395458
Short name T446
Test name
Test status
Simulation time 1167813926 ps
CPU time 31.73 seconds
Started Jul 18 04:49:40 PM PDT 24
Finished Jul 18 04:50:13 PM PDT 24
Peak memory 248608 kb
Host smart-af4272a3-3354-4991-88bd-0bc5f3a6547d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37593
95458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3759395458
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1236615231
Short name T141
Test name
Test status
Simulation time 24765054182 ps
CPU time 1448.11 seconds
Started Jul 18 04:49:34 PM PDT 24
Finished Jul 18 05:13:43 PM PDT 24
Peak memory 273076 kb
Host smart-df08712e-ef48-4bf9-96df-00b0c50cb5b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236615231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1236615231
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3945368146
Short name T587
Test name
Test status
Simulation time 22186000048 ps
CPU time 954.69 seconds
Started Jul 18 04:49:36 PM PDT 24
Finished Jul 18 05:05:33 PM PDT 24
Peak memory 283688 kb
Host smart-40efa811-764a-45ba-af8c-c7d35bf36f1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945368146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3945368146
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1023102207
Short name T402
Test name
Test status
Simulation time 1030241932 ps
CPU time 63.87 seconds
Started Jul 18 04:49:35 PM PDT 24
Finished Jul 18 04:50:41 PM PDT 24
Peak memory 256568 kb
Host smart-a9bf2bff-bcad-4c91-9d22-3920f66426e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10231
02207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1023102207
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3563938786
Short name T296
Test name
Test status
Simulation time 356174647 ps
CPU time 34.97 seconds
Started Jul 18 04:49:35 PM PDT 24
Finished Jul 18 04:50:11 PM PDT 24
Peak memory 249104 kb
Host smart-103e777e-4367-4487-9c11-cfc3b5d344a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35639
38786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3563938786
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.386266785
Short name T660
Test name
Test status
Simulation time 691365676 ps
CPU time 43.57 seconds
Started Jul 18 04:49:36 PM PDT 24
Finished Jul 18 04:50:21 PM PDT 24
Peak memory 256616 kb
Host smart-ab2ec928-6712-405d-b492-29336d3a9660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38626
6785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.386266785
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.763459505
Short name T573
Test name
Test status
Simulation time 113396016 ps
CPU time 13.26 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 04:49:57 PM PDT 24
Peak memory 249184 kb
Host smart-8ed48f21-0486-4398-8c20-1fcfc36056d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76345
9505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.763459505
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1706429331
Short name T273
Test name
Test status
Simulation time 37522167210 ps
CPU time 2398.22 seconds
Started Jul 18 04:49:38 PM PDT 24
Finished Jul 18 05:29:38 PM PDT 24
Peak memory 289492 kb
Host smart-6243bc05-a174-4157-bdfe-8546a70e8972
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706429331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1706429331
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1418521616
Short name T26
Test name
Test status
Simulation time 29803873508 ps
CPU time 1690.2 seconds
Started Jul 18 04:49:38 PM PDT 24
Finished Jul 18 05:17:50 PM PDT 24
Peak memory 269012 kb
Host smart-b8bc9eec-1232-43b6-9dd5-b95e6614c5cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418521616 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1418521616
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2713331597
Short name T238
Test name
Test status
Simulation time 62364577 ps
CPU time 2.77 seconds
Started Jul 18 04:49:36 PM PDT 24
Finished Jul 18 04:49:41 PM PDT 24
Peak memory 249156 kb
Host smart-b023d7e6-9923-4ef2-8390-6fdf6ac23eca
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2713331597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2713331597
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.4026471204
Short name T636
Test name
Test status
Simulation time 220329931023 ps
CPU time 3483.97 seconds
Started Jul 18 04:49:37 PM PDT 24
Finished Jul 18 05:47:43 PM PDT 24
Peak memory 289560 kb
Host smart-3d4cd54e-fd79-4441-a59e-d1c24c76f3e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026471204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.4026471204
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.4255322650
Short name T499
Test name
Test status
Simulation time 201554200 ps
CPU time 11.17 seconds
Started Jul 18 04:49:38 PM PDT 24
Finished Jul 18 04:49:51 PM PDT 24
Peak memory 248836 kb
Host smart-843bb7a4-6461-49f8-8d24-f2aab945e2c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4255322650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.4255322650
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1344109938
Short name T471
Test name
Test status
Simulation time 1131840680 ps
CPU time 15.02 seconds
Started Jul 18 04:49:36 PM PDT 24
Finished Jul 18 04:49:53 PM PDT 24
Peak memory 254680 kb
Host smart-9eb1b4fd-51b2-4121-976f-777f0f8c5c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13441
09938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1344109938
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3904995449
Short name T605
Test name
Test status
Simulation time 358485541 ps
CPU time 23.4 seconds
Started Jul 18 04:49:35 PM PDT 24
Finished Jul 18 04:50:00 PM PDT 24
Peak memory 256176 kb
Host smart-627c8d1a-b940-4138-be7a-520caf8a5cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39049
95449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3904995449
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.4089552631
Short name T606
Test name
Test status
Simulation time 121074019352 ps
CPU time 1057.69 seconds
Started Jul 18 04:49:35 PM PDT 24
Finished Jul 18 05:07:14 PM PDT 24
Peak memory 271036 kb
Host smart-f8d3cee4-721f-4dc5-8ce3-3ad3a1fa514c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089552631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4089552631
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3247841448
Short name T540
Test name
Test status
Simulation time 104425394045 ps
CPU time 1695.22 seconds
Started Jul 18 04:49:37 PM PDT 24
Finished Jul 18 05:17:54 PM PDT 24
Peak memory 273624 kb
Host smart-309c3d81-1bbc-4045-b6c6-bc2ce97baeca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247841448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3247841448
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.429908717
Short name T323
Test name
Test status
Simulation time 11326828237 ps
CPU time 125.51 seconds
Started Jul 18 04:49:38 PM PDT 24
Finished Jul 18 04:51:45 PM PDT 24
Peak memory 249088 kb
Host smart-e52b3912-62f5-463a-a6ea-1a6e20ff53b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429908717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.429908717
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1818885937
Short name T634
Test name
Test status
Simulation time 2541993128 ps
CPU time 69.61 seconds
Started Jul 18 04:49:38 PM PDT 24
Finished Jul 18 04:50:49 PM PDT 24
Peak memory 256708 kb
Host smart-30917b96-80c8-494a-8470-2673b26379a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18188
85937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1818885937
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2423081915
Short name T688
Test name
Test status
Simulation time 2849463750 ps
CPU time 50.27 seconds
Started Jul 18 04:49:44 PM PDT 24
Finished Jul 18 04:50:36 PM PDT 24
Peak memory 249020 kb
Host smart-121313b0-3e53-4e3e-874d-fc39467c02fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24230
81915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2423081915
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.877330026
Short name T454
Test name
Test status
Simulation time 4332668433 ps
CPU time 54.78 seconds
Started Jul 18 04:49:40 PM PDT 24
Finished Jul 18 04:50:36 PM PDT 24
Peak memory 256768 kb
Host smart-cdf60fc6-845a-4bf6-8577-4107a2eb6ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87733
0026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.877330026
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3355825901
Short name T683
Test name
Test status
Simulation time 1679961506 ps
CPU time 44.28 seconds
Started Jul 18 04:49:43 PM PDT 24
Finished Jul 18 04:50:29 PM PDT 24
Peak memory 256400 kb
Host smart-4f522e30-69da-481c-a8b5-34e93d66594d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33558
25901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3355825901
Directory /workspace/9.alert_handler_smoke/latest
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