Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65127122	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31512755

1

T1

89561

T2

10193

T3

8884

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14574234	1			T1	34490		T2	3920		T3	3445
values[0x0]	40125018	1			T1	124037		T2	14323		T3	12414
values[0x1]	41940625	1			T1	123623		T2	14323		T3	12458

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55763498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40876379

1

T1

113040

T2

12942

T3

11198

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	360882	1			T2	120		T17	4913		T18	9
valid_sources[0x01]	304352	1			T2	27		T17	4829		T18	21
valid_sources[0x02]	330015	1			T2	55		T17	4790		T18	33
valid_sources[0x03]	568297	1			T2	114		T17	4891		T18	11
valid_sources[0x04]	311289	1			T2	93		T17	4813		T18	10
valid_sources[0x05]	311969	1			T2	20		T17	4918		T18	17
valid_sources[0x06]	301542	1			T2	106		T17	4761		T18	8
valid_sources[0x07]	312217	1			T2	113		T17	4830		T20	38
valid_sources[0x08]	296693	1			T2	76		T17	4916		T18	12
valid_sources[0x09]	312968	1			T2	278		T17	5024		T18	20
valid_sources[0x0a]	294184	1			T17	5024		T18	13		T20	40
valid_sources[0x0b]	329342	1			T2	439		T17	4929		T18	20
valid_sources[0x0c]	335744	1			T2	32		T17	4884		T18	21
valid_sources[0x0d]	311753	1			T2	155		T17	5078		T18	19
valid_sources[0x0e]	309396	1			T2	308		T17	4950		T18	16
valid_sources[0x0f]	304244	1			T2	28		T17	5049		T18	1
valid_sources[0x10]	321543	1			T2	67		T17	4888		T18	22
valid_sources[0x11]	306587	1			T2	13		T17	4931		T18	16
valid_sources[0x12]	310529	1			T2	383		T17	5026		T18	37
valid_sources[0x13]	321780	1			T2	139		T17	4821		T18	34
valid_sources[0x14]	308802	1			T2	230		T17	4884		T18	44
valid_sources[0x15]	312013	1			T2	99		T17	4907		T20	25
valid_sources[0x16]	320178	1			T2	121		T17	4956		T18	1
valid_sources[0x17]	305201	1			T2	96		T17	4743		T18	9
valid_sources[0x18]	599915	1			T2	96		T17	4963		T18	4
valid_sources[0x19]	322861	1			T2	149		T17	4870		T18	35
valid_sources[0x1a]	298603	1			T2	83		T17	4781		T18	3
valid_sources[0x1b]	609176	1			T2	270		T17	4952		T18	8
valid_sources[0x1c]	309055	1			T2	167		T17	4917		T18	7
valid_sources[0x1d]	330041	1			T2	55		T17	4833		T18	20
valid_sources[0x1e]	304798	1			T2	167		T17	4918		T18	15
valid_sources[0x1f]	317861	1			T2	37		T17	4930		T18	16
valid_sources[0x20]	317318	1			T2	95		T17	4976		T18	6
valid_sources[0x21]	307463	1			T2	159		T17	4912		T18	20
valid_sources[0x22]	315589	1			T2	1		T17	4923		T18	5
valid_sources[0x23]	349062	1			T2	35		T17	4933		T20	41
valid_sources[0x24]	325504	1			T17	4943		T18	8		T20	24
valid_sources[0x25]	317726	1			T2	367		T17	5026		T18	18
valid_sources[0x26]	766536	1			T2	346		T17	4753		T18	29
valid_sources[0x27]	308691	1			T2	131		T17	4888		T18	19
valid_sources[0x28]	333170	1			T2	132		T17	4969		T18	1
valid_sources[0x29]	305410	1			T2	7		T17	4844		T18	24
valid_sources[0x2a]	344255	1			T2	165		T17	5046		T18	12
valid_sources[0x2b]	323612	1			T2	63		T17	4960		T18	3
valid_sources[0x2c]	309688	1			T2	123		T17	5087		T18	16
valid_sources[0x2d]	301408	1			T2	15		T17	4973		T20	20
valid_sources[0x2e]	322410	1			T2	40		T17	5004		T18	9
valid_sources[0x2f]	314921	1			T2	101		T17	4977		T18	7
valid_sources[0x30]	303822	1			T2	280		T17	4764		T18	10
valid_sources[0x31]	302858	1			T2	119		T17	5011		T18	5
valid_sources[0x32]	360661	1			T2	292		T17	4856		T18	29
valid_sources[0x33]	315995	1			T2	89		T17	4798		T18	17
valid_sources[0x34]	512076	1			T2	128		T17	4890		T18	4
valid_sources[0x35]	313194	1			T2	40		T17	4843		T18	7
valid_sources[0x36]	333287	1			T2	27		T17	4796		T18	2
valid_sources[0x37]	300255	1			T17	4942		T18	16		T20	25
valid_sources[0x38]	324295	1			T17	5057		T18	2		T20	25
valid_sources[0x39]	323595	1			T2	81		T17	4843		T18	15
valid_sources[0x3a]	348386	1			T2	72		T17	4917		T18	8
valid_sources[0x3b]	309987	1			T2	185		T17	4912		T18	19
valid_sources[0x3c]	306461	1			T17	4817		T18	5		T20	30
valid_sources[0x3d]	335748	1			T2	39		T17	4796		T18	13
valid_sources[0x3e]	319364	1			T2	152		T17	4776		T18	5
valid_sources[0x3f]	292264	1			T17	4929		T18	18		T20	40
valid_sources[0x40]	324454	1			T2	436		T17	4900		T18	16
valid_sources[0x41]	631656	1			T2	142		T17	4877		T18	16
valid_sources[0x42]	316597	1			T2	156		T17	4860		T20	43
valid_sources[0x43]	309852	1			T2	153		T17	4855		T18	3
valid_sources[0x44]	308263	1			T2	131		T17	4933		T18	7
valid_sources[0x45]	313734	1			T2	14		T17	4700		T18	4
valid_sources[0x46]	717718	1			T2	7		T17	4817		T18	20
valid_sources[0x47]	321024	1			T2	100		T17	4982		T18	14
valid_sources[0x48]	312770	1			T2	693		T17	4922		T18	8
valid_sources[0x49]	627250	1			T2	49		T17	4837		T18	13
valid_sources[0x4a]	302747	1			T2	62		T17	4866		T18	39
valid_sources[0x4b]	543115	1			T2	227		T17	4946		T18	8
valid_sources[0x4c]	346158	1			T2	41		T17	4751		T18	21
valid_sources[0x4d]	327850	1			T2	49		T17	4935		T18	3
valid_sources[0x4e]	325329	1			T2	96		T17	4872		T18	5
valid_sources[0x4f]	311346	1			T2	213		T17	4944		T18	17
valid_sources[0x50]	308831	1			T2	159		T17	4957		T18	5
valid_sources[0x51]	308910	1			T2	199		T17	4904		T18	6
valid_sources[0x52]	343989	1			T2	144		T17	4802		T18	8
valid_sources[0x53]	326607	1			T2	204		T17	4826		T18	10
valid_sources[0x54]	305950	1			T17	4780		T18	6		T20	35
valid_sources[0x55]	816617	1			T1	282150		T2	77		T17	4955
valid_sources[0x56]	307029	1			T2	99		T17	4948		T20	27
valid_sources[0x57]	320272	1			T2	20		T17	5075		T20	27
valid_sources[0x58]	305425	1			T2	60		T17	4950		T18	11
valid_sources[0x59]	318394	1			T2	343		T17	5053		T18	27
valid_sources[0x5a]	798154	1			T2	139		T17	4948		T18	8
valid_sources[0x5b]	305147	1			T2	21		T17	4869		T18	12
valid_sources[0x5c]	308807	1			T2	166		T17	4922		T18	12
valid_sources[0x5d]	315922	1			T2	263		T17	4902		T18	2
valid_sources[0x5e]	721027	1			T2	74		T17	5024		T18	3
valid_sources[0x5f]	302183	1			T2	4		T17	4892		T18	20
valid_sources[0x60]	599463	1			T2	41		T17	4832		T18	38
valid_sources[0x61]	311512	1			T2	27		T17	5043		T18	3
valid_sources[0x62]	312669	1			T2	67		T17	4751		T18	1
valid_sources[0x63]	319560	1			T2	248		T17	4870		T18	11
valid_sources[0x64]	307546	1			T2	57		T17	4905		T18	6
valid_sources[0x65]	328408	1			T2	62		T17	4865		T18	5
valid_sources[0x66]	315034	1			T2	5		T17	4800		T18	10
valid_sources[0x67]	718640	1			T2	3		T17	4842		T18	8
valid_sources[0x68]	311544	1			T2	191		T17	4853		T18	3
valid_sources[0x69]	317036	1			T2	71		T17	5050		T18	26
valid_sources[0x6a]	619185	1			T2	91		T17	5009		T18	8
valid_sources[0x6b]	814952	1			T2	147		T17	4984		T18	25
valid_sources[0x6c]	718711	1			T2	6		T17	4866		T18	16
valid_sources[0x6d]	312313	1			T2	317		T17	4811		T18	18
valid_sources[0x6e]	638804	1			T2	108		T17	4979		T18	12
valid_sources[0x6f]	316127	1			T2	187		T17	4777		T18	3
valid_sources[0x70]	311503	1			T2	22		T17	4882		T18	4
valid_sources[0x71]	312297	1			T2	90		T17	4887		T18	2
valid_sources[0x72]	320311	1			T2	183		T17	4971		T18	8
valid_sources[0x73]	317303	1			T17	4922		T18	23		T20	36
valid_sources[0x74]	302758	1			T2	24		T17	4787		T18	10
valid_sources[0x75]	300837	1			T2	427		T17	4842		T18	11
valid_sources[0x76]	319380	1			T2	199		T17	4899		T18	16
valid_sources[0x77]	314152	1			T2	164		T17	4898		T18	2
valid_sources[0x78]	305065	1			T2	93		T17	4915		T18	24
valid_sources[0x79]	322158	1			T2	117		T17	4908		T18	20
valid_sources[0x7a]	318412	1			T2	56		T17	4952		T18	5
valid_sources[0x7b]	314887	1			T2	148		T17	4840		T18	16
valid_sources[0x7c]	319404	1			T2	114		T17	4844		T18	8
valid_sources[0x7d]	1086898	1			T2	41		T17	4955		T18	8
valid_sources[0x7e]	306383	1			T2	229		T17	4868		T18	4
valid_sources[0x7f]	326323	1			T2	190		T17	4939		T18	2
valid_sources[0x80]	308817	1			T2	160		T17	4790		T18	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7255862

1

T1

17356

T2

1931

T3

1707

values[0x0]

all_enables

biggest_size

15332117

1

T1

46278

T2

5291

T3

4529

values[0x1]

all_enables

biggest_size

8924776

1

T1

25927

T2

2971

T3

2648