Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T100,T203,T204
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13843	0	0
DisabledNoTrigBkwd_A	2147483647	757151	0	0
DisabledNoTrigFwd_A	2147483647	1542812493	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13843	0	0
T32	17524	0	0	0
T65	190683	0	0	0
T66	358745	0	0	0
T67	108818	0	0	0
T69	83268	0	0	0
T70	780260	0	0	0
T75	92037	0	0	0
T79	147730	0	0	0
T100	3000	631	0	0
T101	66368	0	0	0
T102	149931	0	0	0
T196	139170	0	0	0
T197	135769	0	0	0
T201	315729	0	0	0
T203	3544	627	0	0
T204	2628	563	0	0
T205	0	938	0	0
T206	0	656	0	0
T207	0	873	0	0
T208	0	1210	0	0
T209	0	655	0	0
T210	0	644	0	0
T211	0	553	0	0
T212	0	757	0	0
T213	0	886	0	0
T214	0	1060	0	0
T215	0	120	0	0
T216	0	776	0	0
T217	0	1096	0	0
T218	0	172	0	0
T219	0	259	0	0
T220	0	767	0	0
T221	0	600	0	0
T222	60099	0	0	0
T223	23072	0	0	0
T224	4312	0	0	0
T225	4185	0	0	0
T226	722626	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	757151	0	0
T1	1623760	774	0	0
T2	884508	112	0	0
T3	1042804	129	0	0
T4	2130220	9	0	0
T5	496304	583	0	0
T6	0	4492	0	0
T7	406936	4453	0	0
T8	0	3	0	0
T14	0	1845	0	0
T17	533672	6190	0	0
T18	152040	0	0	0
T19	1320464	32	0	0
T20	88572	487	0	0
T21	3273712	9	0	0
T22	400412	69	0	0
T24	0	22	0	0
T28	0	25	0	0
T29	0	631	0	0
T39	0	654	0	0
T40	0	73	0	0
T41	0	69	0	0
T44	0	124	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1542812493	0	0
T1	3247520	1624039	0	0
T2	1179344	861703	0	0
T3	1042804	521099	0	0
T4	2130220	937037	0	0
T17	533672	2596601	0	0
T18	152040	84631	0	0
T19	1320464	583410	0	0
T20	88572	47759	0	0
T21	3273712	2900640	0	0
T22	400412	222407	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T2,T3,T17
1	1	Covered	T1,T3,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T203,T205,T206
1	1	Covered	T1,T3,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	672804857	4922	0	0
DisabledNoTrigBkwd_A	672804857	272049	0	0
DisabledNoTrigFwd_A	672804857	338939636	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	4922	0	0
T67	108818	0	0	0
T197	135769	0	0	0
T201	315729	0	0	0
T203	1772	627	0	0
T204	1314	0	0	0
T205	0	938	0	0
T206	0	656	0	0
T208	0	1210	0	0
T214	0	1060	0	0
T218	0	172	0	0
T219	0	259	0	0
T222	60099	0	0	0
T223	23072	0	0	0
T224	4312	0	0	0
T225	4185	0	0	0
T226	361313	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	272049	0	0
T1	811880	268	0	0
T2	294836	0	0	0
T3	260701	87	0	0
T4	532555	9	0	0
T7	0	1418	0	0
T17	133418	3868	0	0
T18	38010	0	0	0
T19	330116	19	0	0
T20	22143	476	0	0
T21	818428	9	0	0
T22	100103	69	0	0
T28	0	19	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	338939636	0	0
T1	811880	830	0	0
T2	294836	294752	0	0
T3	260701	9004	0	0
T4	532555	582	0	0
T17	133418	863366	0	0
T18	38010	21770	0	0
T19	330116	149632	0	0
T20	22143	582	0	0
T21	818428	631818	0	0
T22	100103	20199	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T100,T210,T213
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T17,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	672804857	2281	0	0
DisabledNoTrigBkwd_A	672804857	183222	0	0
DisabledNoTrigFwd_A	672804857	384009217	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	2281	0	0
T32	17524	0	0	0
T65	190683	0	0	0
T66	358745	0	0	0
T69	83268	0	0	0
T79	147730	0	0	0
T100	3000	631	0	0
T101	66368	0	0	0
T102	149931	0	0	0
T196	139170	0	0	0
T203	1772	0	0	0
T210	0	644	0	0
T213	0	886	0	0
T215	0	120	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	183222	0	0
T3	260701	2	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	1779	0	0
T7	406936	2054	0	0
T14	0	1843	0	0
T17	133418	1220	0	0
T18	38010	0	0	0
T19	330116	13	0	0
T20	22143	11	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T24	0	19	0	0
T39	0	65	0	0
T40	0	33	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	384009217	0	0
T1	811880	810541	0	0
T2	294836	270186	0	0
T3	260701	256419	0	0
T4	532555	467333	0	0
T17	133418	855509	0	0
T18	38010	3123	0	0
T19	330116	51974	0	0
T20	22143	3047	0	0
T21	818428	736778	0	0
T22	100103	8519	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T2,T3,T17
1	1	Covered	T1,T3,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T204,T211,T212
1	1	Covered	T1,T3,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T17,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	672804857	2473	0	0
DisabledNoTrigBkwd_A	672804857	145422	0	0
DisabledNoTrigFwd_A	672804857	414110683	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	2473	0	0
T27	409778	0	0	0
T46	113530	0	0	0
T70	780260	0	0	0
T71	71891	0	0	0
T75	92037	0	0	0
T76	192424	0	0	0
T77	104252	0	0	0
T119	30715	0	0	0
T204	1314	563	0	0
T211	0	553	0	0
T212	0	757	0	0
T221	0	600	0	0
T226	361313	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	145422	0	0
T1	811880	506	0	0
T2	294836	0	0	0
T3	260701	0	0	0
T4	532555	0	0	0
T5	0	583	0	0
T6	0	2	0	0
T7	0	981	0	0
T14	0	2	0	0
T17	133418	79	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T28	0	6	0	0
T39	0	463	0	0
T40	0	18	0	0
T44	0	124	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	414110683	0	0
T1	811880	838	0	0
T2	294836	294752	0	0
T3	260701	253610	0	0
T4	532555	590	0	0
T17	133418	129693	0	0
T18	38010	37911	0	0
T19	330116	329761	0	0
T20	22143	22065	0	0
T21	818428	723877	0	0
T22	100103	100013	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T1,T17,T18
1	1	Covered	T2,T3,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T209,T216
1	1	Covered	T2,T3,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	672804857	4167	0	0
DisabledNoTrigBkwd_A	672804857	156458	0	0
DisabledNoTrigFwd_A	672804857	405752957	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	4167	0	0
T73	96543	0	0	0
T207	1705	873	0	0
T208	3669	0	0	0
T209	0	655	0	0
T216	0	776	0	0
T217	0	1096	0	0
T220	0	767	0	0
T227	28104	0	0	0
T228	75486	0	0	0
T229	21777	0	0	0
T230	22203	0	0	0
T231	9806	0	0	0
T232	34783	0	0	0
T233	342952	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	156458	0	0
T2	294836	112	0	0
T3	260701	40	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	2711	0	0
T8	0	3	0	0
T17	133418	1023	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T24	0	3	0	0
T29	0	631	0	0
T39	0	126	0	0
T40	0	22	0	0
T41	0	69	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	405752957	0	0
T1	811880	811830	0	0
T2	294836	2013	0	0
T3	260701	2066	0	0
T4	532555	468532	0	0
T17	133418	748033	0	0
T18	38010	21827	0	0
T19	330116	52043	0	0
T20	22143	22065	0	0
T21	818428	808167	0	0
T22	100103	93676	0	0