Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T23
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T1,T3,T17
1	1	0	Covered	T17,T18,T19
1	1	1	Covered	T17,T18,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T7,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T17,T7,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T25,T26
1	1	Covered	T17,T18,T19

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T17,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T1,T17,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T3,T17,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T17

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T17,T18,T19

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T17,T18,T19
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T17,T7,T27
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T7,T28,T29
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T27,T30,T31
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T24,T32,T33
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T17,T18,T19
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T17,T18,T19
TimeoutSt->Phase0St	172	Covered	T17,T18,T19

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T35,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T28,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T30,T31
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T32,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T18,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1206	0	0
CheckAccumTrig0_A	2147483647	2378	0	0
CheckAccumTrig1_A	2147483647	112	0	0
CheckClr_A	2147483647	1125	0	0
CheckEn_A	2147483647	1201391704	0	0
CheckPhase0_A	2147483647	2709	0	0
CheckPhase1_A	2147483647	2650	0	0
CheckPhase2_A	2147483647	2609	0	0
CheckPhase3_A	2147483647	2561	0	0
CheckTimeout0_A	2147483647	3989	0	0
CheckTimeoutSt1_A	2147483647	462367	0	0
CheckTimeoutSt2_A	2147483647	3608	0	0
CheckTimeoutStTrig_A	2147483647	262	0	0
ErrorStAllEscAsserted_A	2147483647	5937	0	0
ErrorStIsTerminal_A	2147483647	4977	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1206	0	0
T8	3935132	0	0	0
T11	164880	248	0	0
T12	0	186	0	0
T13	0	332	0	0
T15	2683920	0	0	0
T24	81120	0	0	0
T29	1686244	0	0	0
T37	0	162	0	0
T38	0	278	0	0
T39	1654700	0	0	0
T40	375104	0	0	0
T41	607840	0	0	0
T42	177532	0	0	0
T43	74096	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2378	0	0
T1	1623760	2	0	0
T2	884508	1	0	0
T3	1042804	3	0	0
T4	2130220	1	0	0
T5	496304	2	0	0
T6	0	3	0	0
T7	406936	11	0	0
T8	0	1	0	0
T14	0	2	0	0
T17	533672	11	0	0
T18	152040	0	0	0
T19	1320464	3	0	0
T20	88572	4	0	0
T21	3273712	6	0	0
T22	400412	1	0	0
T24	0	3	0	0
T28	0	8	0	0
T29	0	1	0	0
T39	0	6	0	0
T40	0	7	0	0
T41	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	112	0	0
T4	1065110	0	0	0
T5	496304	0	0	0
T7	813872	1	0	0
T15	1341960	0	0	0
T16	108234	0	0	0
T17	266836	2	0	0
T18	76020	0	0	0
T19	660232	0	0	0
T20	44286	0	0	0
T21	1636856	0	0	0
T22	200206	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T27	0	5	0	0
T28	191122	0	0	0
T29	843122	1	0	0
T33	0	2	0	0
T39	413675	0	0	0
T42	88766	0	0	0
T43	37048	0	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	223822	0	0	0
T60	14384	0	0	0
T61	12351	0	0	0
T62	10460	0	0	0
T63	24034	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1125	0	0
T4	1065110	0	0	0
T5	744456	1	0	0
T6	847784	1	0	0
T7	1220808	3	0	0
T8	983783	0	0	0
T9	0	14	0	0
T14	800847	0	0	0
T15	0	2	0	0
T17	133418	5	0	0
T18	76020	1	0	0
T19	660232	0	0	0
T20	66429	4	0	0
T21	2455284	4	0	0
T22	300309	0	0	0
T24	20280	3	0	0
T28	286683	7	0	0
T29	421561	15	0	0
T39	413675	1	0	0
T40	93776	4	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T44	357176	0	0	0
T59	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T64	0	9	0	0
T65	0	1	0	0
T66	0	3	0	0
T67	0	2	0	0
T68	41992	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1201391704	0	0
T1	3247520	1624037	0	0
T2	1179344	861700	0	0
T3	1042804	277173	0	0
T4	2130220	937035	0	0
T17	533672	2595029	0	0
T18	152040	84630	0	0
T19	1320464	583400	0	0
T20	88572	47757	0	0
T21	3273712	2276920	0	0
T22	400412	222405	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2709	0	0
T1	1623760	2	0	0
T2	884508	1	0	0
T3	1042804	3	0	0
T4	2130220	1	0	0
T5	496304	2	0	0
T6	0	3	0	0
T7	406936	12	0	0
T8	0	1	0	0
T14	0	2	0	0
T17	533672	14	0	0
T18	152040	2	0	0
T19	1320464	4	0	0
T20	88572	6	0	0
T21	3273712	7	0	0
T22	400412	1	0	0
T28	0	8	0	0
T39	0	7	0	0
T40	0	5	0	0
T41	0	1	0	0
T44	0	1	0	0
T68	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2650	0	0
T1	1623760	2	0	0
T2	884508	1	0	0
T3	1042804	3	0	0
T4	2130220	1	0	0
T5	496304	2	0	0
T6	0	3	0	0
T7	406936	10	0	0
T8	0	1	0	0
T14	0	2	0	0
T17	533672	14	0	0
T18	152040	2	0	0
T19	1320464	4	0	0
T20	88572	6	0	0
T21	3273712	7	0	0
T22	400412	1	0	0
T28	0	7	0	0
T39	0	7	0	0
T40	0	5	0	0
T41	0	1	0	0
T44	0	1	0	0
T68	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2609	0	0
T1	1623760	2	0	0
T2	884508	1	0	0
T3	1042804	3	0	0
T4	2130220	1	0	0
T5	496304	2	0	0
T6	0	3	0	0
T7	406936	10	0	0
T8	0	1	0	0
T14	0	2	0	0
T17	533672	14	0	0
T18	152040	2	0	0
T19	1320464	4	0	0
T20	88572	6	0	0
T21	3273712	7	0	0
T22	400412	1	0	0
T28	0	7	0	0
T39	0	7	0	0
T40	0	5	0	0
T41	0	1	0	0
T44	0	1	0	0
T68	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2561	0	0
T1	1623760	2	0	0
T2	884508	1	0	0
T3	1042804	3	0	0
T4	2130220	1	0	0
T5	496304	2	0	0
T6	0	3	0	0
T7	406936	10	0	0
T8	0	1	0	0
T14	0	2	0	0
T17	533672	14	0	0
T18	152040	2	0	0
T19	1320464	4	0	0
T20	88572	6	0	0
T21	3273712	7	0	0
T22	400412	1	0	0
T28	0	7	0	0
T39	0	7	0	0
T40	0	5	0	0
T41	0	1	0	0
T44	0	1	0	0
T68	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3989	0	0
T4	2130220	0	0	0
T5	992608	0	0	0
T7	1627744	6	0	0
T15	0	2	0	0
T17	533672	149	0	0
T18	152040	5	0	0
T19	1320464	21	0	0
T20	88572	5	0	0
T21	3273712	20	0	0
T22	400412	0	0	0
T24	0	2	0	0
T25	0	56	0	0
T28	382244	4	0	0
T29	0	9	0	0
T39	0	21	0	0
T40	0	5	0	0
T42	0	1	0	0
T43	0	1	0	0
T60	0	1	0	0
T63	0	1	0	0
T68	0	6	0	0
T69	0	1	0	0
T70	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	462367	0	0
T4	2130220	0	0	0
T5	992608	0	0	0
T7	1627744	278	0	0
T15	0	81	0	0
T17	533672	24717	0	0
T18	152040	923	0	0
T19	1320464	4870	0	0
T20	88572	1230	0	0
T21	3273712	3714	0	0
T22	400412	0	0	0
T24	0	153	0	0
T25	0	3211	0	0
T28	382244	515	0	0
T29	0	1132	0	0
T39	0	3006	0	0
T40	0	686	0	0
T42	0	180	0	0
T43	0	179	0	0
T46	0	1123	0	0
T60	0	146	0	0
T68	0	961	0	0
T69	0	160	0	0
T70	0	1727	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3608	0	0
T4	2130220	0	0	0
T5	992608	0	0	0
T7	1627744	4	0	0
T15	0	3	0	0
T17	533672	144	0	0
T18	152040	3	0	0
T19	1320464	20	0	0
T20	88572	3	0	0
T21	3273712	19	0	0
T22	400412	0	0	0
T24	0	1	0	0
T25	0	55	0	0
T28	382244	4	0	0
T29	0	8	0	0
T39	0	20	0	0
T40	0	5	0	0
T42	0	1	0	0
T43	0	4	0	0
T46	0	10	0	0
T60	0	1	0	0
T68	0	4	0	0
T69	0	1	0	0
T70	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	262	0	0
T4	532555	0	0	0
T5	496304	0	0	0
T6	423892	0	0	0
T7	813872	1	0	0
T14	800847	0	0	0
T17	133418	2	0	0
T18	38010	2	0	0
T19	330116	1	0	0
T20	44286	2	0	0
T21	1636856	1	0	0
T22	200206	0	0	0
T25	0	3	0	0
T27	409778	3	0	0
T28	191122	0	0	0
T33	0	4	0	0
T44	357176	0	0	0
T46	113530	2	0	0
T47	0	5	0	0
T48	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T67	0	1	0	0
T68	41992	2	0	0
T70	780260	4	0	0
T71	71891	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	92037	0	0	0
T76	192424	0	0	0
T77	104252	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5937	0	0
T8	3935132	0	0	0
T11	164880	1516	0	0
T12	0	766	0	0
T13	0	1449	0	0
T15	2683920	0	0	0
T24	81120	0	0	0
T29	1686244	0	0	0
T37	0	764	0	0
T38	0	1442	0	0
T39	1654700	0	0	0
T40	375104	0	0	0
T41	607840	0	0	0
T42	177532	0	0	0
T43	74096	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4977	0	0
T8	3935132	0	0	0
T11	164880	1276	0	0
T12	0	646	0	0
T13	0	1209	0	0
T15	2683920	0	0	0
T24	81120	0	0	0
T29	1686244	0	0	0
T37	0	644	0	0
T38	0	1202	0	0
T39	1654700	0	0	0
T40	375104	0	0	0
T41	607840	0	0	0
T42	177532	0	0	0
T43	74096	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3247520	3247320	0	0
T2	1179344	1179008	0	0
T3	1042804	1042496	0	0
T4	2130220	2129864	0	0
T17	533672	533668	0	0
T18	152040	151644	0	0
T19	1320464	1319044	0	0
T20	88572	88260	0	0
T21	3273712	3272560	0	0
T22	400412	400052	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3247520	3247320	0	0
T2	1179344	1179008	0	0
T3	1042804	1042496	0	0
T4	2130220	2129864	0	0
T17	533672	533668	0	0
T18	152040	151644	0	0
T19	1320464	1319044	0	0
T20	88572	88260	0	0
T21	3273712	3272560	0	0
T22	400412	400052	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T1,T3,T17
1	1	0	Covered	T17,T18,T19
1	1	1	Covered	T17,T18,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T20
0	1	Covered	T20,T21,T7
1	0	Covered	T17,T7,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T18,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T7,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T20
1	0	Not Covered
1	1	Covered	T20,T21,T7

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T19
1	Covered	T3,T20,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T19
1	Covered	T1,T17,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T17,T19,T21

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T17,T20,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T17
Phase1St	198	Covered	T1,T3,T17
Phase2St	215	Covered	T1,T3,T17
Phase3St	233	Covered	T1,T3,T17
TerminalSt	249	Covered	T1,T3,T17
TimeoutSt	159	Covered	T17,T18,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T3,T17
IdleSt->TimeoutSt	159	Covered	T17,T18,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T17,T35,T31
Phase0St->Phase1St	198	Covered	T1,T3,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T7,T28,T25
Phase1St->Phase2St	215	Covered	T1,T3,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T30,T50
Phase2St->Phase3St	233	Covered	T1,T3,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T32,T33,T35
Phase3St->TerminalSt	249	Covered	T1,T3,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T17,T19,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T17,T18,T20
TimeoutSt->Phase0St	172	Covered	T17,T20,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T20,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T35,T78,T50
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T28,T25
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T30,T50
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T32,T33,T35
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T21,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	672804857	269	0	0
CheckAccumTrig0_A	672804857	919	0	0
CheckAccumTrig1_A	672804857	48	0	0
CheckClr_A	672804857	480	0	0
CheckEn_A	672560726	259848502	0	0
CheckPhase0_A	672804857	1017	0	0
CheckPhase1_A	672804857	990	0	0
CheckPhase2_A	672804857	973	0	0
CheckPhase3_A	672804857	953	0	0
CheckTimeout0_A	672804857	1275	0	0
CheckTimeoutSt1_A	672804857	143964	0	0
CheckTimeoutSt2_A	672804857	1155	0	0
CheckTimeoutStTrig_A	672804857	69	0	0
ErrorStAllEscAsserted_A	672804857	1470	0	0
ErrorStIsTerminal_A	672804857	1230	0	0
EscStateOut_A	672558843	672485818	0	0
u_state_regs_A	672804857	672629808	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	269	0	0
T8	983783	0	0	0
T11	41220	49	0	0
T12	0	49	0	0
T13	0	73	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	41	0	0
T38	0	57	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	919	0	0
T1	811880	1	0	0
T2	294836	0	0	0
T3	260701	1	0	0
T4	532555	1	0	0
T7	0	5	0	0
T17	133418	3	0	0
T18	38010	0	0	0
T19	330116	2	0	0
T20	22143	3	0	0
T21	818428	6	0	0
T22	100103	1	0	0
T28	0	7	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	48	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	1	0	0
T17	133418	1	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T24	0	1	0	0
T27	0	3	0	0
T28	95561	0	0	0
T33	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	480	0	0
T5	248152	0	0	0
T6	423892	1	0	0
T7	406936	3	0	0
T14	800847	0	0	0
T15	0	1	0	0
T20	22143	3	0	0
T21	818428	4	0	0
T22	100103	0	0	0
T24	0	2	0	0
T28	95561	7	0	0
T29	0	1	0	0
T39	0	1	0	0
T44	357176	0	0	0
T59	0	2	0	0
T68	41992	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672560726	259848502	0	0
T1	811880	830	0	0
T2	294836	294751	0	0
T3	260701	9004	0	0
T4	532555	582	0	0
T17	133418	861796	0	0
T18	38010	21770	0	0
T19	330116	149630	0	0
T20	22143	582	0	0
T21	818428	8108	0	0
T22	100103	20199	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1017	0	0
T1	811880	1	0	0
T2	294836	0	0	0
T3	260701	1	0	0
T4	532555	1	0	0
T7	0	7	0	0
T17	133418	3	0	0
T18	38010	0	0	0
T19	330116	2	0	0
T20	22143	4	0	0
T21	818428	7	0	0
T22	100103	1	0	0
T28	0	7	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	990	0	0
T1	811880	1	0	0
T2	294836	0	0	0
T3	260701	1	0	0
T4	532555	1	0	0
T7	0	5	0	0
T17	133418	3	0	0
T18	38010	0	0	0
T19	330116	2	0	0
T20	22143	4	0	0
T21	818428	7	0	0
T22	100103	1	0	0
T28	0	6	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	973	0	0
T1	811880	1	0	0
T2	294836	0	0	0
T3	260701	1	0	0
T4	532555	1	0	0
T7	0	5	0	0
T17	133418	3	0	0
T18	38010	0	0	0
T19	330116	2	0	0
T20	22143	4	0	0
T21	818428	7	0	0
T22	100103	1	0	0
T28	0	6	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	953	0	0
T1	811880	1	0	0
T2	294836	0	0	0
T3	260701	1	0	0
T4	532555	1	0	0
T7	0	5	0	0
T17	133418	3	0	0
T18	38010	0	0	0
T19	330116	2	0	0
T20	22143	4	0	0
T21	818428	7	0	0
T22	100103	1	0	0
T28	0	6	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1275	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	3	0	0
T17	133418	76	0	0
T18	38010	1	0	0
T19	330116	0	0	0
T20	22143	3	0	0
T21	818428	2	0	0
T22	100103	0	0	0
T24	0	1	0	0
T28	95561	4	0	0
T29	0	4	0	0
T39	0	8	0	0
T68	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	143964	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	87	0	0
T17	133418	12664	0	0
T18	38010	195	0	0
T19	330116	0	0	0
T20	22143	498	0	0
T21	818428	381	0	0
T22	100103	0	0	0
T24	0	3	0	0
T28	95561	515	0	0
T29	0	427	0	0
T39	0	1185	0	0
T68	0	101	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1155	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	1	0	0
T15	0	1	0	0
T17	133418	75	0	0
T18	38010	1	0	0
T19	330116	0	0	0
T20	22143	2	0	0
T21	818428	1	0	0
T22	100103	0	0	0
T28	95561	4	0	0
T29	0	4	0	0
T39	0	8	0	0
T43	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	69	0	0
T5	248152	0	0	0
T6	423892	0	0	0
T7	406936	1	0	0
T14	800847	0	0	0
T20	22143	1	0	0
T21	818428	1	0	0
T22	100103	0	0	0
T25	0	3	0	0
T27	0	3	0	0
T28	95561	0	0	0
T33	0	2	0	0
T44	357176	0	0	0
T47	0	4	0	0
T62	0	1	0	0
T68	41992	1	0	0
T70	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1470	0	0
T8	983783	0	0	0
T11	41220	376	0	0
T12	0	174	0	0
T13	0	362	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	186	0	0
T38	0	372	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1230	0	0
T8	983783	0	0	0
T11	41220	316	0	0
T12	0	144	0	0
T13	0	302	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	156	0	0
T38	0	312	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672558843	672485818	0	0
T1	811880	811830	0	0
T2	294836	294752	0	0
T3	260701	260624	0	0
T4	532555	532466	0	0
T17	133418	133417	0	0
T18	38010	37911	0	0
T19	330116	329761	0	0
T20	22143	22065	0	0
T21	818428	818140	0	0
T22	100103	100013	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	672629808	0	0
T1	811880	811830	0	0
T2	294836	294752	0	0
T3	260701	260624	0	0
T4	532555	532466	0	0
T17	133418	133417	0	0
T18	38010	37911	0	0
T19	330116	329761	0	0
T20	22143	22065	0	0
T21	818428	818140	0	0
T22	100103	100013	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T3,T17,T7
1	1	0	Covered	T17,T18,T19
1	1	1	Covered	T17,T18,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T25,T33,T31
1	0	Covered	T39,T63,T46

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T18,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T39,T63,T46

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Not Covered
1	1	Covered	T25,T33,T31

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T39,T45,T79

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T39,T40
1	Covered	T2,T3,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T6,T40,T41

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T39,T8,T24

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T39,T8,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T39

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T6,T39

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T17
Phase1St	198	Covered	T2,T3,T17
Phase2St	215	Covered	T2,T3,T17
Phase3St	233	Covered	T2,T3,T17
TerminalSt	249	Covered	T2,T3,T17
TimeoutSt	159	Covered	T17,T18,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T3,T17
IdleSt->TimeoutSt	159	Covered	T17,T18,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T34,T80,T81
Phase0St->Phase1St	198	Covered	T2,T3,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T82,T83,T31
Phase1St->Phase2St	215	Covered	T2,T3,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T84,T85,T86
Phase2St->Phase3St	233	Covered	T2,T3,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T82,T87,T88
Phase3St->TerminalSt	249	Covered	T2,T3,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T17,T39,T8
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T17,T18,T19
TimeoutSt->Phase0St	172	Covered	T39,T63,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T39,T63,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T81,T89
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T82,T83,T90
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T84,T85,T86
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T82,T87,T88
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T39,T8,T64
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	672804857	311	0	0
CheckAccumTrig0_A	672804857	452	0	0
CheckAccumTrig1_A	672804857	24	0	0
CheckClr_A	672804857	214	0	0
CheckEn_A	672560726	347641735	0	0
CheckPhase0_A	672804857	533	0	0
CheckPhase1_A	672804857	526	0	0
CheckPhase2_A	672804857	518	0	0
CheckPhase3_A	672804857	509	0	0
CheckTimeout0_A	672804857	842	0	0
CheckTimeoutSt1_A	672804857	100355	0	0
CheckTimeoutSt2_A	672804857	753	0	0
CheckTimeoutStTrig_A	672804857	64	0	0
ErrorStAllEscAsserted_A	672804857	1487	0	0
ErrorStIsTerminal_A	672804857	1247	0	0
EscStateOut_A	672558843	672485818	0	0
u_state_regs_A	672804857	672629808	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	311	0	0
T8	983783	0	0	0
T11	41220	57	0	0
T12	0	51	0	0
T13	0	84	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	36	0	0
T38	0	83	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	452	0	0
T2	294836	1	0	0
T3	260701	1	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	1	0	0
T8	0	1	0	0
T17	133418	1	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T24	0	1	0	0
T29	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	24	0	0
T8	983783	0	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T39	413675	1	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0
T46	0	1	0	0
T54	0	2	0	0
T59	111911	0	0	0
T63	0	1	0	0
T82	0	1	0	0
T87	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	214	0	0
T8	983783	1	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T25	0	1	0	0
T27	0	4	0	0
T29	421561	0	0	0
T39	413675	1	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0
T46	0	3	0	0
T59	111911	0	0	0
T64	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T70	0	2	0	0
T94	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672560726	347641735	0	0
T1	811880	811829	0	0
T2	294836	2013	0	0
T3	260701	2066	0	0
T4	532555	468531	0	0
T17	133418	748032	0	0
T18	38010	21827	0	0
T19	330116	52041	0	0
T20	22143	22064	0	0
T21	818428	808163	0	0
T22	100103	93675	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	533	0	0
T2	294836	1	0	0
T3	260701	1	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	1	0	0
T8	0	1	0	0
T17	133418	1	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T24	0	1	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	526	0	0
T2	294836	1	0	0
T3	260701	1	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	1	0	0
T8	0	1	0	0
T17	133418	1	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T24	0	1	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	518	0	0
T2	294836	1	0	0
T3	260701	1	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	1	0	0
T8	0	1	0	0
T17	133418	1	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T24	0	1	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	509	0	0
T2	294836	1	0	0
T3	260701	1	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	1	0	0
T8	0	1	0	0
T17	133418	1	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T24	0	1	0	0
T29	0	1	0	0
T39	0	3	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	842	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	1	0	0
T15	0	2	0	0
T17	133418	66	0	0
T18	38010	1	0	0
T19	330116	9	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T25	0	36	0	0
T28	95561	0	0	0
T39	0	12	0	0
T40	0	3	0	0
T63	0	1	0	0
T70	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	100355	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	28	0	0
T15	0	81	0	0
T17	133418	10935	0	0
T18	38010	195	0	0
T19	330116	2279	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T25	0	2405	0	0
T28	95561	0	0	0
T39	0	1715	0	0
T40	0	446	0	0
T46	0	1123	0	0
T70	0	1727	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	753	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	1	0	0
T15	0	2	0	0
T17	133418	65	0	0
T18	38010	1	0	0
T19	330116	9	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T25	0	35	0	0
T28	95561	0	0	0
T39	0	11	0	0
T40	0	3	0	0
T46	0	10	0	0
T70	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	64	0	0
T25	137449	1	0	0
T31	0	1	0	0
T32	17524	0	0	0
T33	0	1	0	0
T49	0	2	0	0
T52	0	1	0	0
T65	190683	0	0	0
T66	358745	0	0	0
T69	83268	0	0	0
T74	0	1	0	0
T79	147730	0	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	2	0	0
T98	0	4	0	0
T99	20505	0	0	0
T100	3000	0	0	0
T101	66368	0	0	0
T102	149931	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1487	0	0
T8	983783	0	0	0
T11	41220	374	0	0
T12	0	188	0	0
T13	0	357	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	200	0	0
T38	0	368	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1247	0	0
T8	983783	0	0	0
T11	41220	314	0	0
T12	0	158	0	0
T13	0	297	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	170	0	0
T38	0	308	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672558843	672485818	0	0
T1	811880	811830	0	0
T2	294836	294752	0	0
T3	260701	260624	0	0
T4	532555	532466	0	0
T17	133418	133417	0	0
T18	38010	37911	0	0
T19	330116	329761	0	0
T20	22143	22065	0	0
T21	818428	818140	0	0
T22	100103	100013	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	672629808	0	0
T1	811880	811830	0	0
T2	294836	294752	0	0
T3	260701	260624	0	0
T4	532555	532466	0	0
T17	133418	133417	0	0
T18	38010	37911	0	0
T19	330116	329761	0	0
T20	22143	22065	0	0
T21	818428	818140	0	0
T22	100103	100013	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T18
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T17,T18

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T17,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T17,T7,T6
1	1	0	Covered	T17,T21,T7
1	1	1	Covered	T17,T18,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T17,T18,T19
1	0	Covered	T29,T25,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T18,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T29,T25,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T26
1	1	Covered	T17,T18,T19

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T18
1	Covered	T17,T68,T29

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T18
1	Covered	T17,T24,T45

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T17,T19
1	Covered	T17,T18,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T3,T17,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T17,T18,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T17,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T17,T18
Phase1St	198	Covered	T3,T17,T18
Phase2St	215	Covered	T3,T17,T18
Phase3St	233	Covered	T3,T17,T18
TerminalSt	249	Covered	T3,T17,T18
TimeoutSt	159	Covered	T17,T18,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T3,T17,T19
IdleSt->TimeoutSt	159	Covered	T17,T18,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T7,T27,T36
Phase0St->Phase1St	198	Covered	T3,T17,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T103,T26
Phase1St->Phase2St	215	Covered	T3,T17,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T51,T87,T103
Phase2St->Phase3St	233	Covered	T3,T17,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T24,T104,T105
Phase3St->TerminalSt	249	Covered	T3,T17,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T17,T18,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T17,T18,T19
TimeoutSt->Phase0St	172	Covered	T17,T18,T19

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T36,T106,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T17,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T17,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T103,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T17,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T17,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T51,T103,T53
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T17,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T17,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T104,T105
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T17,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T17,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T18,T20,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T17,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	672804857	340	0	0
CheckAccumTrig0_A	672804857	510	0	0
CheckAccumTrig1_A	672804857	19	0	0
CheckClr_A	672804857	204	0	0
CheckEn_A	672560726	287351081	0	0
CheckPhase0_A	672804857	583	0	0
CheckPhase1_A	672804857	574	0	0
CheckPhase2_A	672804857	565	0	0
CheckPhase3_A	672804857	551	0	0
CheckTimeout0_A	672804857	1179	0	0
CheckTimeoutSt1_A	672804857	132783	0	0
CheckTimeoutSt2_A	672804857	1097	0	0
CheckTimeoutStTrig_A	672804857	61	0	0
ErrorStAllEscAsserted_A	672804857	1460	0	0
ErrorStIsTerminal_A	672804857	1220	0	0
EscStateOut_A	672558843	672485818	0	0
u_state_regs_A	672804857	672629808	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	340	0	0
T8	983783	0	0	0
T11	41220	83	0	0
T12	0	43	0	0
T13	0	88	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	44	0	0
T38	0	82	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	510	0	0
T3	260701	1	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	1	0	0
T7	406936	4	0	0
T14	0	1	0	0
T17	133418	2	0	0
T18	38010	0	0	0
T19	330116	1	0	0
T20	22143	1	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T24	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	19	0	0
T15	670980	0	0	0
T16	108234	0	0	0
T25	0	1	0	0
T29	421561	1	0	0
T42	44383	0	0	0
T43	18524	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	111911	0	0	0
T60	14384	0	0	0
T61	12351	0	0	0
T62	10460	0	0	0
T63	24034	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	204	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	423892	0	0	0
T7	406936	0	0	0
T15	0	1	0	0
T18	38010	1	0	0
T19	330116	0	0	0
T20	22143	1	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T24	0	1	0	0
T28	95561	0	0	0
T29	0	9	0	0
T40	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672560726	287351081	0	0
T1	811880	810540	0	0
T2	294836	270185	0	0
T3	260701	12494	0	0
T4	532555	467332	0	0
T17	133418	855508	0	0
T18	38010	3123	0	0
T19	330116	51972	0	0
T20	22143	3047	0	0
T21	818428	736775	0	0
T22	100103	8519	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	583	0	0
T3	260701	1	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	1	0	0
T7	406936	3	0	0
T14	0	1	0	0
T17	133418	4	0	0
T18	38010	2	0	0
T19	330116	2	0	0
T20	22143	2	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T39	0	2	0	0
T68	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	574	0	0
T3	260701	1	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	1	0	0
T7	406936	3	0	0
T14	0	1	0	0
T17	133418	4	0	0
T18	38010	2	0	0
T19	330116	2	0	0
T20	22143	2	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T39	0	2	0	0
T68	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	565	0	0
T3	260701	1	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	1	0	0
T7	406936	3	0	0
T14	0	1	0	0
T17	133418	4	0	0
T18	38010	2	0	0
T19	330116	2	0	0
T20	22143	2	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T39	0	2	0	0
T68	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	551	0	0
T3	260701	1	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T6	0	1	0	0
T7	406936	3	0	0
T14	0	1	0	0
T17	133418	4	0	0
T18	38010	2	0	0
T19	330116	2	0	0
T20	22143	2	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T39	0	2	0	0
T68	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1179	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	2	0	0
T17	133418	4	0	0
T18	38010	3	0	0
T19	330116	12	0	0
T20	22143	2	0	0
T21	818428	6	0	0
T22	100103	0	0	0
T24	0	1	0	0
T28	95561	0	0	0
T29	0	4	0	0
T42	0	1	0	0
T68	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	132783	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	163	0	0
T17	133418	751	0	0
T18	38010	533	0	0
T19	330116	2591	0	0
T20	22143	732	0	0
T21	818428	1150	0	0
T22	100103	0	0	0
T24	0	150	0	0
T28	95561	0	0	0
T29	0	531	0	0
T42	0	180	0	0
T68	0	165	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1097	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	2	0	0
T17	133418	2	0	0
T18	38010	1	0	0
T19	330116	11	0	0
T20	22143	1	0	0
T21	818428	6	0	0
T22	100103	0	0	0
T24	0	1	0	0
T28	95561	0	0	0
T29	0	3	0	0
T42	0	1	0	0
T43	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	61	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	0	0	0
T17	133418	2	0	0
T18	38010	2	0	0
T19	330116	1	0	0
T20	22143	1	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T28	95561	0	0	0
T46	0	2	0	0
T60	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T71	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1460	0	0
T8	983783	0	0	0
T11	41220	367	0	0
T12	0	200	0	0
T13	0	369	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	183	0	0
T38	0	341	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1220	0	0
T8	983783	0	0	0
T11	41220	307	0	0
T12	0	170	0	0
T13	0	309	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	153	0	0
T38	0	281	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672558843	672485818	0	0
T1	811880	811830	0	0
T2	294836	294752	0	0
T3	260701	260624	0	0
T4	532555	532466	0	0
T17	133418	133417	0	0
T18	38010	37911	0	0
T19	330116	329761	0	0
T20	22143	22065	0	0
T21	818428	818140	0	0
T22	100103	100013	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	672629808	0	0
T1	811880	811830	0	0
T2	294836	294752	0	0
T3	260701	260624	0	0
T4	532555	532466	0	0
T17	133418	133417	0	0
T18	38010	37911	0	0
T19	330116	329761	0	0
T20	22143	22065	0	0
T21	818428	818140	0	0
T22	100103	100013	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T17,T21
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T17,T21

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T17
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T23
1	1	1	Covered	T1,T17,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T21,T7
1	0	1	Covered	T1,T3,T17
1	1	0	Covered	T17,T18,T19
1	1	1	Covered	T17,T21,T68

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T17,T21,T68
0	1	Covered	T70,T33,T72
1	0	Covered	T17,T27,T48

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T17,T21,T68
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T27,T48

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T21,T68
1	0	Covered	T25
1	1	Covered	T70,T33,T72

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T5
1	Covered	T17,T5,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T5
1	Covered	T29,T45,T25

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T17,T5,T7
1	Covered	T1,T17,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T5
1	Covered	T7,T6,T14

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T17,T5,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T7,T28,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T5,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T17,T5,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T17,T5
Phase1St	198	Covered	T1,T17,T5
Phase2St	215	Covered	T1,T17,T5
Phase3St	233	Covered	T1,T17,T5
TerminalSt	249	Covered	T1,T17,T5
TimeoutSt	159	Covered	T17,T21,T68

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T17,T5
IdleSt->TimeoutSt	159	Covered	T17,T21,T68
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T50,T103
Phase0St->Phase1St	198	Covered	T1,T17,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T33,T48,T103
Phase1St->Phase2St	215	Covered	T1,T17,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T108,T109
Phase2St->Phase3St	233	Covered	T1,T17,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T87,T110,T111
Phase3St->TerminalSt	249	Covered	T1,T17,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T17,T5,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T17,T21,T68
TimeoutSt->Phase0St	172	Covered	T17,T70,T27

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T17,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T21,T68
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T17,T70,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T17,T21,T68
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T17,T21,T68
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T50,T103,T111
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T17,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T17,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T33,T48,T103
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T17,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T17,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T108,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T17,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T17,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T110,T111,T112
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T17,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T17,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T17,T5,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T17,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	672804857	286	0	0
CheckAccumTrig0_A	672804857	497	0	0
CheckAccumTrig1_A	672804857	21	0	0
CheckClr_A	672804857	227	0	0
CheckEn_A	672560726	306550386	0	0
CheckPhase0_A	672804857	576	0	0
CheckPhase1_A	672804857	560	0	0
CheckPhase2_A	672804857	553	0	0
CheckPhase3_A	672804857	548	0	0
CheckTimeout0_A	672804857	693	0	0
CheckTimeoutSt1_A	672804857	85265	0	0
CheckTimeoutSt2_A	672804857	603	0	0
CheckTimeoutStTrig_A	672804857	68	0	0
ErrorStAllEscAsserted_A	672804857	1520	0	0
ErrorStIsTerminal_A	672804857	1280	0	0
EscStateOut_A	672558843	672485818	0	0
u_state_regs_A	672804857	672629808	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	286	0	0
T8	983783	0	0	0
T11	41220	59	0	0
T12	0	43	0	0
T13	0	87	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	41	0	0
T38	0	56	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	497	0	0
T1	811880	1	0	0
T2	294836	0	0	0
T3	260701	0	0	0
T4	532555	0	0	0
T5	0	2	0	0
T6	0	1	0	0
T7	0	2	0	0
T14	0	1	0	0
T17	133418	5	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T28	0	1	0	0
T39	0	2	0	0
T40	0	4	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	21	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	0	0	0
T17	133418	1	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T27	0	2	0	0
T28	95561	0	0	0
T48	0	1	0	0
T111	0	3	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	227	0	0
T4	532555	0	0	0
T5	248152	1	0	0
T7	406936	0	0	0
T9	0	14	0	0
T17	133418	5	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T25	0	1	0	0
T28	95561	0	0	0
T29	0	5	0	0
T40	0	3	0	0
T61	0	1	0	0
T64	0	9	0	0
T66	0	1	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672560726	306550386	0	0
T1	811880	838	0	0
T2	294836	294751	0	0
T3	260701	253609	0	0
T4	532555	590	0	0
T17	133418	129693	0	0
T18	38010	37910	0	0
T19	330116	329757	0	0
T20	22143	22064	0	0
T21	818428	723874	0	0
T22	100103	100012	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	576	0	0
T1	811880	1	0	0
T2	294836	0	0	0
T3	260701	0	0	0
T4	532555	0	0	0
T5	0	2	0	0
T6	0	1	0	0
T7	0	2	0	0
T14	0	1	0	0
T17	133418	6	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T28	0	1	0	0
T39	0	2	0	0
T40	0	4	0	0
T44	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	560	0	0
T1	811880	1	0	0
T2	294836	0	0	0
T3	260701	0	0	0
T4	532555	0	0	0
T5	0	2	0	0
T6	0	1	0	0
T7	0	2	0	0
T14	0	1	0	0
T17	133418	6	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T28	0	1	0	0
T39	0	2	0	0
T40	0	4	0	0
T44	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	553	0	0
T1	811880	1	0	0
T2	294836	0	0	0
T3	260701	0	0	0
T4	532555	0	0	0
T5	0	2	0	0
T6	0	1	0	0
T7	0	2	0	0
T14	0	1	0	0
T17	133418	6	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T28	0	1	0	0
T39	0	2	0	0
T40	0	4	0	0
T44	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	548	0	0
T1	811880	1	0	0
T2	294836	0	0	0
T3	260701	0	0	0
T4	532555	0	0	0
T5	0	2	0	0
T6	0	1	0	0
T7	0	2	0	0
T14	0	1	0	0
T17	133418	6	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	0	0	0
T22	100103	0	0	0
T28	0	1	0	0
T39	0	2	0	0
T40	0	4	0	0
T44	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	693	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	0	0	0
T17	133418	3	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	12	0	0
T22	100103	0	0	0
T25	0	20	0	0
T28	95561	0	0	0
T29	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T60	0	1	0	0
T68	0	4	0	0
T69	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	85265	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	0	0	0
T17	133418	367	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	2183	0	0
T22	100103	0	0	0
T25	0	806	0	0
T28	95561	0	0	0
T29	0	174	0	0
T39	0	106	0	0
T40	0	240	0	0
T43	0	179	0	0
T60	0	146	0	0
T68	0	695	0	0
T69	0	160	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	603	0	0
T4	532555	0	0	0
T5	248152	0	0	0
T7	406936	0	0	0
T17	133418	2	0	0
T18	38010	0	0	0
T19	330116	0	0	0
T20	22143	0	0	0
T21	818428	12	0	0
T22	100103	0	0	0
T25	0	20	0	0
T28	95561	0	0	0
T29	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T43	0	1	0	0
T60	0	1	0	0
T68	0	4	0	0
T69	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	68	0	0
T27	409778	0	0	0
T33	0	2	0	0
T34	515921	0	0	0
T46	113530	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T70	780260	1	0	0
T71	71891	0	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	92037	0	0	0
T76	192424	0	0	0
T77	104252	0	0	0
T96	0	1	0	0
T119	30715	0	0	0
T120	29538	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1520	0	0
T8	983783	0	0	0
T11	41220	399	0	0
T12	0	204	0	0
T13	0	361	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	195	0	0
T38	0	361	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	1280	0	0
T8	983783	0	0	0
T11	41220	339	0	0
T12	0	174	0	0
T13	0	301	0	0
T15	670980	0	0	0
T24	20280	0	0	0
T29	421561	0	0	0
T37	0	165	0	0
T38	0	301	0	0
T39	413675	0	0	0
T40	93776	0	0	0
T41	151960	0	0	0
T42	44383	0	0	0
T43	18524	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672558843	672485818	0	0
T1	811880	811830	0	0
T2	294836	294752	0	0
T3	260701	260624	0	0
T4	532555	532466	0	0
T17	133418	133417	0	0
T18	38010	37911	0	0
T19	330116	329761	0	0
T20	22143	22065	0	0
T21	818428	818140	0	0
T22	100103	100013	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	672804857	672629808	0	0
T1	811880	811830	0	0
T2	294836	294752	0	0
T3	260701	260624	0	0
T4	532555	532466	0	0
T17	133418	133417	0	0
T18	38010	37911	0	0
T19	330116	329761	0	0
T20	22143	22065	0	0
T21	818428	818140	0	0
T22	100103	100013	0	0