Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	85.19	100.00	88.89				66.67
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	88.89				66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.89	100.00	88.89	100.00			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T187,T188
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14052	0	0
DisabledNoTrigBkwd_A	2147483647	765641	0	0
DisabledNoTrigFwd_A	2147483647	1544413452	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14052	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T16	411074	0	0	0
T17	119776	0	0	0
T32	1353	598	0	0
T33	1807	0	0	0
T34	21259	0	0	0
T35	12762	0	0	0
T100	55155	0	0	0
T172	0	1159	0	0
T177	0	583	0	0
T187	0	235	0	0
T188	0	662	0	0
T189	3026	827	0	0
T190	1293	507	0	0
T191	0	1297	0	0
T192	0	396	0	0
T193	0	1128	0	0
T194	0	198	0	0
T195	0	912	0	0
T196	0	636	0	0
T197	0	817	0	0
T198	0	572	0	0
T199	0	367	0	0
T200	0	644	0	0
T201	0	1605	0	0
T202	0	728	0	0
T203	0	181	0	0
T204	46424	0	0	0
T205	191221	0	0	0
T206	46530	0	0	0
T207	41123	0	0	0
T208	29542	0	0	0
T209	272512	0	0	0
T210	173142	0	0	0
T211	60156	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	765641	0	0
T1	563767	246	0	0
T2	15996	0	0	0
T3	53913	13	0	0
T4	3203964	2	0	0
T5	3053036	1747	0	0
T6	334740	0	0	0
T7	44046	6	0	0
T8	3246984	2	0	0
T9	0	982	0	0
T10	0	1504	0	0
T11	0	461	0	0
T12	0	14	0	0
T13	52869	0	0	0
T16	0	1691	0	0
T17	0	1579	0	0
T18	332664	65	0	0
T19	401544	217	0	0
T20	38187	47	0	0
T21	5243	0	0	0
T22	429086	405	0	0
T32	0	5	0	0
T34	0	2	0	0
T35	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1544413452	0	0
T1	2255068	1698574	0	0
T2	63984	21754	0	0
T3	71884	40974	0	0
T4	3203964	832589	0	0
T5	3053036	1267204	0	0
T6	334740	232059	0	0
T7	58728	30273	0	0
T8	3246984	2206471	0	0
T18	332664	118200	0	0
T19	401544	203841	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T18,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	2	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	2	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	687847418	0	0	0
DisabledNoTrigBkwd_A	687847418	226056	0	0
DisabledNoTrigFwd_A	687847418	342949497	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	226056	0	0
T4	800991	1	0	0
T5	763259	490	0	0
T6	83685	0	0	0
T8	811746	1	0	0
T10	0	1504	0	0
T11	0	458	0	0
T13	17623	0	0	0
T16	0	570	0	0
T18	83166	10	0	0
T19	100386	65	0	0
T20	12729	1	0	0
T21	5243	0	0	0
T22	429086	115	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	342949497	0	0
T1	563767	558516	0	0
T2	15996	3024	0	0
T3	17971	15476	0	0
T4	800991	621	0	0
T5	763259	633929	0	0
T6	83685	70051	0	0
T7	14682	14628	0	0
T8	811746	789290	0	0
T18	83166	8948	0	0
T19	100386	2631	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T18
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T187,T188
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	687847418	3202	0	0
DisabledNoTrigBkwd_A	687847418	159822	0	0
DisabledNoTrigFwd_A	687847418	407357869	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	3202	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T16	411074	0	0	0
T17	119776	0	0	0
T32	1353	598	0	0
T33	1807	0	0	0
T34	21259	0	0	0
T35	12762	0	0	0
T177	0	583	0	0
T187	0	235	0	0
T188	0	662	0	0
T192	0	396	0	0
T202	0	728	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	159822	0	0
T1	563767	246	0	0
T2	15996	0	0	0
T3	17971	3	0	0
T4	800991	0	0	0
T5	763259	237	0	0
T6	83685	0	0	0
T7	14682	4	0	0
T8	811746	1	0	0
T9	0	981	0	0
T18	83166	23	0	0
T19	100386	0	0	0
T20	0	20	0	0
T22	0	189	0	0
T32	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	407357869	0	0
T1	563767	17858	0	0
T2	15996	3729	0	0
T3	17971	3782	0	0
T4	800991	625	0	0
T5	763259	239260	0	0
T6	83685	78470	0	0
T7	14682	2065	0	0
T8	811746	741664	0	0
T18	83166	22913	0	0
T19	100386	100308	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T189,T172,T191
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	687847418	5963	0	0
DisabledNoTrigBkwd_A	687847418	194371	0	0
DisabledNoTrigFwd_A	687847418	406964003	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	5963	0	0
T100	55155	0	0	0
T172	0	1159	0	0
T189	3026	827	0	0
T191	0	1297	0	0
T194	0	198	0	0
T195	0	912	0	0
T197	0	817	0	0
T198	0	572	0	0
T203	0	181	0	0
T204	46424	0	0	0
T205	191221	0	0	0
T206	46530	0	0	0
T207	41123	0	0	0
T208	29542	0	0	0
T209	272512	0	0	0
T210	173142	0	0	0
T211	60156	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	194371	0	0
T3	17971	6	0	0
T4	800991	0	0	0
T5	763259	362	0	0
T6	83685	0	0	0
T7	14682	2	0	0
T8	811746	0	0	0
T9	0	1	0	0
T11	0	3	0	0
T12	0	14	0	0
T13	17623	0	0	0
T16	0	161	0	0
T18	83166	32	0	0
T19	100386	0	0	0
T20	12729	12	0	0
T22	0	38	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	406964003	0	0
T1	563767	558505	0	0
T2	15996	1950	0	0
T3	17971	9187	0	0
T4	800991	800928	0	0
T5	763259	250780	0	0
T6	83685	75186	0	0
T7	14682	2076	0	0
T8	811746	498155	0	0
T18	83166	3254	0	0
T19	100386	100308	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T190,T193,T196
1	1	Covered	T2,T3,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	687847418	4887	0	0
DisabledNoTrigBkwd_A	687847418	185392	0	0
DisabledNoTrigFwd_A	687847418	387142083	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	4887	0	0
T41	275336	0	0	0
T42	192041	0	0	0
T43	105529	0	0	0
T86	30741	0	0	0
T190	1293	507	0	0
T193	0	1128	0	0
T196	0	636	0	0
T199	0	367	0	0
T200	0	644	0	0
T201	0	1605	0	0
T212	117032	0	0	0
T213	84486	0	0	0
T214	132615	0	0	0
T215	889116	0	0	0
T216	113122	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	185392	0	0
T3	17971	4	0	0
T4	800991	1	0	0
T5	763259	658	0	0
T6	83685	0	0	0
T7	14682	0	0	0
T8	811746	0	0	0
T13	17623	0	0	0
T16	0	960	0	0
T17	0	1579	0	0
T18	83166	0	0	0
T19	100386	152	0	0
T20	12729	14	0	0
T22	0	63	0	0
T34	0	2	0	0
T35	0	2	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	387142083	0	0
T1	563767	563695	0	0
T2	15996	13051	0	0
T3	17971	12529	0	0
T4	800991	30415	0	0
T5	763259	143235	0	0
T6	83685	8352	0	0
T7	14682	11504	0	0
T8	811746	177362	0	0
T18	83166	83085	0	0
T19	100386	594	0	0