Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T1,T7,T4
1	1	0	Covered	T2,T3,T7
1	1	1	Covered	T2,T3,T7

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T5,T6,T22
1	0	Covered	T18,T5,T24

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T18,T5,T24

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T16,T25,T26
1	1	Covered	T5,T6,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T7,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T3,T4,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T4
1	Covered	T1,T18,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T18,T5,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T7,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T7,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T3,T7

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T7
Phase1St	198	Covered	T1,T3,T7
Phase2St	215	Covered	T1,T3,T7
Phase3St	233	Covered	T1,T3,T7
TerminalSt	249	Covered	T1,T3,T7
TimeoutSt	159	Covered	T2,T3,T7

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T1,T3,T7
IdleSt->TimeoutSt	159	Covered	T2,T3,T7
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T6,T8,T10
Phase0St->Phase1St	198	Covered	T1,T3,T7
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T20,T12,T10
Phase1St->Phase2St	215	Covered	T1,T3,T7
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T5,T27,T28
Phase2St->Phase3St	233	Covered	T1,T3,T7
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T22,T24,T28
Phase3St->TerminalSt	249	Covered	T1,T3,T7
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T7,T5,T6
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T2,T3,T18
TimeoutSt->Phase0St	172	Covered	T7,T18,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T18,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T8,T10
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T12,T10
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T28,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T24,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T5,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	817	0	0
CheckAccumTrig0_A	2147483647	2393	0	0
CheckAccumTrig1_A	2147483647	126	0	0
CheckClr_A	2147483647	1093	0	0
CheckEn_A	2147483647	1210159601	0	0
CheckPhase0_A	2147483647	2726	0	0
CheckPhase1_A	2147483647	2681	0	0
CheckPhase2_A	2147483647	2623	0	0
CheckPhase3_A	2147483647	2582	0	0
CheckTimeout0_A	2147483647	3970	0	0
CheckTimeoutSt1_A	2147483647	497927	0	0
CheckTimeoutSt2_A	2147483647	3583	0	0
CheckTimeoutStTrig_A	2147483647	254	0	0
ErrorStAllEscAsserted_A	2147483647	4351	0	0
ErrorStIsTerminal_A	2147483647	3631	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	817	0	0
T9	555300	0	0	0
T10	902984	0	0	0
T11	1131980	0	0	0
T12	2952328	0	0	0
T13	70492	152	0	0
T14	0	148	0	0
T15	0	232	0	0
T16	1644296	0	0	0
T21	20972	0	0	0
T22	1716344	0	0	0
T30	0	153	0	0
T31	0	132	0	0
T32	5412	0	0	0
T33	7228	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2393	0	0
T1	563767	1	0	0
T2	15996	0	0	0
T3	53913	3	0	0
T4	3203964	2	0	0
T5	3053036	17	0	0
T6	334740	0	0	0
T7	44046	2	0	0
T8	3246984	2	0	0
T9	0	2	0	0
T10	0	5	0	0
T11	0	3	0	0
T12	0	1	0	0
T13	52869	0	0	0
T16	0	17	0	0
T17	0	2	0	0
T18	332664	2	0	0
T19	401544	2	0	0
T20	38187	4	0	0
T21	5243	0	0	0
T22	429086	17	0	0
T32	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	126	0	0
T5	1526518	1	0	0
T6	167370	0	0	0
T8	1623492	0	0	0
T9	138825	0	0	0
T13	35246	0	0	0
T18	83166	1	0	0
T19	200772	0	0	0
T20	25458	0	0	0
T21	10486	0	0	0
T22	858172	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T32	2706	0	0	0
T36	0	1	0	0
T37	346663	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	8	0	0
T46	0	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	26319	0	0	0
T54	161515	0	0	0
T55	140430	0	0	0
T56	43854	0	0	0
T57	914723	0	0	0
T58	161965	0	0	0
T59	16412	0	0	0
T60	22995	0	0	0
T61	26172	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1093	0	0
T4	800991	0	0	0
T5	2289777	7	0	0
T6	334740	1	0	0
T7	14682	1	0	0
T8	3246984	2	0	0
T9	416475	1	0	0
T10	225746	4	0	0
T11	0	1	0	0
T12	738082	1	0	0
T13	70492	0	0	0
T16	0	1	0	0
T18	83166	0	0	0
T19	301158	0	0	0
T20	50916	1	0	0
T21	20972	0	0	0
T22	1287258	6	0	0
T24	0	2	0	0
T27	0	1	0	0
T32	4059	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	3	0	0
T38	0	6	0	0
T60	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1210159601	0	0
T1	2255068	1698571	0	0
T2	63984	21753	0	0
T3	71884	32281	0	0
T4	3203964	832588	0	0
T5	3053036	1171277	0	0
T6	334740	232056	0	0
T7	58728	30272	0	0
T8	3246984	2206469	0	0
T18	332664	118199	0	0
T19	401544	203839	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2726	0	0
T1	563767	1	0	0
T2	15996	0	0	0
T3	53913	3	0	0
T4	3203964	2	0	0
T5	3053036	25	0	0
T6	334740	1	0	0
T7	44046	3	0	0
T8	3246984	1	0	0
T9	0	2	0	0
T10	0	4	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	52869	0	0	0
T16	0	20	0	0
T17	0	2	0	0
T18	332664	3	0	0
T19	401544	2	0	0
T20	38187	4	0	0
T21	5243	0	0	0
T22	429086	18	0	0
T32	0	1	0	0
T34	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2681	0	0
T1	563767	1	0	0
T2	15996	0	0	0
T3	53913	3	0	0
T4	3203964	2	0	0
T5	3053036	25	0	0
T6	334740	1	0	0
T7	44046	3	0	0
T8	3246984	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	52869	0	0	0
T16	0	20	0	0
T17	0	2	0	0
T18	332664	3	0	0
T19	401544	2	0	0
T20	38187	3	0	0
T21	5243	0	0	0
T22	429086	18	0	0
T32	0	1	0	0
T34	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2623	0	0
T1	563767	1	0	0
T2	15996	0	0	0
T3	53913	3	0	0
T4	3203964	2	0	0
T5	3053036	24	0	0
T6	334740	1	0	0
T7	44046	3	0	0
T8	3246984	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	52869	0	0	0
T16	0	20	0	0
T17	0	2	0	0
T18	332664	3	0	0
T19	401544	2	0	0
T20	38187	3	0	0
T21	5243	0	0	0
T22	429086	18	0	0
T32	0	1	0	0
T34	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2582	0	0
T1	563767	1	0	0
T2	15996	0	0	0
T3	53913	3	0	0
T4	3203964	2	0	0
T5	3053036	24	0	0
T6	334740	1	0	0
T7	44046	3	0	0
T8	3246984	1	0	0
T9	0	2	0	0
T10	0	3	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	52869	0	0	0
T16	0	20	0	0
T17	0	2	0	0
T18	332664	3	0	0
T19	401544	2	0	0
T20	38187	3	0	0
T21	5243	0	0	0
T22	429086	17	0	0
T32	0	1	0	0
T34	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3970	0	0
T2	47988	10	0	0
T3	53913	2	0	0
T4	3203964	0	0	0
T5	3053036	501	0	0
T6	334740	11	0	0
T7	58728	1	0	0
T8	3246984	0	0	0
T13	17623	0	0	0
T16	0	116	0	0
T17	0	1	0	0
T18	332664	2	0	0
T19	401544	0	0	0
T20	50916	2	0	0
T21	5243	1	0	0
T22	0	5	0	0
T24	0	7	0	0
T27	0	111	0	0
T36	0	6	0	0
T37	0	5	0	0
T63	0	5	0	0
T64	0	4	0	0
T65	0	1	0	0
T66	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	497927	0	0
T2	47988	1029	0	0
T3	53913	401	0	0
T4	3203964	0	0	0
T5	3053036	89679	0	0
T6	334740	2682	0	0
T7	58728	150	0	0
T8	3246984	0	0	0
T13	17623	0	0	0
T16	0	17170	0	0
T17	0	26	0	0
T18	332664	93	0	0
T19	401544	0	0	0
T20	50916	98	0	0
T21	5243	41	0	0
T22	0	1266	0	0
T24	0	1335	0	0
T27	0	20174	0	0
T36	0	1071	0	0
T37	0	438	0	0
T63	0	93	0	0
T64	0	202	0	0
T65	0	77	0	0
T66	0	314	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3583	0	0
T2	47988	10	0	0
T3	53913	2	0	0
T4	2402973	0	0	0
T5	3053036	493	0	0
T6	334740	9	0	0
T7	44046	0	0	0
T8	3246984	0	0	0
T9	138825	0	0	0
T13	17623	0	0	0
T16	0	111	0	0
T17	0	1	0	0
T18	249498	1	0	0
T19	401544	0	0	0
T20	50916	2	0	0
T21	5243	1	0	0
T22	429086	4	0	0
T24	0	2	0	0
T25	0	1	0	0
T27	0	105	0	0
T32	1353	0	0	0
T36	0	4	0	0
T37	0	7	0	0
T53	0	1	0	0
T60	0	1	0	0
T63	0	4	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	254	0	0
T4	800991	0	0	0
T5	3053036	5	0	0
T6	334740	1	0	0
T7	14682	0	0	0
T8	3246984	0	0	0
T9	416475	0	0	0
T13	70492	0	0	0
T16	0	5	0	0
T18	83166	0	0	0
T19	401544	0	0	0
T20	50916	0	0	0
T21	20972	0	0	0
T22	1287258	1	0	0
T24	0	3	0	0
T25	0	1	0	0
T27	0	8	0	0
T32	4059	0	0	0
T37	0	1	0	0
T40	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4351	0	0
T9	555300	0	0	0
T10	902984	0	0	0
T11	1131980	0	0	0
T12	2952328	0	0	0
T13	70492	772	0	0
T14	0	716	0	0
T15	0	1432	0	0
T16	1644296	0	0	0
T21	20972	0	0	0
T22	1716344	0	0	0
T30	0	713	0	0
T31	0	718	0	0
T32	5412	0	0	0
T33	7228	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3631	0	0
T9	555300	0	0	0
T10	902984	0	0	0
T11	1131980	0	0	0
T12	2952328	0	0	0
T13	70492	652	0	0
T14	0	596	0	0
T15	0	1192	0	0
T16	1644296	0	0	0
T21	20972	0	0	0
T22	1716344	0	0	0
T30	0	593	0	0
T31	0	598	0	0
T32	5412	0	0	0
T33	7228	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2255068	2254780	0	0
T2	63984	63664	0	0
T3	71884	71608	0	0
T4	3203964	3203712	0	0
T5	3053036	3052976	0	0
T6	334740	334428	0	0
T7	58728	58512	0	0
T8	3246984	3246644	0	0
T18	332664	332340	0	0
T19	401544	401232	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2255068	2254780	0	0
T2	63984	63664	0	0
T3	71884	71608	0	0
T4	3203964	3203712	0	0
T5	3053036	3052976	0	0
T6	334740	334428	0	0
T7	58728	58512	0	0
T8	3246984	3246644	0	0
T18	332664	332340	0	0
T19	401544	401232	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T18

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T7,T5,T8
1	1	0	Covered	T3,T5,T6
1	1	1	Covered	T2,T5,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T5,T6,T22
1	0	Covered	T37,T39,T79

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T5,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T37,T39,T79

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Not Covered
1	1	Covered	T5,T6,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T18,T5
1	Covered	T7,T20,T22

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T18,T5
1	Covered	T3,T5,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T18
1	Covered	T5,T16,T80

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T5
1	Covered	T18,T22,T12

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T7,T5,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T18,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T7,T18
Phase1St	198	Covered	T3,T7,T18
Phase2St	215	Covered	T3,T7,T18
Phase3St	233	Covered	T3,T7,T18
TerminalSt	249	Covered	T3,T7,T18
TimeoutSt	159	Covered	T2,T5,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T3,T7,T18
IdleSt->TimeoutSt	159	Covered	T2,T5,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T81,T82,T45
Phase0St->Phase1St	198	Covered	T3,T7,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T40,T83,T84
Phase1St->Phase2St	215	Covered	T3,T7,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T79,T85
Phase2St->Phase3St	233	Covered	T3,T7,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T22,T24,T86
Phase3St->TerminalSt	249	Covered	T3,T7,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T7,T5,T6
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T5,T22
TimeoutSt->Phase0St	172	Covered	T5,T6,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T81,T46,T87
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T7,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T7,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T40,T84,T88
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T7,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T7,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T79,T85,T45
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T7,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T7,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T22,T24,T86
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T7,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T7,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T6,T9
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T7,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	687847418	205	0	0
CheckAccumTrig0_A	687847418	459	0	0
CheckAccumTrig1_A	687847418	26	0	0
CheckClr_A	687847418	189	0	0
CheckEn_A	687690561	319458487	0	0
CheckPhase0_A	687847418	533	0	0
CheckPhase1_A	687847418	523	0	0
CheckPhase2_A	687847418	515	0	0
CheckPhase3_A	687847418	508	0	0
CheckTimeout0_A	687847418	1260	0	0
CheckTimeoutSt1_A	687847418	170087	0	0
CheckTimeoutSt2_A	687847418	1173	0	0
CheckTimeoutStTrig_A	687847418	58	0	0
ErrorStAllEscAsserted_A	687847418	1111	0	0
ErrorStIsTerminal_A	687847418	931	0	0
EscStateOut_A	687686703	687616700	0	0
u_state_regs_A	687847418	687700798	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	205	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	40	0	0
T14	0	34	0	0
T15	0	52	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	40	0	0
T31	0	39	0	0
T32	1353	0	0	0
T33	1807	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	459	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	2	0	0
T6	83685	0	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	17623	0	0	0
T16	0	2	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	12729	1	0	0
T22	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	26	0	0
T37	346663	1	0	0
T39	0	1	0	0
T46	0	3	0	0
T49	0	1	0	0
T53	26319	0	0	0
T54	161515	0	0	0
T55	140430	0	0	0
T56	43854	0	0	0
T57	914723	0	0	0
T58	161965	0	0	0
T59	16412	0	0	0
T60	22995	0	0	0
T61	26172	0	0	0
T79	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	189	0	0
T4	800991	0	0	0
T5	763259	0	0	0
T6	83685	1	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T9	0	1	0	0
T13	17623	0	0	0
T16	0	1	0	0
T18	83166	0	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	0	1	0	0
T24	0	1	0	0
T37	0	1	0	0
T53	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690561	319458487	0	0
T1	563767	558504	0	0
T2	15996	1950	0	0
T3	17971	9187	0	0
T4	800991	800927	0	0
T5	763259	222964	0	0
T6	83685	75185	0	0
T7	14682	2076	0	0
T8	811746	498155	0	0
T18	83166	3254	0	0
T19	100386	100307	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	533	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	3	0	0
T6	83685	1	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	17623	0	0	0
T16	0	4	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	12729	1	0	0
T22	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	523	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	3	0	0
T6	83685	1	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	17623	0	0	0
T16	0	4	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	12729	1	0	0
T22	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	515	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	3	0	0
T6	83685	1	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	17623	0	0	0
T16	0	4	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	12729	1	0	0
T22	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	508	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	3	0	0
T6	83685	1	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	17623	0	0	0
T16	0	4	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	12729	1	0	0
T22	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	1260	0	0
T2	15996	3	0	0
T3	17971	0	0	0
T4	800991	0	0	0
T5	763259	282	0	0
T6	83685	1	0	0
T7	14682	0	0	0
T8	811746	0	0	0
T16	0	46	0	0
T17	0	1	0	0
T18	83166	0	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T22	0	3	0	0
T24	0	3	0	0
T27	0	35	0	0
T37	0	4	0	0
T64	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	170087	0	0
T2	15996	320	0	0
T3	17971	0	0	0
T4	800991	0	0	0
T5	763259	51705	0	0
T6	83685	127	0	0
T7	14682	0	0	0
T8	811746	0	0	0
T16	0	6555	0	0
T17	0	26	0	0
T18	83166	0	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T22	0	833	0	0
T24	0	1131	0	0
T27	0	6398	0	0
T37	0	265	0	0
T64	0	93	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	1173	0	0
T2	15996	3	0	0
T3	17971	0	0	0
T4	800991	0	0	0
T5	763259	281	0	0
T6	83685	0	0	0
T7	14682	0	0	0
T8	811746	0	0	0
T16	0	44	0	0
T17	0	1	0	0
T18	83166	0	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T22	0	2	0	0
T24	0	1	0	0
T27	0	33	0	0
T37	0	2	0	0
T53	0	1	0	0
T64	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	58	0	0
T5	763259	1	0	0
T6	83685	1	0	0
T8	811746	0	0	0
T9	138825	0	0	0
T13	17623	0	0	0
T16	0	2	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	1	0	0
T24	0	2	0	0
T27	0	1	0	0
T32	1353	0	0	0
T37	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T85	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	1111	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	186	0	0
T14	0	191	0	0
T15	0	359	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	180	0	0
T31	0	195	0	0
T32	1353	0	0	0
T33	1807	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	931	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	156	0	0
T14	0	161	0	0
T15	0	299	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	150	0	0
T31	0	165	0	0
T32	1353	0	0	0
T33	1807	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687686703	687616700	0	0
T1	563767	563695	0	0
T2	15996	15916	0	0
T3	17971	17902	0	0
T4	800991	800928	0	0
T5	763259	763244	0	0
T6	83685	83607	0	0
T7	14682	14628	0	0
T8	811746	811661	0	0
T18	83166	83085	0	0
T19	100386	100308	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	687700798	0	0
T1	563767	563695	0	0
T2	15996	15916	0	0
T3	17971	17902	0	0
T4	800991	800928	0	0
T5	763259	763244	0	0
T6	83685	83607	0	0
T7	14682	14628	0	0
T8	811746	811661	0	0
T18	83166	83085	0	0
T19	100386	100308	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T7,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T7
1	0	1	Covered	T4,T5,T16
1	1	0	Covered	T2,T18,T5
1	1	1	Covered	T7,T5,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T7,T5,T6
0	1	Covered	T7,T5,T6
1	0	Covered	T5,T64,T63

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T7,T5,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T64,T63

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T5,T6
1	0	Not Covered
1	1	Covered	T7,T5,T6

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T7,T6,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T4
1	Covered	T5,T19,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T4
1	Covered	T22,T34,T94

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T5,T19
1	Covered	T3,T4,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T7,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T7,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T7,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T7,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T7,T4
Phase1St	198	Covered	T3,T7,T4
Phase2St	215	Covered	T3,T7,T4
Phase3St	233	Covered	T3,T7,T4
TerminalSt	249	Covered	T3,T7,T4
TimeoutSt	159	Covered	T7,T5,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T3,T4,T5
IdleSt->TimeoutSt	159	Covered	T7,T5,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T6,T95,T96
Phase0St->Phase1St	198	Covered	T3,T7,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T83,T97,T98
Phase1St->Phase2St	215	Covered	T3,T7,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T99,T45,T26
Phase2St->Phase3St	233	Covered	T3,T7,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T100,T40,T101
Phase3St->TerminalSt	249	Covered	T3,T7,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T5,T22,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T6,T22
TimeoutSt->Phase0St	172	Covered	T7,T5,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T5,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T5,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T5,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T6,T95,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T7,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T7,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T83,T97,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T7,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T7,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T99,T45,T26
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T7,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T7,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T100,T40,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T7,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T7,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T16,T34,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T7,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	687847418	202	0	0
CheckAccumTrig0_A	687847418	498	0	0
CheckAccumTrig1_A	687847418	28	0	0
CheckClr_A	687847418	199	0	0
CheckEn_A	687690561	313534005	0	0
CheckPhase0_A	687847418	578	0	0
CheckPhase1_A	687847418	570	0	0
CheckPhase2_A	687847418	559	0	0
CheckPhase3_A	687847418	550	0	0
CheckTimeout0_A	687847418	519	0	0
CheckTimeoutSt1_A	687847418	71676	0	0
CheckTimeoutSt2_A	687847418	431	0	0
CheckTimeoutStTrig_A	687847418	59	0	0
ErrorStAllEscAsserted_A	687847418	1060	0	0
ErrorStIsTerminal_A	687847418	880	0	0
EscStateOut_A	687686703	687616700	0	0
u_state_regs_A	687847418	687700798	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	202	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	29	0	0
T14	0	42	0	0
T15	0	63	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	30	0	0
T31	0	38	0	0
T32	1353	0	0	0
T33	1807	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	498	0	0
T3	17971	1	0	0
T4	800991	1	0	0
T5	763259	3	0	0
T6	83685	0	0	0
T7	14682	0	0	0
T8	811746	0	0	0
T13	17623	0	0	0
T16	0	8	0	0
T17	0	1	0	0
T18	83166	0	0	0
T19	100386	1	0	0
T20	12729	1	0	0
T22	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	28	0	0
T5	763259	1	0	0
T6	83685	0	0	0
T8	811746	0	0	0
T9	138825	0	0	0
T13	17623	0	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T26	0	1	0	0
T32	1353	0	0	0
T38	0	2	0	0
T40	0	3	0	0
T63	0	1	0	0
T64	0	2	0	0
T66	0	1	0	0
T71	0	1	0	0
T100	0	1	0	0
T103	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	199	0	0
T6	83685	1	0	0
T8	811746	0	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T12	738082	0	0	0
T13	17623	0	0	0
T16	0	3	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T24	0	1	0	0
T27	0	1	0	0
T28	0	1	0	0
T32	1353	0	0	0
T34	0	1	0	0
T37	0	3	0	0
T64	0	3	0	0
T104	0	1	0	0
T105	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690561	313534005	0	0
T1	563767	563694	0	0
T2	15996	13050	0	0
T3	17971	3836	0	0
T4	800991	30415	0	0
T5	763259	142617	0	0
T6	83685	8352	0	0
T7	14682	11504	0	0
T8	811746	177362	0	0
T18	83166	83084	0	0
T19	100386	594	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	578	0	0
T3	17971	1	0	0
T4	800991	1	0	0
T5	763259	5	0	0
T6	83685	0	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T13	17623	0	0	0
T16	0	8	0	0
T17	0	1	0	0
T18	83166	0	0	0
T19	100386	1	0	0
T20	12729	1	0	0
T22	0	3	0	0
T34	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	570	0	0
T3	17971	1	0	0
T4	800991	1	0	0
T5	763259	5	0	0
T6	83685	0	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T13	17623	0	0	0
T16	0	8	0	0
T17	0	1	0	0
T18	83166	0	0	0
T19	100386	1	0	0
T20	12729	1	0	0
T22	0	3	0	0
T34	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	559	0	0
T3	17971	1	0	0
T4	800991	1	0	0
T5	763259	5	0	0
T6	83685	0	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T13	17623	0	0	0
T16	0	8	0	0
T17	0	1	0	0
T18	83166	0	0	0
T19	100386	1	0	0
T20	12729	1	0	0
T22	0	3	0	0
T34	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	550	0	0
T3	17971	1	0	0
T4	800991	1	0	0
T5	763259	5	0	0
T6	83685	0	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T13	17623	0	0	0
T16	0	8	0	0
T17	0	1	0	0
T18	83166	0	0	0
T19	100386	1	0	0
T20	12729	1	0	0
T22	0	3	0	0
T34	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	519	0	0
T4	800991	0	0	0
T5	763259	3	0	0
T6	83685	8	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T13	17623	0	0	0
T18	83166	0	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	0	2	0	0
T24	0	1	0	0
T27	0	62	0	0
T36	0	1	0	0
T63	0	5	0	0
T64	0	3	0	0
T66	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	71676	0	0
T4	800991	0	0	0
T5	763259	307	0	0
T6	83685	2032	0	0
T7	14682	150	0	0
T8	811746	0	0	0
T13	17623	0	0	0
T18	83166	0	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	0	433	0	0
T24	0	96	0	0
T27	0	10613	0	0
T36	0	544	0	0
T63	0	93	0	0
T64	0	109	0	0
T66	0	174	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	431	0	0
T5	763259	1	0	0
T6	83685	7	0	0
T8	811746	0	0	0
T9	138825	0	0	0
T13	17623	0	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	2	0	0
T27	0	61	0	0
T32	1353	0	0	0
T37	0	4	0	0
T60	0	1	0	0
T63	0	4	0	0
T64	0	1	0	0
T66	0	1	0	0
T67	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	59	0	0
T4	800991	0	0	0
T5	763259	1	0	0
T6	83685	1	0	0
T7	14682	1	0	0
T8	811746	0	0	0
T13	17623	0	0	0
T18	83166	0	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T24	0	1	0	0
T27	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T75	0	1	0	0
T100	0	1	0	0
T105	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	1060	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	200	0	0
T14	0	180	0	0
T15	0	350	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	169	0	0
T31	0	161	0	0
T32	1353	0	0	0
T33	1807	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	880	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	170	0	0
T14	0	150	0	0
T15	0	290	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	139	0	0
T31	0	131	0	0
T32	1353	0	0	0
T33	1807	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687686703	687616700	0	0
T1	563767	563695	0	0
T2	15996	15916	0	0
T3	17971	17902	0	0
T4	800991	800928	0	0
T5	763259	763244	0	0
T6	83685	83607	0	0
T7	14682	14628	0	0
T8	811746	811661	0	0
T18	83166	83085	0	0
T19	100386	100308	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	687700798	0	0
T1	563767	563695	0	0
T2	15996	15916	0	0
T3	17971	17902	0	0
T4	800991	800928	0	0
T5	763259	763244	0	0
T6	83685	83607	0	0
T7	14682	14628	0	0
T8	811746	811661	0	0
T18	83166	83085	0	0
T19	100386	100308	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T18
1	0	1	Covered	T1,T4,T19
1	1	0	Covered	T3,T7,T18
1	1	1	Covered	T2,T3,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T18
0	1	Covered	T5,T16,T27
1	0	Covered	T18,T24,T41

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T24,T41

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T18
1	0	Covered	T25,T106
1	1	Covered	T5,T16,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T18,T5
1	Covered	T5,T22,T10

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T18,T5,T20
1	Covered	T4,T5,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T19
1	Covered	T18,T5,T22

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T18,T5
1	Covered	T5,T22,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T5,T22,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T4,T18,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T5,T19,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T4,T5,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T18,T5
Phase1St	198	Covered	T4,T18,T5
Phase2St	215	Covered	T4,T18,T5
Phase3St	233	Covered	T4,T18,T5
TerminalSt	249	Covered	T4,T18,T5
TimeoutSt	159	Covered	T2,T3,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T4,T5,T19
IdleSt->TimeoutSt	159	Covered	T2,T3,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T8,T10,T36
Phase0St->Phase1St	198	Covered	T4,T18,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T20,T10,T54
Phase1St->Phase2St	215	Covered	T4,T18,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T29,T45,T47
Phase2St->Phase3St	233	Covered	T4,T18,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T40,T45,T107
Phase3St->TerminalSt	249	Covered	T4,T18,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T5,T22,T10
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T3,T18
TimeoutSt->Phase0St	172	Covered	T18,T5,T16

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T5,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T8,T10,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T18,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T18,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T10,T54
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T18,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T18,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T29,T45,T101
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T18,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T18,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T40,T45,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T18,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T18,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T22,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T18,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	687847418	201	0	0
CheckAccumTrig0_A	687847418	903	0	0
CheckAccumTrig1_A	687847418	47	0	0
CheckClr_A	687847418	454	0	0
CheckEn_A	687690561	247449137	0	0
CheckPhase0_A	687847418	1007	0	0
CheckPhase1_A	687847418	987	0	0
CheckPhase2_A	687847418	963	0	0
CheckPhase3_A	687847418	949	0	0
CheckTimeout0_A	687847418	529	0	0
CheckTimeoutSt1_A	687847418	70450	0	0
CheckTimeoutSt2_A	687847418	400	0	0
CheckTimeoutStTrig_A	687847418	81	0	0
ErrorStAllEscAsserted_A	687847418	1076	0	0
ErrorStIsTerminal_A	687847418	896	0	0
EscStateOut_A	687686703	687616700	0	0
u_state_regs_A	687847418	687700798	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	201	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	44	0	0
T14	0	34	0	0
T15	0	60	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	38	0	0
T31	0	25	0	0
T32	1353	0	0	0
T33	1807	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	903	0	0
T4	800991	1	0	0
T5	763259	8	0	0
T6	83685	0	0	0
T8	811746	1	0	0
T10	0	5	0	0
T11	0	2	0	0
T13	17623	0	0	0
T16	0	7	0	0
T17	0	1	0	0
T18	83166	0	0	0
T19	100386	1	0	0
T20	12729	1	0	0
T21	5243	0	0	0
T22	429086	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	47	0	0
T5	763259	0	0	0
T6	83685	0	0	0
T8	811746	0	0	0
T13	17623	0	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T24	0	1	0	0
T26	0	1	0	0
T32	1353	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	8	0	0
T46	0	1	0	0
T48	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	454	0	0
T5	763259	3	0	0
T6	83685	0	0	0
T8	811746	1	0	0
T9	138825	0	0	0
T10	0	4	0	0
T11	0	1	0	0
T13	17623	0	0	0
T19	100386	0	0	0
T20	12729	1	0	0
T21	5243	0	0	0
T22	429086	1	0	0
T24	0	1	0	0
T32	1353	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T62	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690561	247449137	0	0
T1	563767	558515	0	0
T2	15996	3024	0	0
T3	17971	15476	0	0
T4	800991	621	0	0
T5	763259	566436	0	0
T6	83685	70050	0	0
T7	14682	14627	0	0
T8	811746	789289	0	0
T18	83166	8948	0	0
T19	100386	2631	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	1007	0	0
T4	800991	1	0	0
T5	763259	9	0	0
T6	83685	0	0	0
T8	811746	0	0	0
T10	0	4	0	0
T11	0	2	0	0
T13	17623	0	0	0
T16	0	8	0	0
T17	0	1	0	0
T18	83166	1	0	0
T19	100386	1	0	0
T20	12729	1	0	0
T21	5243	0	0	0
T22	429086	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	987	0	0
T4	800991	1	0	0
T5	763259	9	0	0
T6	83685	0	0	0
T8	811746	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	17623	0	0	0
T16	0	8	0	0
T17	0	1	0	0
T18	83166	1	0	0
T19	100386	1	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	5	0	0
T34	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	963	0	0
T4	800991	1	0	0
T5	763259	9	0	0
T6	83685	0	0	0
T8	811746	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	17623	0	0	0
T16	0	8	0	0
T17	0	1	0	0
T18	83166	1	0	0
T19	100386	1	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	5	0	0
T34	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	949	0	0
T4	800991	1	0	0
T5	763259	9	0	0
T6	83685	0	0	0
T8	811746	0	0	0
T10	0	3	0	0
T11	0	2	0	0
T13	17623	0	0	0
T16	0	8	0	0
T17	0	1	0	0
T18	83166	1	0	0
T19	100386	1	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	5	0	0
T34	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	529	0	0
T2	15996	4	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	4	0	0
T6	83685	2	0	0
T7	14682	0	0	0
T8	811746	0	0	0
T16	0	2	0	0
T18	83166	2	0	0
T19	100386	0	0	0
T20	12729	1	0	0
T21	0	1	0	0
T24	0	2	0	0
T65	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	70450	0	0
T2	15996	440	0	0
T3	17971	175	0	0
T4	800991	0	0	0
T5	763259	802	0	0
T6	83685	523	0	0
T7	14682	0	0	0
T8	811746	0	0	0
T16	0	176	0	0
T18	83166	93	0	0
T19	100386	0	0	0
T20	12729	39	0	0
T21	0	41	0	0
T24	0	93	0	0
T65	0	77	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	400	0	0
T2	15996	4	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	3	0	0
T6	83685	2	0	0
T7	14682	0	0	0
T8	811746	0	0	0
T16	0	1	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	12729	1	0	0
T21	0	1	0	0
T24	0	1	0	0
T65	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	81	0	0
T5	763259	1	0	0
T6	83685	0	0	0
T8	811746	0	0	0
T9	138825	0	0	0
T13	17623	0	0	0
T16	0	1	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T25	0	1	0	0
T27	0	4	0	0
T32	1353	0	0	0
T40	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	1076	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	197	0	0
T14	0	170	0	0
T15	0	349	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	186	0	0
T31	0	174	0	0
T32	1353	0	0	0
T33	1807	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	896	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	167	0	0
T14	0	140	0	0
T15	0	289	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	156	0	0
T31	0	144	0	0
T32	1353	0	0	0
T33	1807	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687686703	687616700	0	0
T1	563767	563695	0	0
T2	15996	15916	0	0
T3	17971	17902	0	0
T4	800991	800928	0	0
T5	763259	763244	0	0
T6	83685	83607	0	0
T7	14682	14628	0	0
T8	811746	811661	0	0
T18	83166	83085	0	0
T19	100386	100308	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	687700798	0	0
T1	563767	563695	0	0
T2	15996	15916	0	0
T3	17971	17902	0	0
T4	800991	800928	0	0
T5	763259	763244	0	0
T6	83685	83607	0	0
T7	14682	14628	0	0
T8	811746	811661	0	0
T18	83166	83085	0	0
T19	100386	100308	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T18
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T2,T18,T5
1	1	1	Covered	T2,T3,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T5
0	1	Covered	T5,T16,T24
1	0	Covered	T5,T36,T38

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T36,T38

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T16,T26
1	1	Covered	T5,T16,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T8
1	Covered	T3,T7,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T5,T22,T16

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T18
1	Covered	T1,T5,T8

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T5,T12,T24

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T13,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T7,T5,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T7,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T3,T7,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T7,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T13,T14,T15
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T7
Phase1St	198	Covered	T1,T3,T7
Phase2St	215	Covered	T1,T3,T7
Phase3St	233	Covered	T1,T3,T7
TerminalSt	249	Covered	T1,T3,T7
TimeoutSt	159	Covered	T2,T3,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T13,T14,T15
IdleSt->Phase0St	152	Covered	T1,T3,T7
IdleSt->TimeoutSt	159	Covered	T2,T3,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T49,T108,T109
Phase0St->Phase1St	198	Covered	T1,T3,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T12,T50,T110
Phase1St->Phase2St	215	Covered	T1,T3,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T28,T40
Phase2St->Phase3St	233	Covered	T1,T3,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T28,T111,T112
Phase3St->TerminalSt	249	Covered	T1,T3,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T5,T8,T22
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T2,T3,T5
TimeoutSt->Phase0St	172	Covered	T5,T16,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T16,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T49,T109,T113
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T12,T50,T110
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T28,T40
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T111,T112
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T8,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T15

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	687847418	209	0	0
CheckAccumTrig0_A	687847418	533	0	0
CheckAccumTrig1_A	687847418	25	0	0
CheckClr_A	687847418	251	0	0
CheckEn_A	687690561	329717972	0	0
CheckPhase0_A	687847418	608	0	0
CheckPhase1_A	687847418	601	0	0
CheckPhase2_A	687847418	586	0	0
CheckPhase3_A	687847418	575	0	0
CheckTimeout0_A	687847418	1662	0	0
CheckTimeoutSt1_A	687847418	185714	0	0
CheckTimeoutSt2_A	687847418	1579	0	0
CheckTimeoutStTrig_A	687847418	56	0	0
ErrorStAllEscAsserted_A	687847418	1104	0	0
ErrorStIsTerminal_A	687847418	924	0	0
EscStateOut_A	687686703	687616700	0	0
u_state_regs_A	687847418	687700798	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	209	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	39	0	0
T14	0	38	0	0
T15	0	57	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	45	0	0
T31	0	30	0	0
T32	1353	0	0	0
T33	1807	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	533	0	0
T1	563767	1	0	0
T2	15996	0	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	4	0	0
T6	83685	0	0	0
T7	14682	1	0	0
T8	811746	1	0	0
T9	0	1	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	0	1	0	0
T22	0	7	0	0
T32	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	25	0	0
T5	763259	1	0	0
T6	83685	0	0	0
T8	811746	0	0	0
T9	138825	0	0	0
T13	17623	0	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T32	1353	0	0	0
T36	0	1	0	0
T38	0	3	0	0
T40	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T52	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	251	0	0
T5	763259	4	0	0
T6	83685	0	0	0
T8	811746	1	0	0
T9	138825	0	0	0
T12	0	1	0	0
T13	17623	0	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	4	0	0
T27	0	1	0	0
T32	1353	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T60	0	1	0	0
T63	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687690561	329717972	0	0
T1	563767	17858	0	0
T2	15996	3729	0	0
T3	17971	3782	0	0
T4	800991	625	0	0
T5	763259	239260	0	0
T6	83685	78469	0	0
T7	14682	2065	0	0
T8	811746	741663	0	0
T18	83166	22913	0	0
T19	100386	100307	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	608	0	0
T1	563767	1	0	0
T2	15996	0	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	8	0	0
T6	83685	0	0	0
T7	14682	1	0	0
T8	811746	1	0	0
T9	0	1	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	0	1	0	0
T22	0	7	0	0
T32	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	601	0	0
T1	563767	1	0	0
T2	15996	0	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	8	0	0
T6	83685	0	0	0
T7	14682	1	0	0
T8	811746	1	0	0
T9	0	1	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	0	1	0	0
T22	0	7	0	0
T32	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	586	0	0
T1	563767	1	0	0
T2	15996	0	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	7	0	0
T6	83685	0	0	0
T7	14682	1	0	0
T8	811746	1	0	0
T9	0	1	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	0	1	0	0
T22	0	7	0	0
T32	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	575	0	0
T1	563767	1	0	0
T2	15996	0	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	7	0	0
T6	83685	0	0	0
T7	14682	1	0	0
T8	811746	1	0	0
T9	0	1	0	0
T18	83166	1	0	0
T19	100386	0	0	0
T20	0	1	0	0
T22	0	7	0	0
T32	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	1662	0	0
T2	15996	3	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	212	0	0
T6	83685	0	0	0
T7	14682	0	0	0
T8	811746	0	0	0
T16	0	68	0	0
T18	83166	0	0	0
T19	100386	0	0	0
T20	12729	1	0	0
T24	0	1	0	0
T27	0	14	0	0
T36	0	5	0	0
T37	0	1	0	0
T66	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	185714	0	0
T2	15996	269	0	0
T3	17971	226	0	0
T4	800991	0	0	0
T5	763259	36865	0	0
T6	83685	0	0	0
T7	14682	0	0	0
T8	811746	0	0	0
T16	0	10439	0	0
T18	83166	0	0	0
T19	100386	0	0	0
T20	12729	59	0	0
T24	0	15	0	0
T27	0	3163	0	0
T36	0	527	0	0
T37	0	173	0	0
T66	0	140	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	1579	0	0
T2	15996	3	0	0
T3	17971	1	0	0
T4	800991	0	0	0
T5	763259	208	0	0
T6	83685	0	0	0
T7	14682	0	0	0
T8	811746	0	0	0
T16	0	66	0	0
T18	83166	0	0	0
T19	100386	0	0	0
T20	12729	1	0	0
T25	0	1	0	0
T27	0	11	0	0
T36	0	4	0	0
T37	0	1	0	0
T66	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	56	0	0
T5	763259	3	0	0
T6	83685	0	0	0
T8	811746	0	0	0
T9	138825	0	0	0
T13	17623	0	0	0
T16	0	2	0	0
T19	100386	0	0	0
T20	12729	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T24	0	1	0	0
T27	0	3	0	0
T32	1353	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	1104	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	189	0	0
T14	0	175	0	0
T15	0	374	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	178	0	0
T31	0	188	0	0
T32	1353	0	0	0
T33	1807	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	924	0	0
T9	138825	0	0	0
T10	225746	0	0	0
T11	282995	0	0	0
T12	738082	0	0	0
T13	17623	159	0	0
T14	0	145	0	0
T15	0	314	0	0
T16	411074	0	0	0
T21	5243	0	0	0
T22	429086	0	0	0
T30	0	148	0	0
T31	0	158	0	0
T32	1353	0	0	0
T33	1807	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687686703	687616700	0	0
T1	563767	563695	0	0
T2	15996	15916	0	0
T3	17971	17902	0	0
T4	800991	800928	0	0
T5	763259	763244	0	0
T6	83685	83607	0	0
T7	14682	14628	0	0
T8	811746	811661	0	0
T18	83166	83085	0	0
T19	100386	100308	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	687847418	687700798	0	0
T1	563767	563695	0	0
T2	15996	15916	0	0
T3	17971	17902	0	0
T4	800991	800928	0	0
T5	763259	763244	0	0
T6	83685	83607	0	0
T7	14682	14628	0	0
T8	811746	811661	0	0
T18	83166	83085	0	0
T19	100386	100308	0	0