Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	87816	1			T20	3288		T13	4884		T9	1
class_i[0x1]	75324	1			T3	2		T5	15		T20	1558
class_i[0x2]	48801	1			T3	1		T19	30		T6	9
class_i[0x3]	73413	1			T3	1		T19	58		T6	65

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	70944	1			T3	1		T5	7		T19	49
alert[0x1]	70820	1			T3	2		T19	17		T6	31
alert[0x2]	68688	1			T3	1		T5	8		T19	11
alert[0x3]	74902	1			T19	11		T6	23		T20	1551

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

285103

1

T5

15

T19

88

T6

74

esc_ping_fail

251

1

T3

4

T8

8

T9

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	70873	1			T5	7		T19	49		T6	4
esc_integrity_fail	alert[0x1]	70746	1			T19	17		T6	31		T20	1086
esc_integrity_fail	alert[0x2]	68632	1			T5	8		T19	11		T6	16
esc_integrity_fail	alert[0x3]	74852	1			T19	11		T6	23		T20	1551
esc_ping_fail	alert[0x0]	71	1			T3	1		T8	3		T9	1
esc_ping_fail	alert[0x1]	74	1			T3	2		T8	3		T9	1
esc_ping_fail	alert[0x2]	56	1			T3	1		T69	1		T248	2
esc_ping_fail	alert[0x3]	50	1			T8	2		T248	4		T251	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	87763	1			T20	3288		T13	4884		T9	1
esc_integrity_fail	class_i[0x1]	75232	1			T5	15		T20	1558		T8	15
esc_integrity_fail	class_i[0x2]	48736	1			T19	30		T6	9		T15	205
esc_integrity_fail	class_i[0x3]	73372	1			T19	58		T6	65		T16	584
esc_ping_fail	class_i[0x0]	53	1			T292	6		T313	1		T314	1
esc_ping_fail	class_i[0x1]	92	1			T3	2		T8	8		T258	8
esc_ping_fail	class_i[0x2]	65	1			T3	1		T9	2		T248	9
esc_ping_fail	class_i[0x3]	41	1			T3	1		T69	3		T338	1